3 ['cache_20and_20branch_20predictor_20maintenance_20operations_0',['Cache and branch predictor maintenance operations',['../group__CMSIS__CBPM.html',1,'']]],
4 ['cbar_20bits_1',['CBAR Bits',['../group__CMSIS__CBAR__BITS.html',1,'']]],
5 ['cmsis_20core_20intrinsics_2',['CMSIS Core Intrinsics',['../group__CMSIS__Core__intrinsics.html',1,'']]],
6 ['cmsis_20core_20register_20access_20functions_3',['CMSIS Core Register Access Functions',['../group__CMSIS__Core__RegAccFunctions.html',1,'']]],
7 ['cmsis_20simd_20intrinsics_4',['CMSIS SIMD Intrinsics',['../group__CMSIS__SIMD__intrinsics.html',1,'']]],
8 ['compiler_20control_5',['Compiler Control',['../group__comp__cntrl__gr.html',1,'']]],
9 ['configuration_20base_20address_20register_20_28cbar_29_6',['Configuration Base Address Register (CBAR)',['../group__CMSIS__CBAR.html',1,'']]],
10 ['coprocessor_20access_20control_20register_20_28cpacr_29_7',['Coprocessor Access Control Register (CPACR)',['../group__CMSIS__CPACR.html',1,'']]],
11 ['core_20peripherals_8',['Core Peripherals',['../group__CMSIS__Core__FunctionInterface.html',1,'']]],
12 ['core_20register_20access_9',['Core Register Access',['../group__CMSIS__core__register.html',1,'']]],
13 ['counter_20frequency_20register_20_28cntfrq_29_10',['Counter Frequency register (CNTFRQ)',['../group__CMSIS__CNTFRQ.html',1,'']]],
14 ['cpacr_20bits_11',['CPACR Bits',['../group__CMSIS__CPACR__BITS.html',1,'']]],
15 ['cpacr_20cp_20field_20values_12',['CPACR CP field values',['../group__CMSIS__CPACR__CP.html',1,'']]],
16 ['cpsr_20bits_13',['CPSR Bits',['../group__CMSIS__CPSR__BITS.html',1,'']]],
17 ['cpsr_20m_20field_20values_14',['CPSR M field values',['../group__CMSIS__CPSR__M.html',1,'']]],
18 ['current_20program_20status_20register_20_28cpsr_29_15',['Current Program Status Register (CPSR)',['../group__CMSIS__CPSR.html',1,'']]]