3 ['radis_0',['RADIS',['../unionACTLR__Type.html#a7921e6e73e0841402a5519f09e6e2ef3',1,'ACTLR_Type']]],
4 ['raw_5fint_5fstatus_1',['RAW_INT_STATUS',['../structL2C__310__TypeDef.html#a404f8453b6df3aaf5f3db4ff9b658637',1,'L2C_310_TypeDef']]],
5 ['read_2',['READ',['../core__ca_8h.html#ga2ee598252f996e4f96640b096291d280acb9be765f361bb7efb9073730aac92c6',1,'core_ca.h']]],
6 ['ref_5fcache_2etxt_3',['ref_cache.txt',['../ref__cache_8txt.html',1,'']]],
7 ['ref_5fcore_5fregister_2etxt_4',['ref_core_register.txt',['../ref__core__register_8txt.html',1,'']]],
8 ['ref_5fgic_2etxt_5',['ref_gic.txt',['../ref__gic_8txt.html',1,'']]],
9 ['ref_5fmmu_2etxt_6',['ref_mmu.txt',['../ref__mmu_8txt.html',1,'']]],
10 ['ref_5fsystemandclock_2etxt_7',['Ref_SystemAndClock.txt',['../Ref__SystemAndClock_8txt.html',1,'']]],
11 ['ref_5ftimer_2etxt_8',['ref_timer.txt',['../ref__timer_8txt.html',1,'']]],
12 ['reserved_9',['RESERVED',['../core__ca_8h.html#af7f66fda711fd46e157dbb6c1af88e04',1,'core_ca.h']]],
13 ['revision_20history_20of_20cmsis_2dcore_20_28cortex_2da_29_10',['Revision History of CMSIS-Core (Cortex-A)',['../rev_histCoreA.html',1,'']]],
14 ['rg_5ft_11',['rg_t',['../structmmu__region__attributes__Type.html#a3f9d884c340aca62d3287b91809ac262',1,'mmu_region_attributes_Type']]],
15 ['rpr_12',['RPR',['../structGICInterface__Type.html#a37762d42768ecb3d1302f34abc7f2821',1,'GICInterface_Type']]],
16 ['rr_13',['RR',['../unionSCTLR__Type.html#a10212a8d038bb1e076cbd06a5ba0b055',1,'SCTLR_Type']]],
17 ['rsdis_14',['RSDIS',['../unionACTLR__Type.html#a91288f7320d267d76b4aad4adcf8cda3',1,'ACTLR_Type']]],
18 ['rw_15',['RW',['../core__ca_8h.html#ga2ee598252f996e4f96640b096291d280aec2497e0c8af01c04bec31ec0d1d7847',1,'core_ca.h']]]