/** \mainpage Overview

CMSIS-Core (Cortex-M) implements the basic run-time system for a Cortex-M device and gives the user access to the processor core and the device peripherals.
In detail it defines:
 - <b>Hardware Abstraction Layer (HAL)</b> for Cortex-M processor registers with standardized  definitions for the SysTick, NVIC, System Control Block registers, MPU registers, FPU registers, and core access functions.
 - <b>System exception names</b> to interface to system exceptions without having compatibility issues.
 - <b>Methods to organize header files</b> that makes it easy to learn new Cortex-M microcontroller products and improve software portability. This includes naming conventions for device-specific interrupts.
 - <b>Methods for system initialization</b> to be used by each MCU vendor. For example, the standardized SystemInit() function is essential for configuring the clock system of the device.
 - <b>Intrinsic functions</b> used to generate CPU instructions that are not supported by standard C functions.
 - A variable to determine the <b>system clock frequency</b> which simplifies the setup the SysTick timer.


The following sections provide details about the CMSIS-Core (Cortex-M):
 - \ref using_pg describes the project setup and shows a simple program example.
\if ARMv8M
 - \ref using_TrustZone_pg "Using TrustZone&reg; for Armv8-M" describes how to use the security extensions available in the Armv8-M architecture.
\endif
 - \ref templates_pg describes the files of the CMSIS-Core (Cortex-M) in detail and explains how to adapt template files provided by Arm to silicon vendor devices.
 - \ref coreMISRA_Exceptions_pg describes the violations to the MISRA standard.
 - <a href="modules.html">\b Reference </a> describe the features and functions of the \ref device_h_pg in detail.
 - <a href="annotated.html">\b Data \b Structures </a> describe the data structures of the \ref device_h_pg in detail.

<hr>

CMSIS-Core (Cortex-M) in ARM::CMSIS Pack
-----------------------------

Files relevant to CMSIS-Core (Cortex-M) are present in the following <b>ARM::CMSIS</b> directories:
|File/Folder                   |Content                                                                 |
|------------------------------|------------------------------------------------------------------------|
|\b CMSIS\\Documentation\\Core | This documentation                                                     |
|\b CMSIS\\Core\\Include       | CMSIS-Core (Cortex-M) header files (for example core_cm3.h, core_cmInstr.h, etc.) |
|\b Device                     | \ref using_ARM_pg "Arm reference implementations" of Cortex-M devices  |
|\b Device\\\_Template_Vendor  | \ref templates_pg for extension by silicon vendors                     |

<hr>

\section ref_v6-v8M Processor Support

CMSIS supports the complete range of <a href="https://developer.arm.com/products/processors/cortex-m" target="_blank"><b>Cortex-M processors</b></a> and
the <a href="https://developer.arm.com/architectures/cpu-architecture/m-profile" target="_blank"><b>Armv8-M/v8.1-M architecture</b></a> including security extensions.

\subsection ref_man_sec Cortex-M Generic User Guides

The Cortex-M Device Generic User Guides contain the programmers model and detailed information about the core peripherals and are available for:

- <a href="https://developer.arm.com/documentation/dui0497/latest/" target="_blank"><b>Cortex-M0 Devices Generic User Guide</b></a> (Armv6-M architecture)
- <a href="https://developer.arm.com/documentation/dui0662/latest/"  target="_blank"><b>Cortex-M0+ Devices Generic User Guide</b></a> (Armv6-M architecture)
- <a href="https://developer.arm.com/documentation/dui0552/latest/"  target="_blank"><b>Cortex-M3 Devices Generic User Guide</b></a> (Armv7-M architecture)
- <a href="https://developer.arm.com/documentation/dui0553/latest/"  target="_blank"><b>Cortex-M4 Devices Generic User Guide</b></a> (Armv7-M architecture)
- <a href="https://developer.arm.com/documentation/dui0646/latest/"  target="_blank"><b>Cortex-M7 Devices Generic User Guide</b></a> (Armv7-M architecture)
- <a href="https://developer.arm.com/documentation/dui1095/latest/"  target="_blank"><b>Cortex-M23 Devices Generic User Guide</b></a> (Armv8-M architecture)
- <a href="https://developer.arm.com/documentation/100235/latest/"   target="_blank"><b>Cortex-M33 Devices Generic User Guide</b></a> (Armv8-M architecture)
- <a href="https://developer.arm.com/documentation/101273/latest/"   target="_blank"><b>Cortex-M55 Devices Generic User Guide</b></a> (Armv8.1-M architecture)
- <a href="https://developer.arm.com/documentation/101928/latest"   target="_blank"><b>Cortex-M85 Devices Generic User Guide</b></a> (Armv8.1-M architecture)

CMSIS also supports the following Cortex-M processor variants:
- <a href="https://developer.arm.com/products/processors/cortex-m/cortex-m1"       target="_blank"><b>Cortex-M1</b></a> is a processor designed specifically for implementation in FPGAs (Armv6-M architecture).
- <a href="https://developer.arm.com/products/processors/cortex-m/sc000-processor" target="_blank"><b>SecurCore SC000</b></a> is designed specifically for smartcard and security applications (Armv6-M architecture).
- <a href="https://developer.arm.com/products/processors/cortex-m/sc300-processor" target="_blank"><b>SecurCore SC300</b></a> is designed specifically for smartcard and security applications (Armv7-M architecture).
- <a href="https://developer.arm.com/products/processors/cortex-m/cortex-m35p"     target="_blank"><b>Cortex-M35P</b></a> is a tamper resistant Cortex-M processor with optional software isolation using TrustZone for Armv8-M.
- <a href="https://www.armchina.com/mountain?infoId=160"                           target="_blank"><b>STAR-MC1</b></a> is a variant of Armv8-M with TrustZone designed by Arm China.


\subsection ARMv8M Armv8-M and Armv8.1-M Architecture

Armv8-M introduces two profiles \b baseline (for power and area constrained applications) and \b mainline (full-featured with optional SIMD, floating-point, and co-processor extensions).
Both Armv8-M profiles and Armv8.1-M are supported by CMSIS.

The Armv8-M architecture is described in the <a href="https://developer.arm.com/documentation/ddi0553/latest/" target="_blank"><b>Armv8-M Architecture Reference Manual</b></a>.

The Armv8.1-M architecture further extends Armv8-M with Helium (the so called M-Profile Vector Extension (MVE)), as well as further instruction set and debug extensions.
More information about Armv8.1-M architecture is available under <a href="https://developer.arm.com/technologies/helium" target="_blank"><b>Arm Helium technology</b></a>.

<hr>

\section tested_tools_sec Tested and Verified Toolchains

The \ref templates_pg supplied by Arm have been tested and verified with the following toolchains:
 - Arm: Arm Compiler 5.06 update 7 (not for Cortex-M23/33/35P/55/85, Armv8-M, Armv8.1-M)
 - Arm: Arm Compiler 6.16
 - Arm: Arm Compiler 6.6.4 (not for Cortex-M0/23/33/35P/55/85, Armv8-M, Armv8.1-M)
 - GNU: GNU Arm Embedded Toolchain 10-2020-q4-major (10.2.1 20201103)
 - IAR: IAR ANSI C/C++ Compiler for Arm 8.20.1.14183
*/
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
/**

\page core_revisionHistory Revision History of CMSIS-Core (Cortex-M)

<table class="cmtable" summary="Revision History">
    <tr>
      <th>Version</th>
      <th>Description</th>
    </tr>
    <tr>
      <td>V5.7.0</td>
      <td>
        <ul>
          <li>Added: Added new compiler macros __ALIAS and __NO_INIT</li>
        </ul>
      </td>
    </tr>
    <tr>
      <td>V5.6.0</td>
      <td>
        <ul>
          <li>Added: Arm Cortex-M85 cpu support</li>
          <li>Added: Arm China Star-MC1 cpu support</li>
          <li>Updated: system_ARMCM55.c</li>
        </ul>
      </td>
    </tr>
    <tr>
      <td>V5.5.0</td>
      <td>
        <ul>
          <li>Updated GCC LinkerDescription, GCC Assembler startup</li>
          <li>Added ARMv8-M Stack Sealing (to linker, startup) for toolchain ARM, GCC</li>
          <li>Changed C-Startup to default Startup.</li>
          </li>
            Updated Armv8-M Assembler startup to use GAS syntax<br>
            Note: Updating existing projects may need manual user interaction!
          </li>
        </ul>
      </td>
    </tr>
    <tr>
      <td>V5.4.0</td>
      <td>
        <ul>
\if ARMv8M
          <li>Added: Cortex-M55 cpu support</li>
          <li>Enhanced: MVE support for Armv8.1-MML</li>
\endif
          <li>Fixed: Device config define checks</li>
          <li>Added: L1 Cache functions for Armv7-M and later</li>
        </ul>
      </td>
    </tr>
    <tr>
      <td>V5.3.0</td>
      <td>
        <ul>
          <li>Added: Provisions for compiler-independent C startup code.</li>
        </ul>
      </td>
    </tr>
    <tr>
      <td>V5.2.1</td>
      <td>
        <ul>
          <li>Fixed: Compilation issue in cmsis_armclang_ltm.h introduced in 5.2.0</li>
        </ul>
      </td>
    </tr>
    <tr>
      <td>V5.2.0</td>
      <td>
        <ul>
          <li>Added: Cortex-M35P support.</li>
          <li>Added: Cortex-M1 support.
          <li>Added: Armv8.1 architecture support.
          <li>Added: \ref __RESTRICT and \ref __STATIC_FORCEINLINE compiler control macros.
        </ul>
      </td>
    </tr>
    <tr>
      <td>V5.1.2</td>
      <td>
        <ul>
          <li>Removed using get/set built-ins FPSCR in GCC >= 7.2 due to shortcomings.</li>
          <li>Added __NO_RETURN to __NVIC_SystemReset() to silence compiler warnings.</li>
          <li>Added support for Cortex-M1 (beta).</li>
          <li>Removed usage of register keyword.</li>
          <li>Added defines for EXC_RETURN, FNC_RETURN and integrity signature values.</li>
          <li>Enhanced MPUv7 API with defines for memory access attributes.</li>
        </ul>
      </td>
    </tr>
    <tr>
      <td>V5.1.1</td>
      <td>
        <ul>
          <li>Aligned MSPLIM and PSPLIM access functions along supported compilers.</li>
        </ul>
      </td>
    </tr>
    <tr>
      <td>V5.1.0</td>
      <td>
        <ul>
          <li>Added MPU Functions for ARMv8-M for Cortex-M23/M33.</li>
          <li>Moved __SSAT and __USAT intrinsics to CMSIS-Core.</li>
          <li>Aligned __REV, __REV16 and __REVSH intrinsics along supported compilers.</li>
        </ul>
      </td>
    </tr>
    <tr>
      <td>V5.0.2</td>
      <td>
        <ul>
          <li>Added macros  \ref \__UNALIGNED_UINT16_READ,  \ref \__UNALIGNED_UINT16_WRITE.</li>
          <li>Added macros  \ref \__UNALIGNED_UINT32_READ,  \ref \__UNALIGNED_UINT32_WRITE.</li>
          <li>Deprecated macro  \ref \__UNALIGNED_UINT32.</li>
          <li>Changed \ref version_control_gr macros to be core agnostic.</li>
          <li>Added \ref mpu_functions for Cortex-M0+/M3/M4/M7.</li>
        </ul>
      </td>
    </tr>
    <tr>
      <td>V5.0.1</td>
      <td>
        <ul>
          <li>Added: macro \ref \__PACKED_STRUCT.</li>
          <li>Added: uVisor support.</li>
        </ul>
      </td>
    </tr>
    <tr>
      <td>V5.00</td>
      <td>
        <ul>
          <li>Added: Cortex-M23, Cortex-M33 support.</li>
          <li>Added: macro __SAU_PRESENT with __SAU_REGION_PRESENT.</li>
          <li>Replaced: macro __SAU_PRESENT with __SAU_REGION_PRESENT.</li>
          <li>Reworked: SAU register and functions.</li>
          <li>Added: macro \ref \__ALIGNED.</li>
          <li>Updated: function \ref SCB_EnableICache.</li>
          <li>Added: cmsis_compiler.h with compiler specific CMSIS macros, functions, instructions.</li>
          <li>Added: macro \ref \__PACKED.</li>
          <li>Updated: compiler specific include files.</li>
          <li>Updated: core dependant include files.</li>
          <li>Removed: deprecated files core_cmfunc.h, core_cminstr.h, core_cmsimd.h.</li>
        </ul>
      </td>
    </tr>
    <tr>
      <td>V5.00<br>Beta 6</td>
      <td>
        <ul>
          <li>Added: SCB_CFSR register bit definitions.</li>
          <li>Added: function \ref NVIC_GetEnableIRQ.</li>
          <li>Updated: core instruction macros \ref \__NOP, \ref \__WFI, \ref \__WFE, \ref \__SEV for toolchain GCC.</li>
        </ul>
      </td>
    </tr>
    <tr>
      <td>V5.00<br>Beta 5</td>
      <td>
        <ul>
          <li>Moved: DSP libraries from CMSIS/DSP/Lib to CMSIS/Lib.</li>
          <li>Added: DSP libraries build projects to CMSIS pack.</li>
        </ul>
      </td>
    </tr>
    <tr>
      <td>V5.00<br>Beta 4</td>
      <td>
        <ul>
          <li>Updated: ARMv8M device files.</li>
          <li>Corrected: ARMv8MBL interrupts.</li>
          <li>Reworked: NVIC functions.</li>
        </ul>
      </td>
    </tr>
    <tr>
      <td>V5.00<br>Beta 2</td>
      <td>
        <ul>
\if ARMv8M
          <li>Changed: ARMv8M SAU regions to 8.</li>
          <li>Changed: moved function \ref TZ_SAU_Setup to file partition_&lt;device&gt;.h.</li>
\endif
          <li>Changed: license under Apache-2.0.</li>
          <li>Added: check if macro is defined before use.</li>
          <li>Corrected: function \ref SCB_DisableDCache.</li>
          <li>Corrected: macros \ref \_VAL2FLD, \ref \_FLD2VAL.</li>
          <li>Added: NVIC function virtualization with macros \ref CMSIS_NVIC_VIRTUAL and \ref CMSIS_VECTAB_VIRTUAL.</li>
        </ul>
      </td>
    </tr>
    <tr>
      <td>V5.00<br>Beta 1</td>
      <td>
        <ul>
          <li>Renamed: cmsis_armcc_V6.h to cmsis_armclang.h.</li>
          <li>Renamed: core\_*.h to lower case.</li>
          <li>Added: function \ref SCB_GetFPUType to all CMSIS cores.</li>
          <li>Added: ARMv8-M support.</li>
        </ul>
      </td>
    </tr>
    <tr>
      <td>V4.30</td>
      <td>
        <ul>
          <li>Corrected: DoxyGen function parameter comments.</li>
          <li>Corrected: IAR toolchain: removed for \ref NVIC_SystemReset the attribute(noreturn).</li>
          <li>Corrected: GCC toolchain: suppressed irrelevant compiler warnings.</li>
          <li>Added: Support files for Arm Compiler v6 (cmsis_armcc_v6.h).</li>
        </ul>
      </td>
    </tr>
    <tr>
      <td>V4.20</td>
      <td>
        <ul>
          <li>Corrected: MISRA-C:2004 violations.</li>
          <li>Corrected: predefined macro for TI CCS Compiler.</li>
          <li>Corrected: function \ref __SHADD16 in arm_math.h.</li>
          <li>Updated: cache functions for Cortex-M7.</li>
          <li>Added: macros \ref _VAL2FLD, \ref _FLD2VAL to core\_*.h.</li>
          <li>Updated: functions \ref __QASX, \ref __QSAX, \ref __SHASX, \ref __SHSAX.</li>
          <li>Corrected: potential bug in function \ref __SHADD16.</li>
        </ul>
      </td>
    </tr>
    <tr>
      <td>V4.10</td>
      <td>
        <ul>
          <li>Corrected: MISRA-C:2004 violations.</li>
          <li>Corrected: intrinsic functions \ref __DSB, \ref __DMB, \ref __ISB.</li>
          <li>Corrected: register definitions for ITCMCR register.</li>
          <li>Corrected: register definitions for \ref CONTROL_Type register.</li>
          <li>Added: functions \ref SCB_GetFPUType, \ref SCB_InvalidateDCache_by_Addr to core_cm7.h.</li>
          <li>Added: register definitions for \ref APSR_Type, \ref IPSR_Type, \ref xPSR_Type register.</li>
          <li>Added: \ref __set_BASEPRI_MAX function to core_cmFunc.h.</li>
          <li>Added: intrinsic functions \ref __RBIT, \ref __CLZ  for Cortex-M0/CortexM0+.</li>
        </ul>
      </td>
    </tr>
    <tr>
      <td>V4.00</td>
      <td>
        <ul>
          <li>Added: Cortex-M7 support.</li>
          <li>Added: intrinsic functions for \ref __RRX, \ref __LDRBT, \ref __LDRHT, \ref __LDRT, \ref __STRBT, \ref __STRHT, and \ref __STRT</li>
        </ul>
      </td>
    </tr>
    <tr>
      <td>V3.40</td>
      <td>
       <ul>
         <li>Corrected: C++ include guard settings.</li>
       </ul>
     </td>
    </tr>
    <tr>
      <td>V3.30</td>
      <td>
        <ul>
          <li>Added: COSMIC tool chain support.</li>
          <li>Corrected: GCC __SMLALDX instruction intrinsic for Cortex-M4.</li>
          <li>Corrected: GCC __SMLALD instruction intrinsic for Cortex-M4.</li>
          <li>Corrected: GCC/CLang warnings.</li>
        </ul>
      </td>
    </tr>
    <tr>
      <td>V3.20</td>
      <td>
        <ul>
          <li>Added: \ref __BKPT instruction intrinsic.</li>
          <li>Added: \ref __SMMLA instruction intrinsic for Cortex-M4.</li>
          <li>Corrected: \ref ITM_SendChar.</li>
          <li>Corrected: \ref __enable_irq, \ref __disable_irq and inline assembly for GCC Compiler.</li>
          <li>Corrected: \ref NVIC_GetPriority and VTOR_TBLOFF for Cortex-M0/M0+, SC000.</li>
          <li>Corrected: rework of in-line assembly functions to remove potential compiler warnings.</li>
        </ul>
      </td>
    </tr>
    <tr>
      <td>V3.01</td>
      <td>
       <ul>
         <li>Added support for Cortex-M0+ processor.</li>
       </ul>
     </td>
    </tr>
    <tr>
      <td>V3.00</td>
      <td>
        <ul>
          <li>Added support for GNU GCC ARM Embedded Compiler.</li>
          <li>Added function \ref __ROR.</li>
          <li>Added \ref regMap_pg for TPIU, DWT.</li>
          <li>Added support for \ref core_config_sect "SC000 and SC300 processors".</li>
          <li>Corrected \ref ITM_SendChar function.</li>
          <li>Corrected the functions \ref __STREXB, \ref __STREXH, \ref __STREXW for the GNU GCC compiler section.</li>
          <li>Documentation restructured.</li>
        </ul>
      </td>
    </tr>
    <tr>
      <td>V2.10</td>
      <td>
        <ul>
          <li>Updated documentation.</li>
          <li>Updated CMSIS core include files.</li>
          <li>Changed CMSIS/Device folder structure.</li>
          <li>Added support for Cortex-M0, Cortex-M4 w/o FPU to CMSIS DSP library.</li>
          <li>Reworked CMSIS DSP library examples.</li>
        </ul>
      </td>
    </tr>
    <tr>
      <td>V2.00</td>
      <td>
       <ul>
         <li>Added support for Cortex-M4 processor.</li>
       </ul>
     </td>
    </tr>
    <tr>
      <td>V1.30</td>
      <td>
        <ul>
          <li>Reworked Startup Concept.</li>
          <li>Added additional Debug Functionality.</li>
          <li>Changed folder structure.</li>
          <li>Added doxygen comments.</li>
          <li>Added definitions for bit.</li>
        </ul>
      </td>
    </tr>
    <tr>
      <td>V1.01</td>
      <td>
       <ul>
         <li>Added support for Cortex-M0 processor.</li>
       </ul>
      </td>
    </tr>
    <tr>
      <td>V1.01</td>
      <td>
       <ul>
         <li>Added intrinsic functions for \ref __LDREXB, \ref __LDREXH, \ref __LDREXW, \ref __STREXB, \ref __STREXH, \ref __STREXW, and \ref __CLREX</li>
       </ul>
     </td>
    </tr>
    <tr>
      <td>V1.00</td>
      <td>
       <ul>
         <li>Initial Release for Cortex-M3 processor.</li>
       </ul>
     </td>
    </tr>
</table>

*/