var searchData=
[
  ['radis_0',['RADIS',['../unionACTLR__Type.html#a7921e6e73e0841402a5519f09e6e2ef3',1,'ACTLR_Type']]],
  ['raw_5fint_5fstatus_1',['RAW_INT_STATUS',['../structL2C__310__TypeDef.html#a404f8453b6df3aaf5f3db4ff9b658637',1,'L2C_310_TypeDef']]],
  ['read_2',['READ',['../core__ca_8h.html#ga2ee598252f996e4f96640b096291d280acb9be765f361bb7efb9073730aac92c6',1,'core_ca.h']]],
  ['ref_5fcache_2etxt_3',['Ref_Cache.txt',['../Ref__Cache_8txt.html',1,'']]],
  ['ref_5fcompilercontrol_2etxt_4',['Ref_CompilerControl.txt',['../Ref__CompilerControl_8txt.html',1,'']]],
  ['ref_5fcoreregister_2etxt_5',['Ref_CoreRegister.txt',['../Ref__CoreRegister_8txt.html',1,'']]],
  ['ref_5fgic_2etxt_6',['Ref_GIC.txt',['../Ref__GIC_8txt.html',1,'']]],
  ['ref_5firqctrl_2etxt_7',['Ref_IRQCtrl.txt',['../Ref__IRQCtrl_8txt.html',1,'']]],
  ['ref_5fmmu_2etxt_8',['Ref_MMU.txt',['../Ref__MMU_8txt.html',1,'']]],
  ['ref_5fsystemandclock_2etxt_9',['Ref_SystemAndClock.txt',['../Ref__SystemAndClock_8txt.html',1,'']]],
  ['ref_5ftimer_2etxt_10',['Ref_Timer.txt',['../Ref__Timer_8txt.html',1,'']]],
  ['reserved_11',['RESERVED',['../core__ca_8h.html#af7f66fda711fd46e157dbb6c1af88e04',1,'core_ca.h']]],
  ['revision_20history_20of_20cmsis_2dcore_20_28cortex_2da_29_12',['Revision History of CMSIS-Core (Cortex-A)',['../rev_histCoreA.html',1,'']]],
  ['rg_5ft_13',['rg_t',['../structmmu__region__attributes__Type.html#a3f9d884c340aca62d3287b91809ac262',1,'mmu_region_attributes_Type']]],
  ['rpr_14',['RPR',['../structGICInterface__Type.html#a37762d42768ecb3d1302f34abc7f2821',1,'GICInterface_Type']]],
  ['rr_15',['RR',['../unionSCTLR__Type.html#a10212a8d038bb1e076cbd06a5ba0b055',1,'SCTLR_Type']]],
  ['rsdis_16',['RSDIS',['../unionACTLR__Type.html#a91288f7320d267d76b4aad4adcf8cda3',1,'ACTLR_Type']]],
  ['rw_17',['RW',['../core__ca_8h.html#ga2ee598252f996e4f96640b096291d280aec2497e0c8af01c04bec31ec0d1d7847',1,'core_ca.h']]]
];