CMSIS-Core (Cortex-A)  
CMSIS-Core support for Cortex-A processor-based devices
 
Loading...
Searching...
No Matches
Monitor Vector Base Address Register (MVBAR)
Core Register Access

The MVBAR holds the exception base address for all exceptions that are taken to Monitor mode.

Bits Name Function
[31:5] MVBA Bits[31:5] of the base address of the exception vectors for exceptions that are taken to Monitor mode.
[4:0] - Reserved.

Consider using __get_MVBAR and __set_MVBAR for accessing this register.