CMSIS-Core (Cortex-A)  
CMSIS-Core support for Cortex-A processor-based devices
 
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Cache and branch predictor maintenance operations

This section describes the cache and branch predictor maintenance operations.

Cache maintenance operations are defined to act on particular memory locations. In addition, for instruction caches and branch predictors, there are operations that invalidate all entries.

Consider using L1 Cache Functions and L2C-310 Cache Controller Functions for cache maintenance instead of raw register usage.