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Core A: cache: instr mva
authoryroeht <ranquet@lrde.epita.fr>
Tue, 4 Apr 2023 07:35:15 +0000 (09:35 +0200)
committerGitHub <noreply@github.com>
Tue, 4 Apr 2023 07:35:15 +0000 (09:35 +0200)
commit241b9d3b5e027c5839399e7b250d59d4f2ef6aa1
treecae1cacf62e03695813d74c0862576861b7d73eatree | snapshot
parent020f77f281f852b6f7a90ced825789a07c66cf04commit | diff
Core A: cache: instr mva

As documented by ARM at:
    https://developer.arm.com/documentation/ddi0301/h/Babhejba

Co-authored-by: Théophile Ranquet <tranquet@sequans.com>
Co-authored-by: Jonatan Antoni <jonatan.antoni@arm.com>
CMSIS/Core_A/Include/cmsis_cp15.h diff | blob | history
CMSIS/Core_A/Include/core_ca.h diff | blob | history
https://github.com/ARM-software/CMSIS_6.git