]> begriffs open source - cmsis/commit
__NVIC_EnableIRQ compiler barriers
authorKevin Bracey <kevin.bracey@arm.com>
Wed, 16 Jan 2019 13:34:55 +0000 (15:34 +0200)
committerJonatan Antoni <jonatan.antoni@arm.com>
Thu, 9 May 2019 07:25:04 +0000 (09:25 +0200)
commit91da2facfc766da46a9ebb345c2ec3358d547890
treebf6b138896bc512726c4b294b199885ca8fc412e
parent559c8491ec8d5ba7682c7de15c7aac43a3eb3b5f
__NVIC_EnableIRQ compiler barriers

__NVIC_DisableIRQ and __NVIC_EnableIRQ can be used to function as a
mutex-style protection lock against a particular interrupt handler,
similar to __disable_irq and __enable_irq for all interrupts.

However, __NVIC_EnableIRQ, unlike a mutex unlock or __enable_irq, had no
compiler barriers. Being just a volatile write, in the following code
sequence:

    NVIC_DisableIRQ(devx);
    // modify some RAM accessed by devx IRQ handler
    NVIC_EnableIRQ(devx);

there would be nothing preventing the RAM accesses from moved below the
NVIC_EnableIRQ.

Add barriers to NVIC_EnableIRQ, so that the above code works the same as
a mutex or __disable_irq, without any added need to mark the shared RAM
as volatile.

Fixes issue #493
13 files changed:
CMSIS/Core/Include/core_armv8mbl.h
CMSIS/Core/Include/core_armv8mml.h
CMSIS/Core/Include/core_cm0.h
CMSIS/Core/Include/core_cm0plus.h
CMSIS/Core/Include/core_cm1.h
CMSIS/Core/Include/core_cm23.h
CMSIS/Core/Include/core_cm3.h
CMSIS/Core/Include/core_cm33.h
CMSIS/Core/Include/core_cm35p.h
CMSIS/Core/Include/core_cm4.h
CMSIS/Core/Include/core_cm7.h
CMSIS/Core/Include/core_sc000.h
CMSIS/Core/Include/core_sc300.h