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(parent: 39944a3) | patch
Correct bit field width in EWIC Event Number ID Reg and TCM Error Bank Reg (#1622)
authorJoseph Yiu <77114984+joseph-yiu@users.noreply.github.com>
Thu, 20 Apr 2023 05:53:19 +0000 (06:53 +0100)
committerGitHub <noreply@github.com>
Thu, 20 Apr 2023 05:53:19 +0000 (07:53 +0200)
commitd682408e92e3f8210ac1dad807479703d4a5b461
treeaf57d669d15e98f12444a59b4d467777664f89d8tree | snapshot
parent39944a331b38c45dccf9ebb2044f671b4733a5cacommit | diff
Correct bit field width in EWIC Event Number ID Reg and TCM Error Bank Reg (#1622)

* Correct bit field width in EWIC Event Number ID Register and TCM Error Bank Registers

EWIC_NUMID: NUMEVENT is 16-bit in the TRM.
TEBR0/TEBR1: BANK filed is 3-bit in the TRM.
Revision updated.

* Update date

Update date to 19-April-2023
CMSIS/Core/Include/core_cm55.h diff | blob | history
CMSIS/Core/Include/core_cm85.h diff | blob | history
https://github.com/ARM-software/CMSIS_6.git