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Update RISC-V_IGLOO2_Creative_SoftConsole demo to make use of new RISC-V porting...
authorRichard Barry <ribarry@amazon.com>
Mon, 17 Dec 2018 00:01:36 +0000 (00:01 +0000)
committerRichard Barry <ribarry@amazon.com>
Mon, 17 Dec 2018 00:01:36 +0000 (00:01 +0000)
commit8285ca6b5f578c7d6880064b1a383f8987a4fd96
treee7d58c212bb01cfdbbdc2280edd27b154f7ce810tree | snapshot
parent101806906dc0cc2f3bad4d616b818a6c1681da79commit | diff
Update RISC-V_IGLOO2_Creative_SoftConsole demo to make use of new RISC-V porting layer structure and exercise some external interrupts - all tests currently passing in Renode.
FreeRTOS/Demo/RISC-V_IGLOO2_Creative_SoftConsole/.cproject diff | blob | history
FreeRTOS/Demo/RISC-V_IGLOO2_Creative_SoftConsole/.settings/language.settings.xml diff | blob | history
FreeRTOS/Demo/RISC-V_IGLOO2_Creative_SoftConsole/FreeRTOSConfig.h diff | blob | history
FreeRTOS/Demo/RISC-V_IGLOO2_Creative_SoftConsole/Microsemi_Code/riscv_hal/microsemi-riscv-igloo2.ld diff | blob | history
FreeRTOS/Demo/RISC-V_IGLOO2_Creative_SoftConsole/Microsemi_Code/riscv_hal/microsemi-riscv-ram.ld diff | blob | history
FreeRTOS/Demo/RISC-V_IGLOO2_Creative_SoftConsole/Microsemi_Code/riscv_hal/riscv_hal.c diff | blob | history
FreeRTOS/Demo/RISC-V_IGLOO2_Creative_SoftConsole/Microsemi_Code/riscv_hal/riscv_plic.h diff | blob | history
FreeRTOS/Demo/RISC-V_IGLOO2_Creative_SoftConsole/full_demo/main_full.c diff | blob | history
FreeRTOS/Demo/RISC-V_IGLOO2_Creative_SoftConsole/main.c diff | blob | history
https://github.com/FreeRTOS/FreeRTOS-Kernel.git