begriffs open source - freertos/commit

author	Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
	Thu, 27 Jan 2022 01:55:01 +0000 (17:55 -0800)
committer	GitHub <noreply@github.com>
	Thu, 27 Jan 2022 01:55:01 +0000 (17:55 -0800)
commit	9efca75d1ebfc6c02f9e004c199dffa327267a09
tree	ce4018c9401f931e6c8e0e160938ab8cb2203792	tree \| snapshot
parent	a3843bd5b1e3486b21230cfd2a52f0b2a447a66c	commit \| diff

Riscv re-factoring (#444)

* Refactor RISCV port

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
* Changes to make re-factoring work on ESP32-C3

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
* Remove alignment and place handlers in separate sections

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
* Correct section names

This is needed so that the assemblers correctly recognizes functions.

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
* Move mtvec programming to the application

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
* Refactor mtimer udpate code

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
* Move critical nesting to port layer

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
* Respect configTASK_RETURN_ADDRESS

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
* Formatting changes

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

portable/GCC/RISC-V/chip_specific_extensions/RISCV_no_extensions/freertos_risc_v_chip_specific_extensions.h	[new file with mode: 0644]	blob
portable/GCC/RISC-V/port.c		diff \| blob \| history
portable/GCC/RISC-V/portASM.S		diff \| blob \| history
portable/GCC/RISC-V/portContext.h	[new file with mode: 0644]	blob
portable/GCC/RISC-V/portmacro.h		diff \| blob \| history