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(parent: 3a3d061) | patch
Cortex-A5 IAR port baseline prior to removing all SAMA5 specifics to make it generic.:
authorRichard Barry <ribarry@amazon.com>
Sun, 3 Aug 2014 18:37:58 +0000 (18:37 +0000)
committerRichard Barry <ribarry@amazon.com>
Sun, 3 Aug 2014 18:37:58 +0000 (18:37 +0000)
commitb2e739495a52c0ead77af35a1f1253d67d4d2d23
treef5fc54ddd0e347057511482913f05358c778b656tree | snapshot
parent3a3d061cc59ac5d0cd193b24a4ec743eb8c411c2commit | diff
Cortex-A5 IAR port baseline prior to removing all SAMA5 specifics to make it generic.:
- Slight improvement to the save context macro.
- Remove some #warning remarks.
- Enable interrupts before calling the ISR handler rather than in the ISR handler.
FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/port.c diff | blob | history
FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/portASM.h diff | blob | history
FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/portASM.s diff | blob | history
FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/portmacro.h diff | blob | history
https://github.com/FreeRTOS/FreeRTOS-Kernel.git