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(parent: 96bad0f) | patch
RISC-V port updates: The machine timer compare register can now be for any HART...
authorRichard Barry <ribarry@amazon.com>
Wed, 4 Sep 2019 15:46:45 +0000 (15:46 +0000)
committerRichard Barry <ribarry@amazon.com>
Wed, 4 Sep 2019 15:46:45 +0000 (15:46 +0000)
commitda3d370ff7cdcf883e9f3ca3ba1c7c731889c9ed
tree3d6437598b7484868a3a510af7f0e0292ba7a5b1tree | snapshot
parent96bad0f6c3de6e36b2a5ece64e830966c77561b6commit | diff
RISC-V port updates:  The machine timer compare register can now be for any HART, and correct the sequence used to update the 64-bit machine timer compare register on 32-bit cores.
FreeRTOS/Source/portable/GCC/RISC-V/port.c diff | blob | history
FreeRTOS/Source/portable/GCC/RISC-V/portASM.S diff | blob | history
FreeRTOS/Source/portable/IAR/RISC-V/chip_specific_extensions/Pulpino_Vega_RV32M1RM/freertos_risc_v_chip_specific_extensions.h [deleted file] blob | history
FreeRTOS/Source/portable/IAR/RISC-V/port.c diff | blob | history
FreeRTOS/Source/portable/IAR/RISC-V/portASM.s diff | blob | history
https://github.com/FreeRTOS/FreeRTOS-Kernel.git