begriffs open source - cmsis-freertos/blob - Source/portable/IAR/ARM_CM33/non_secure/port.c

   1 /*
   2  * FreeRTOS Kernel V10.3.1
   3  * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a copy of
   6  * this software and associated documentation files (the "Software"), to deal in
   7  * the Software without restriction, including without limitation the rights to
   8  * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
   9  * the Software, and to permit persons to whom the Software is furnished to do so,
  10  * subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in all
  13  * copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
  17  * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
  18  * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
  19  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  20  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * http://www.FreeRTOS.org
  23  * http://aws.amazon.com/freertos
  24  *
  25  * 1 tab == 4 spaces!
  26  */
  27
  28 /* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
  29  * all the API functions to use the MPU wrappers. That should only be done when
  30  * task.h is included from an application file. */
  31 #define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
  32
  33 /* Scheduler includes. */
  34 #include "FreeRTOS.h"
  35 #include "task.h"
  36
  37 /* MPU wrappers includes. */
  38 #include "mpu_wrappers.h"
  39
  40 /* Portasm includes. */
  41 #include "portasm.h"
  42
  43 #if( configENABLE_TRUSTZONE == 1 )
  44         /* Secure components includes. */
  45         #include "secure_context.h"
  46         #include "secure_init.h"
  47 #endif /* configENABLE_TRUSTZONE */
  48
  49 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
  50
  51 /**
  52  * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
  53  * i.e. the processor boots as secure and never jumps to the non-secure side.
  54  * The Trust Zone support in the port must be disabled in order to run FreeRTOS
  55  * on the secure side. The following are the valid configuration seetings:
  56  *
  57  * 1. Run FreeRTOS on the Secure Side:
  58  *              configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0
  59  *
  60  * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:
  61  *              configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1
  62  *
  63  * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:
  64  *              configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0
  65  */
  66 #if( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )
  67         #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.
  68 #endif
  69 /*-----------------------------------------------------------*/
  70
  71 /**
  72  * @brief Constants required to manipulate the NVIC.
  73  */
  74 #define portNVIC_SYSTICK_CTRL                           ( ( volatile uint32_t * ) 0xe000e010 )
  75 #define portNVIC_SYSTICK_LOAD                           ( ( volatile uint32_t * ) 0xe000e014 )
  76 #define portNVIC_SYSTICK_CURRENT_VALUE          ( ( volatile uint32_t * ) 0xe000e018 )
  77 #define portNVIC_INT_CTRL                                       ( ( volatile uint32_t * ) 0xe000ed04 )
  78 #define portNVIC_SYSPRI2                                        ( ( volatile uint32_t * ) 0xe000ed20 )
  79 #define portNVIC_SYSTICK_CLK                            ( 0x00000004 )
  80 #define portNVIC_SYSTICK_INT                            ( 0x00000002 )
  81 #define portNVIC_SYSTICK_ENABLE                         ( 0x00000001 )
  82 #define portNVIC_PENDSVSET                                      ( 0x10000000 )
  83 #define portMIN_INTERRUPT_PRIORITY                      ( 255UL )
  84 #define portNVIC_PENDSV_PRI                                     ( portMIN_INTERRUPT_PRIORITY << 16UL )
  85 #define portNVIC_SYSTICK_PRI                            ( portMIN_INTERRUPT_PRIORITY << 24UL )
  86 /*-----------------------------------------------------------*/
  87
  88 /**
  89  * @brief Constants required to manipulate the SCB.
  90  */
  91 #define portSCB_SYS_HANDLER_CTRL_STATE_REG      ( * ( volatile uint32_t * ) 0xe000ed24 )
  92 #define portSCB_MEM_FAULT_ENABLE                        ( 1UL << 16UL )
  93 /*-----------------------------------------------------------*/
  94
  95 /**
  96  * @brief Constants required to manipulate the FPU.
  97  */
  98 #define portCPACR                                                       ( ( volatile uint32_t * ) 0xe000ed88 )  /* Coprocessor Access Control Register. */
  99 #define portCPACR_CP10_VALUE                            ( 3UL )
 100 #define portCPACR_CP11_VALUE                            portCPACR_CP10_VALUE
 101 #define portCPACR_CP10_POS                                      ( 20UL )
 102 #define portCPACR_CP11_POS                                      ( 22UL )
 103
 104 #define portFPCCR                                                       ( ( volatile uint32_t * ) 0xe000ef34 )  /* Floating Point Context Control Register. */
 105 #define portFPCCR_ASPEN_POS                                     ( 31UL )
 106 #define portFPCCR_ASPEN_MASK                            ( 1UL << portFPCCR_ASPEN_POS )
 107 #define portFPCCR_LSPEN_POS                                     ( 30UL )
 108 #define portFPCCR_LSPEN_MASK                            ( 1UL << portFPCCR_LSPEN_POS )
 109 /*-----------------------------------------------------------*/
 110
 111 /**
 112  * @brief Constants required to manipulate the MPU.
 113  */
 114 #define portMPU_TYPE_REG                                        ( * ( ( volatile uint32_t * ) 0xe000ed90 ) )
 115 #define portMPU_CTRL_REG                                        ( * ( ( volatile uint32_t * ) 0xe000ed94 ) )
 116 #define portMPU_RNR_REG                                         ( * ( ( volatile uint32_t * ) 0xe000ed98 ) )
 117
 118 #define portMPU_RBAR_REG                                        ( * ( ( volatile uint32_t * ) 0xe000ed9c ) )
 119 #define portMPU_RLAR_REG                                        ( * ( ( volatile uint32_t * ) 0xe000eda0 ) )
 120
 121 #define portMPU_RBAR_A1_REG                                     ( * ( ( volatile uint32_t * ) 0xe000eda4 ) )
 122 #define portMPU_RLAR_A1_REG                                     ( * ( ( volatile uint32_t * ) 0xe000eda8 ) )
 123
 124 #define portMPU_RBAR_A2_REG                                     ( * ( ( volatile uint32_t * ) 0xe000edac ) )
 125 #define portMPU_RLAR_A2_REG                                     ( * ( ( volatile uint32_t * ) 0xe000edb0 ) )
 126
 127 #define portMPU_RBAR_A3_REG                                     ( * ( ( volatile uint32_t * ) 0xe000edb4 ) )
 128 #define portMPU_RLAR_A3_REG                                     ( * ( ( volatile uint32_t * ) 0xe000edb8 ) )
 129
 130 #define portMPU_MAIR0_REG                                       ( * ( ( volatile uint32_t * ) 0xe000edc0 ) )
 131 #define portMPU_MAIR1_REG                                       ( * ( ( volatile uint32_t * ) 0xe000edc4 ) )
 132
 133 #define portMPU_RBAR_ADDRESS_MASK                       ( 0xffffffe0 ) /* Must be 32-byte aligned. */
 134 #define portMPU_RLAR_ADDRESS_MASK                       ( 0xffffffe0 ) /* Must be 32-byte aligned. */
 135
 136 #define portMPU_MAIR_ATTR0_POS                          ( 0UL )
 137 #define portMPU_MAIR_ATTR0_MASK                         ( 0x000000ff )
 138
 139 #define portMPU_MAIR_ATTR1_POS                          ( 8UL )
 140 #define portMPU_MAIR_ATTR1_MASK                         ( 0x0000ff00 )
 141
 142 #define portMPU_MAIR_ATTR2_POS                          ( 16UL )
 143 #define portMPU_MAIR_ATTR2_MASK                         ( 0x00ff0000 )
 144
 145 #define portMPU_MAIR_ATTR3_POS                          ( 24UL )
 146 #define portMPU_MAIR_ATTR3_MASK                         ( 0xff000000 )
 147
 148 #define portMPU_MAIR_ATTR4_POS                          ( 0UL )
 149 #define portMPU_MAIR_ATTR4_MASK                         ( 0x000000ff )
 150
 151 #define portMPU_MAIR_ATTR5_POS                          ( 8UL )
 152 #define portMPU_MAIR_ATTR5_MASK                         ( 0x0000ff00 )
 153
 154 #define portMPU_MAIR_ATTR6_POS                          ( 16UL )
 155 #define portMPU_MAIR_ATTR6_MASK                         ( 0x00ff0000 )
 156
 157 #define portMPU_MAIR_ATTR7_POS                          ( 24UL )
 158 #define portMPU_MAIR_ATTR7_MASK                         ( 0xff000000 )
 159
 160 #define portMPU_RLAR_ATTR_INDEX0                        ( 0UL << 1UL )
 161 #define portMPU_RLAR_ATTR_INDEX1                        ( 1UL << 1UL )
 162 #define portMPU_RLAR_ATTR_INDEX2                        ( 2UL << 1UL )
 163 #define portMPU_RLAR_ATTR_INDEX3                        ( 3UL << 1UL )
 164 #define portMPU_RLAR_ATTR_INDEX4                        ( 4UL << 1UL )
 165 #define portMPU_RLAR_ATTR_INDEX5                        ( 5UL << 1UL )
 166 #define portMPU_RLAR_ATTR_INDEX6                        ( 6UL << 1UL )
 167 #define portMPU_RLAR_ATTR_INDEX7                        ( 7UL << 1UL )
 168
 169 #define portMPU_RLAR_REGION_ENABLE                      ( 1UL )
 170
 171 /* Enable privileged access to unmapped region. */
 172 #define portMPU_PRIV_BACKGROUND_ENABLE          ( 1UL << 2UL )
 173
 174 /* Enable MPU. */
 175 #define portMPU_ENABLE                                          ( 1UL << 0UL )
 176
 177 /* Expected value of the portMPU_TYPE register. */
 178 #define portEXPECTED_MPU_TYPE_VALUE                     ( 8UL << 8UL ) /* 8 regions, unified. */
 179 /*-----------------------------------------------------------*/
 180
 181 /**
 182  * @brief Constants required to set up the initial stack.
 183  */
 184 #define portINITIAL_XPSR                                        ( 0x01000000 )
 185
 186 #if( configRUN_FREERTOS_SECURE_ONLY == 1 )
 187         /**
 188          * @brief Initial EXC_RETURN value.
 189          *
 190          *     FF         FF         FF         FD
 191          * 1111 1111  1111 1111  1111 1111  1111 1101
 192          *
 193          * Bit[6] - 1 --> The exception was taken from the Secure state.
 194          * Bit[5] - 1 --> Do not skip stacking of additional state context.
 195          * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
 196          * Bit[3] - 1 --> Return to the Thread mode.
 197          * Bit[2] - 1 --> Restore registers from the process stack.
 198          * Bit[1] - 0 --> Reserved, 0.
 199          * Bit[0] - 1 --> The exception was taken to the Secure state.
 200          */
 201         #define portINITIAL_EXC_RETURN                  ( 0xfffffffd )
 202 #else
 203         /**
 204          * @brief Initial EXC_RETURN value.
 205          *
 206          *     FF         FF         FF         BC
 207          * 1111 1111  1111 1111  1111 1111  1011 1100
 208          *
 209          * Bit[6] - 0 --> The exception was taken from the Non-Secure state.
 210          * Bit[5] - 1 --> Do not skip stacking of additional state context.
 211          * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
 212          * Bit[3] - 1 --> Return to the Thread mode.
 213          * Bit[2] - 1 --> Restore registers from the process stack.
 214          * Bit[1] - 0 --> Reserved, 0.
 215          * Bit[0] - 0 --> The exception was taken to the Non-Secure state.
 216          */
 217         #define portINITIAL_EXC_RETURN                  ( 0xffffffbc )
 218 #endif /* configRUN_FREERTOS_SECURE_ONLY */
 219
 220 /**
 221  * @brief CONTROL register privileged bit mask.
 222  *
 223  * Bit[0] in CONTROL register tells the privilege:
 224  *  Bit[0] = 0 ==> The task is privileged.
 225  *  Bit[0] = 1 ==> The task is not privileged.
 226  */
 227 #define portCONTROL_PRIVILEGED_MASK                     ( 1UL << 0UL )
 228
 229 /**
 230  * @brief Initial CONTROL register values.
 231  */
 232 #define portINITIAL_CONTROL_UNPRIVILEGED        ( 0x3 )
 233 #define portINITIAL_CONTROL_PRIVILEGED          ( 0x2 )
 234
 235 /**
 236  * @brief Let the user override the pre-loading of the initial LR with the
 237  * address of prvTaskExitError() in case it messes up unwinding of the stack
 238  * in the debugger.
 239  */
 240 #ifdef configTASK_RETURN_ADDRESS
 241         #define portTASK_RETURN_ADDRESS                 configTASK_RETURN_ADDRESS
 242 #else
 243         #define portTASK_RETURN_ADDRESS                 prvTaskExitError
 244 #endif
 245
 246 /**
 247  * @brief If portPRELOAD_REGISTERS then registers will be given an initial value
 248  * when a task is created. This helps in debugging at the cost of code size.
 249  */
 250 #define portPRELOAD_REGISTERS                           1
 251
 252 /**
 253  * @brief A task is created without a secure context, and must call
 254  * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes
 255  * any secure calls.
 256  */
 257 #define portNO_SECURE_CONTEXT                           0
 258 /*-----------------------------------------------------------*/
 259
 260 /**
 261  * @brief Used to catch tasks that attempt to return from their implementing
 262  * function.
 263  */
 264 static void prvTaskExitError( void );
 265
 266 #if( configENABLE_MPU == 1 )
 267         /**
 268          * @brief Setup the Memory Protection Unit (MPU).
 269          */
 270         static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
 271 #endif /* configENABLE_MPU */
 272
 273 #if( configENABLE_FPU == 1 )
 274         /**
 275          * @brief Setup the Floating Point Unit (FPU).
 276          */
 277         static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
 278 #endif /* configENABLE_FPU */
 279
 280 /**
 281  * @brief Setup the timer to generate the tick interrupts.
 282  *
 283  * The implementation in this file is weak to allow application writers to
 284  * change the timer used to generate the tick interrupt.
 285  */
 286 void vPortSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;
 287
 288 /**
 289  * @brief Checks whether the current execution context is interrupt.
 290  *
 291  * @return pdTRUE if the current execution context is interrupt, pdFALSE
 292  * otherwise.
 293  */
 294 BaseType_t xPortIsInsideInterrupt( void );
 295
 296 /**
 297  * @brief Yield the processor.
 298  */
 299 void vPortYield( void ) PRIVILEGED_FUNCTION;
 300
 301 /**
 302  * @brief Enter critical section.
 303  */
 304 void vPortEnterCritical( void ) PRIVILEGED_FUNCTION;
 305
 306 /**
 307  * @brief Exit from critical section.
 308  */
 309 void vPortExitCritical( void ) PRIVILEGED_FUNCTION;
 310
 311 /**
 312  * @brief SysTick handler.
 313  */
 314 void SysTick_Handler( void ) PRIVILEGED_FUNCTION;
 315
 316 /**
 317  * @brief C part of SVC handler.
 318  */
 319 portDONT_DISCARD void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) PRIVILEGED_FUNCTION;
 320 /*-----------------------------------------------------------*/
 321
 322 /**
 323  * @brief Each task maintains its own interrupt status in the critical nesting
 324  * variable.
 325  */
 326 static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
 327
 328 #if( configENABLE_TRUSTZONE == 1 )
 329         /**
 330          * @brief Saved as part of the task context to indicate which context the
 331          * task is using on the secure side.
 332          */
 333         portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
 334 #endif /* configENABLE_TRUSTZONE */
 335 /*-----------------------------------------------------------*/
 336
 337 __attribute__(( weak )) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */
 338 {
 339         /* Stop and reset the SysTick. */
 340         *( portNVIC_SYSTICK_CTRL ) = 0UL;
 341         *( portNVIC_SYSTICK_CURRENT_VALUE ) = 0UL;
 342
 343         /* Configure SysTick to interrupt at the requested rate. */
 344         *( portNVIC_SYSTICK_LOAD ) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
 345         *( portNVIC_SYSTICK_CTRL ) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;
 346 }
 347 /*-----------------------------------------------------------*/
 348
 349 static void prvTaskExitError( void )
 350 {
 351 volatile uint32_t ulDummy = 0UL;
 352
 353         /* A function that implements a task must not exit or attempt to return to
 354          * its caller as there is nothing to return to. If a task wants to exit it
 355          * should instead call vTaskDelete( NULL ). Artificially force an assert()
 356          * to be triggered if configASSERT() is defined, then stop here so
 357          * application writers can catch the error. */
 358         configASSERT( ulCriticalNesting == ~0UL );
 359         portDISABLE_INTERRUPTS();
 360
 361         while( ulDummy == 0 )
 362         {
 363                 /* This file calls prvTaskExitError() after the scheduler has been
 364                  * started to remove a compiler warning about the function being
 365                  * defined but never called.  ulDummy is used purely to quieten other
 366                  * warnings about code appearing after this function is called - making
 367                  * ulDummy volatile makes the compiler think the function could return
 368                  * and therefore not output an 'unreachable code' warning for code that
 369                  * appears after it. */
 370         }
 371 }
 372 /*-----------------------------------------------------------*/
 373
 374 #if( configENABLE_MPU == 1 )
 375         static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */
 376         {
 377         #if defined( __ARMCC_VERSION )
 378                 /* Declaration when these variable are defined in code instead of being
 379                  * exported from linker scripts. */
 380                 extern uint32_t * __privileged_functions_start__;
 381                 extern uint32_t * __privileged_functions_end__;
 382                 extern uint32_t * __syscalls_flash_start__;
 383                 extern uint32_t * __syscalls_flash_end__;
 384                 extern uint32_t * __unprivileged_flash_start__;
 385                 extern uint32_t * __unprivileged_flash_end__;
 386                 extern uint32_t * __privileged_sram_start__;
 387                 extern uint32_t * __privileged_sram_end__;
 388         #else
 389                 /* Declaration when these variable are exported from linker scripts. */
 390                 extern uint32_t __privileged_functions_start__[];
 391                 extern uint32_t __privileged_functions_end__[];
 392                 extern uint32_t __syscalls_flash_start__[];
 393                 extern uint32_t __syscalls_flash_end__[];
 394                 extern uint32_t __unprivileged_flash_start__[];
 395                 extern uint32_t __unprivileged_flash_end__[];
 396                 extern uint32_t __privileged_sram_start__[];
 397                 extern uint32_t __privileged_sram_end__[];
 398         #endif /* defined( __ARMCC_VERSION ) */
 399
 400                 /* Check that the MPU is present. */
 401                 if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
 402                 {
 403                         /* MAIR0 - Index 0. */
 404                         portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
 405                         /* MAIR0 - Index 1. */
 406                         portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
 407
 408                         /* Setup privileged flash as Read Only so that privileged tasks can
 409                          * read it but not modify. */
 410                         portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
 411                         portMPU_RBAR_REG =      ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
 412                                                                 ( portMPU_REGION_NON_SHAREABLE ) |
 413                                                                 ( portMPU_REGION_PRIVILEGED_READ_ONLY );
 414                         portMPU_RLAR_REG =      ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
 415                                                                 ( portMPU_RLAR_ATTR_INDEX0 ) |
 416                                                                 ( portMPU_RLAR_REGION_ENABLE );
 417
 418                         /* Setup unprivileged flash as Read Only by both privileged and
 419                          * unprivileged tasks. All tasks can read it but no-one can modify. */
 420                         portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
 421                         portMPU_RBAR_REG =      ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
 422                                                                 ( portMPU_REGION_NON_SHAREABLE ) |
 423                                                                 ( portMPU_REGION_READ_ONLY );
 424                         portMPU_RLAR_REG =      ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
 425                                                                 ( portMPU_RLAR_ATTR_INDEX0 ) |
 426                                                                 ( portMPU_RLAR_REGION_ENABLE );
 427
 428                         /* Setup unprivileged syscalls flash as Read Only by both privileged
 429                          * and unprivileged tasks. All tasks can read it but no-one can modify. */
 430                         portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
 431                         portMPU_RBAR_REG =      ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
 432                                                                 ( portMPU_REGION_NON_SHAREABLE ) |
 433                                                                 ( portMPU_REGION_READ_ONLY );
 434                         portMPU_RLAR_REG =      ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
 435                                                                 ( portMPU_RLAR_ATTR_INDEX0 ) |
 436                                                                 ( portMPU_RLAR_REGION_ENABLE );
 437
 438                         /* Setup RAM containing kernel data for privileged access only. */
 439                         portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
 440                         portMPU_RBAR_REG =      ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
 441                                                                 ( portMPU_REGION_NON_SHAREABLE ) |
 442                                                                 ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
 443                                                                 ( portMPU_REGION_EXECUTE_NEVER );
 444                         portMPU_RLAR_REG =      ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
 445                                                                 ( portMPU_RLAR_ATTR_INDEX0 ) |
 446                                                                 ( portMPU_RLAR_REGION_ENABLE );
 447
 448                         /* Enable mem fault. */
 449                         portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE;
 450
 451                         /* Enable MPU with privileged background access i.e. unmapped
 452                          * regions have privileged access. */
 453                         portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE | portMPU_ENABLE );
 454                 }
 455         }
 456 #endif /* configENABLE_MPU */
 457 /*-----------------------------------------------------------*/
 458
 459 #if( configENABLE_FPU == 1 )
 460         static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
 461         {
 462                 #if( configENABLE_TRUSTZONE == 1 )
 463                 {
 464                         /* Enable non-secure access to the FPU. */
 465                         SecureInit_EnableNSFPUAccess();
 466                 }
 467                 #endif /* configENABLE_TRUSTZONE */
 468
 469                 /* CP10 = 11 ==> Full access to FPU i.e. both privileged and
 470                  * unprivileged code should be able to access FPU. CP11 should be
 471                  * programmed to the same value as CP10. */
 472                 *( portCPACR ) |=       (       ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) |
 473                                                                 ( portCPACR_CP11_VALUE << portCPACR_CP11_POS )
 474                                                         );
 475
 476                 /* ASPEN = 1 ==> Hardware should automatically preserve floating point
 477                  * context on exception entry and restore on exception return.
 478                  * LSPEN = 1 ==> Enable lazy context save of FP state. */
 479                 *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );
 480         }
 481 #endif /* configENABLE_FPU */
 482 /*-----------------------------------------------------------*/
 483
 484 void vPortYield( void ) /* PRIVILEGED_FUNCTION */
 485 {
 486         /* Set a PendSV to request a context switch. */
 487         *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
 488
 489         /* Barriers are normally not required but do ensure the code is
 490          * completely within the specified behaviour for the architecture. */
 491         __asm volatile( "dsb" ::: "memory" );
 492         __asm volatile( "isb" );
 493 }
 494 /*-----------------------------------------------------------*/
 495
 496 void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */
 497 {
 498         portDISABLE_INTERRUPTS();
 499         ulCriticalNesting++;
 500
 501         /* Barriers are normally not required but do ensure the code is
 502          * completely within the specified behaviour for the architecture. */
 503         __asm volatile( "dsb" ::: "memory" );
 504         __asm volatile( "isb" );
 505 }
 506 /*-----------------------------------------------------------*/
 507
 508 void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */
 509 {
 510         configASSERT( ulCriticalNesting );
 511         ulCriticalNesting--;
 512
 513         if( ulCriticalNesting == 0 )
 514         {
 515                 portENABLE_INTERRUPTS();
 516         }
 517 }
 518 /*-----------------------------------------------------------*/
 519
 520 void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */
 521 {
 522 uint32_t ulPreviousMask;
 523
 524         ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
 525         {
 526                 /* Increment the RTOS tick. */
 527                 if( xTaskIncrementTick() != pdFALSE )
 528                 {
 529                         /* Pend a context switch. */
 530                         *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
 531                 }
 532         }
 533         portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
 534 }
 535 /*-----------------------------------------------------------*/
 536
 537 void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */
 538 {
 539 #if( configENABLE_MPU == 1 )
 540         #if defined( __ARMCC_VERSION )
 541                 /* Declaration when these variable are defined in code instead of being
 542                  * exported from linker scripts. */
 543                 extern uint32_t * __syscalls_flash_start__;
 544                 extern uint32_t * __syscalls_flash_end__;
 545         #else
 546                 /* Declaration when these variable are exported from linker scripts. */
 547                 extern uint32_t __syscalls_flash_start__[];
 548                 extern uint32_t __syscalls_flash_end__[];
 549         #endif /* defined( __ARMCC_VERSION ) */
 550 #endif /* configENABLE_MPU */
 551
 552 uint32_t ulPC;
 553
 554 #if( configENABLE_TRUSTZONE == 1 )
 555         uint32_t ulR0;
 556         #if( configENABLE_MPU == 1 )
 557                 uint32_t ulControl, ulIsTaskPrivileged;
 558         #endif /* configENABLE_MPU */
 559 #endif /* configENABLE_TRUSTZONE */
 560 uint8_t ucSVCNumber;
 561
 562         /* Register are stored on the stack in the following order - R0, R1, R2, R3,
 563          * R12, LR, PC, xPSR. */
 564         ulPC = pulCallerStackAddress[ 6 ];
 565         ucSVCNumber = ( ( uint8_t *) ulPC )[ -2 ];
 566
 567         switch( ucSVCNumber )
 568         {
 569                 #if( configENABLE_TRUSTZONE == 1 )
 570                         case portSVC_ALLOCATE_SECURE_CONTEXT:
 571                         {
 572                                 /* R0 contains the stack size passed as parameter to the
 573                                  * vPortAllocateSecureContext function. */
 574                                 ulR0 = pulCallerStackAddress[ 0 ];
 575
 576                                 #if( configENABLE_MPU == 1 )
 577                                 {
 578                                         /* Read the CONTROL register value. */
 579                                         __asm volatile ( "mrs %0, control"  : "=r" ( ulControl ) );
 580
 581                                         /* The task that raised the SVC is privileged if Bit[0]
 582                                          * in the CONTROL register is 0. */
 583                                         ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
 584
 585                                         /* Allocate and load a context for the secure task. */
 586                                         xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );
 587                                 }
 588                                 #else
 589                                 {
 590                                         /* Allocate and load a context for the secure task. */
 591                                         xSecureContext = SecureContext_AllocateContext( ulR0 );
 592                                 }
 593                                 #endif /* configENABLE_MPU */
 594
 595                                 configASSERT( xSecureContext != NULL );
 596                                 SecureContext_LoadContext( xSecureContext );
 597                         }
 598                         break;
 599
 600                         case portSVC_FREE_SECURE_CONTEXT:
 601                         {
 602                                 /* R0 contains the secure context handle to be freed. */
 603                                 ulR0 = pulCallerStackAddress[ 0 ];
 604
 605                                 /* Free the secure context. */
 606                                 SecureContext_FreeContext( ( SecureContextHandle_t ) ulR0 );
 607                         }
 608                         break;
 609                 #endif /* configENABLE_TRUSTZONE */
 610
 611                 case portSVC_START_SCHEDULER:
 612                 {
 613                         #if( configENABLE_TRUSTZONE == 1 )
 614                         {
 615                                 /* De-prioritize the non-secure exceptions so that the
 616                                  * non-secure pendSV runs at the lowest priority. */
 617                                 SecureInit_DePrioritizeNSExceptions();
 618
 619                                 /* Initialize the secure context management system. */
 620                                 SecureContext_Init();
 621                         }
 622                         #endif /* configENABLE_TRUSTZONE */
 623
 624                         #if( configENABLE_FPU == 1 )
 625                         {
 626                                 /* Setup the Floating Point Unit (FPU). */
 627                                 prvSetupFPU();
 628                         }
 629                         #endif /* configENABLE_FPU */
 630
 631                         /* Setup the context of the first task so that the first task starts
 632                          * executing. */
 633                         vRestoreContextOfFirstTask();
 634                 }
 635                 break;
 636
 637                 #if( configENABLE_MPU == 1 )
 638                         case portSVC_RAISE_PRIVILEGE:
 639                         {
 640                                 /* Only raise the privilege, if the svc was raised from any of
 641                                  * the system calls. */
 642                                 if( ulPC >= ( uint32_t ) __syscalls_flash_start__ &&
 643                                         ulPC <= ( uint32_t ) __syscalls_flash_end__ )
 644                                 {
 645                                         vRaisePrivilege();
 646                                 }
 647                         }
 648                         break;
 649                 #endif /* configENABLE_MPU */
 650
 651                 default:
 652                 {
 653                         /* Incorrect SVC call. */
 654                         configASSERT( pdFALSE );
 655                 }
 656         }
 657 }
 658 /*-----------------------------------------------------------*/
 659
 660 #if( configENABLE_MPU == 1 )
 661         StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */
 662 #else
 663         StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters ) /* PRIVILEGED_FUNCTION */
 664 #endif /* configENABLE_MPU */
 665 {
 666         /* Simulate the stack frame as it would be created by a context switch
 667          * interrupt. */
 668         #if( portPRELOAD_REGISTERS == 0 )
 669         {
 670                 pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
 671                 *pxTopOfStack = portINITIAL_XPSR;                                                       /* xPSR */
 672                 pxTopOfStack--;
 673                 *pxTopOfStack = ( StackType_t ) pxCode;                                         /* PC */
 674                 pxTopOfStack--;
 675                 *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;        /* LR */
 676                 pxTopOfStack -= 5;                                                                                      /* R12, R3, R2 and R1. */
 677                 *pxTopOfStack = ( StackType_t ) pvParameters;                           /* R0 */
 678                 pxTopOfStack -= 9;                                                                                      /* R11..R4, EXC_RETURN. */
 679                 *pxTopOfStack = portINITIAL_EXC_RETURN;
 680
 681                 #if( configENABLE_MPU == 1 )
 682                 {
 683                         pxTopOfStack--;
 684                         if( xRunPrivileged == pdTRUE )
 685                         {
 686                                 *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED;         /* Slot used to hold this task's CONTROL value. */
 687                         }
 688                         else
 689                         {
 690                                 *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED;       /* Slot used to hold this task's CONTROL value. */
 691                         }
 692                 }
 693                 #endif /* configENABLE_MPU */
 694
 695                 pxTopOfStack--;
 696                 *pxTopOfStack = ( StackType_t ) pxEndOfStack;   /* Slot used to hold this task's PSPLIM value. */
 697
 698                 #if( configENABLE_TRUSTZONE == 1 )
 699                 {
 700                         pxTopOfStack--;
 701                         *pxTopOfStack = portNO_SECURE_CONTEXT;          /* Slot used to hold this task's xSecureContext value. */
 702                 }
 703                 #endif /* configENABLE_TRUSTZONE */
 704         }
 705         #else /* portPRELOAD_REGISTERS */
 706         {
 707                 pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
 708                 *pxTopOfStack = portINITIAL_XPSR;                                                       /* xPSR */
 709                 pxTopOfStack--;
 710                 *pxTopOfStack = ( StackType_t ) pxCode;                                         /* PC */
 711                 pxTopOfStack--;
 712                 *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;        /* LR */
 713                 pxTopOfStack--;
 714                 *pxTopOfStack = ( StackType_t ) 0x12121212UL;                           /* R12 */
 715                 pxTopOfStack--;
 716                 *pxTopOfStack = ( StackType_t ) 0x03030303UL;                           /* R3 */
 717                 pxTopOfStack--;
 718                 *pxTopOfStack = ( StackType_t ) 0x02020202UL;                           /* R2 */
 719                 pxTopOfStack--;
 720                 *pxTopOfStack = ( StackType_t ) 0x01010101UL;                           /* R1 */
 721                 pxTopOfStack--;
 722                 *pxTopOfStack = ( StackType_t ) pvParameters;                           /* R0 */
 723                 pxTopOfStack--;
 724                 *pxTopOfStack = ( StackType_t ) 0x11111111UL;                           /* R11 */
 725                 pxTopOfStack--;
 726                 *pxTopOfStack = ( StackType_t ) 0x10101010UL;                           /* R10 */
 727                 pxTopOfStack--;
 728                 *pxTopOfStack = ( StackType_t ) 0x09090909UL;                           /* R09 */
 729                 pxTopOfStack--;
 730                 *pxTopOfStack = ( StackType_t ) 0x08080808UL;                           /* R08 */
 731                 pxTopOfStack--;
 732                 *pxTopOfStack = ( StackType_t ) 0x07070707UL;                           /* R07 */
 733                 pxTopOfStack--;
 734                 *pxTopOfStack = ( StackType_t ) 0x06060606UL;                           /* R06 */
 735                 pxTopOfStack--;
 736                 *pxTopOfStack = ( StackType_t ) 0x05050505UL;                           /* R05 */
 737                 pxTopOfStack--;
 738                 *pxTopOfStack = ( StackType_t ) 0x04040404UL;                           /* R04 */
 739                 pxTopOfStack--;
 740                 *pxTopOfStack = portINITIAL_EXC_RETURN;                                         /* EXC_RETURN */
 741
 742                 #if( configENABLE_MPU == 1 )
 743                 {
 744                         pxTopOfStack--;
 745                         if( xRunPrivileged == pdTRUE )
 746                         {
 747                                 *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED;         /* Slot used to hold this task's CONTROL value. */
 748                         }
 749                         else
 750                         {
 751                                 *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED;       /* Slot used to hold this task's CONTROL value. */
 752                         }
 753                 }
 754                 #endif /* configENABLE_MPU */
 755
 756                 pxTopOfStack--;
 757                 *pxTopOfStack = ( StackType_t ) pxEndOfStack;   /* Slot used to hold this task's PSPLIM value. */
 758
 759                 #if( configENABLE_TRUSTZONE == 1 )
 760                 {
 761                         pxTopOfStack--;
 762                         *pxTopOfStack = portNO_SECURE_CONTEXT;          /* Slot used to hold this task's xSecureContext value. */
 763                 }
 764                 #endif /* configENABLE_TRUSTZONE */
 765         }
 766         #endif /* portPRELOAD_REGISTERS */
 767
 768         return pxTopOfStack;
 769 }
 770 /*-----------------------------------------------------------*/
 771
 772 BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
 773 {
 774         /* Make PendSV, CallSV and SysTick the same priority as the kernel. */
 775         *( portNVIC_SYSPRI2 ) |= portNVIC_PENDSV_PRI;
 776         *( portNVIC_SYSPRI2 ) |= portNVIC_SYSTICK_PRI;
 777
 778         #if( configENABLE_MPU == 1 )
 779         {
 780                 /* Setup the Memory Protection Unit (MPU). */
 781                 prvSetupMPU();
 782         }
 783         #endif /* configENABLE_MPU */
 784
 785         /* Start the timer that generates the tick ISR. Interrupts are disabled
 786          * here already. */
 787         vPortSetupTimerInterrupt();
 788
 789         /* Initialize the critical nesting count ready for the first task. */
 790         ulCriticalNesting = 0;
 791
 792         /* Start the first task. */
 793         vStartFirstTask();
 794
 795         /* Should never get here as the tasks will now be executing. Call the task
 796          * exit error function to prevent compiler warnings about a static function
 797          * not being called in the case that the application writer overrides this
 798          * functionality by defining configTASK_RETURN_ADDRESS. Call
 799          * vTaskSwitchContext() so link time optimization does not remove the
 800          * symbol. */
 801         vTaskSwitchContext();
 802         prvTaskExitError();
 803
 804         /* Should not get here. */
 805         return 0;
 806 }
 807 /*-----------------------------------------------------------*/
 808
 809 void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
 810 {
 811         /* Not implemented in ports where there is nothing to return to.
 812          * Artificially force an assert. */
 813         configASSERT( ulCriticalNesting == 1000UL );
 814 }
 815 /*-----------------------------------------------------------*/
 816
 817 #if( configENABLE_MPU == 1 )
 818         void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )
 819         {
 820         uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
 821         int32_t lIndex = 0;
 822
 823                 /* Setup MAIR0. */
 824                 xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
 825                 xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
 826
 827                 /* This function is called automatically when the task is created - in
 828                  * which case the stack region parameters will be valid.  At all other
 829                  * times the stack parameters will not be valid and it is assumed that
 830                  * the stack region has already been configured. */
 831                 if( ulStackDepth > 0 )
 832                 {
 833                         /* Define the region that allows access to the stack. */
 834                         ulRegionStartAddress = ( ( uint32_t ) pxBottomOfStack ) & portMPU_RBAR_ADDRESS_MASK;
 835                         ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
 836                         ulRegionEndAddress  &= portMPU_RLAR_ADDRESS_MASK;
 837
 838                         xMPUSettings->xRegionsSettings[ 0 ].ulRBAR =    ( ulRegionStartAddress ) |
 839                                                                                                                         ( portMPU_REGION_NON_SHAREABLE ) |
 840                                                                                                                         ( portMPU_REGION_READ_WRITE ) |
 841                                                                                                                         ( portMPU_REGION_EXECUTE_NEVER );
 842
 843                         xMPUSettings->xRegionsSettings[ 0 ].ulRLAR =    ( ulRegionEndAddress ) |
 844                                                                                                                         ( portMPU_RLAR_ATTR_INDEX0 ) |
 845                                                                                                                         ( portMPU_RLAR_REGION_ENABLE );
 846                 }
 847
 848                 /* User supplied configurable regions. */
 849                 for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )
 850                 {
 851                         /* If xRegions is NULL i.e. the task has not specified any MPU
 852                          * region, the else part ensures that all the configurable MPU
 853                          * regions are invalidated. */
 854                         if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) )
 855                         {
 856                                 /* Translate the generic region definition contained in xRegions
 857                                  * into the ARMv8 specific MPU settings that are then stored in
 858                                  * xMPUSettings. */
 859                                 ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;
 860                                 ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;
 861                                 ulRegionEndAddress  &= portMPU_RLAR_ADDRESS_MASK;
 862
 863                                 /* Start address. */
 864                                 xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR =       ( ulRegionStartAddress ) |
 865                                                                                                                                                         ( portMPU_REGION_NON_SHAREABLE );
 866
 867                                 /* RO/RW. */
 868                                 if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 )
 869                                 {
 870                                         xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY );
 871                                 }
 872                                 else
 873                                 {
 874                                         xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE );
 875                                 }
 876
 877                                 /* XN. */
 878                                 if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 )
 879                                 {
 880                                         xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER );
 881                                 }
 882
 883                                 /* End Address. */
 884                                 xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR =       ( ulRegionEndAddress ) |
 885                                                                                                                                                         ( portMPU_RLAR_REGION_ENABLE );
 886
 887                                 /* Normal memory/ Device memory. */
 888                                 if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
 889                                 {
 890                                         /* Attr1 in MAIR0 is configured as device memory. */
 891                                         xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1;
 892                                 }
 893                                 else
 894                                 {
 895                                         /* Attr1 in MAIR0 is configured as normal memory. */
 896                                         xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;
 897                                 }
 898                         }
 899                         else
 900                         {
 901                                 /* Invalidate the region. */
 902                                 xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL;
 903                                 xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL;
 904                         }
 905
 906                         lIndex++;
 907                 }
 908         }
 909 #endif /* configENABLE_MPU */
 910 /*-----------------------------------------------------------*/
 911
 912 BaseType_t xPortIsInsideInterrupt( void )
 913 {
 914 uint32_t ulCurrentInterrupt;
 915 BaseType_t xReturn;
 916
 917         /* Obtain the number of the currently executing interrupt. Interrupt Program
 918          * Status Register (IPSR) holds the exception number of the currently-executing
 919          * exception or zero for Thread mode.*/
 920         __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );
 921
 922         if( ulCurrentInterrupt == 0 )
 923         {
 924                 xReturn = pdFALSE;
 925         }
 926         else
 927         {
 928                 xReturn = pdTRUE;
 929         }
 930
 931         return xReturn;
 932 }
 933 /*-----------------------------------------------------------*/