begriffs open source - cmsis-freertos/blob - Source/portable/GCC/ARM_CM23/non_secure/portasm.c

   1 /*
   2  * FreeRTOS Kernel V11.2.0
   3  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
   4  *
   5  * SPDX-License-Identifier: MIT
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy of
   8  * this software and associated documentation files (the "Software"), to deal in
   9  * the Software without restriction, including without limitation the rights to
  10  * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
  11  * the Software, and to permit persons to whom the Software is furnished to do so,
  12  * subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in all
  15  * copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
  19  * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
  20  * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
  21  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  22  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * https://www.FreeRTOS.org
  25  * https://github.com/FreeRTOS
  26  *
  27  */
  28
  29 /* Standard includes. */
  30 #include <stdint.h>
  31
  32 /* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION
  33  * is defined correctly and privileged functions are placed in correct sections. */
  34 #define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
  35
  36 /* Portasm includes. */
  37 #include "portasm.h"
  38
  39 /* System call numbers includes. */
  40 #include "mpu_syscall_numbers.h"
  41
  42 /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the
  43  * header files. */
  44 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
  45
  46 #if ( configENABLE_FPU == 1 )
  47     #error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.
  48 #endif
  49
  50 #if ( configENABLE_MPU == 1 )
  51
  52     void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
  53     {
  54         __asm volatile
  55         (
  56             " .syntax unified                                 \n"
  57             "                                                 \n"
  58             " program_mpu_first_task:                         \n"
  59             "    ldr r3, =pxCurrentTCB                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
  60             "    ldr r0, [r3]                                 \n" /* r0 = pxCurrentTCB.*/
  61             "                                                 \n"
  62             "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
  63             "    ldr r1, =0xe000ed94                          \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
  64             "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
  65             "    movs r3, #1                                  \n" /* r3 = 1. */
  66             "    bics r2, r3                                  \n" /* r2 = r2 & ~r3 i.e. Clear the bit 0 in r2. */
  67             "    str r2, [r1]                                 \n" /* Disable MPU. */
  68             "                                                 \n"
  69             "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
  70             "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
  71             "    ldr r2, =0xe000edc0                          \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
  72             "    str r1, [r2]                                 \n" /* Program MAIR0. */
  73             "                                                 \n"
  74             "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
  75             "    ldr r1, =0xe000ed98                          \n" /* r1 = 0xe000ed98 [Location of RNR]. */
  76             "                                                 \n"
  77             "    movs r3, #4                                  \n" /* r3 = 4. */
  78             "    str r3, [r1]                                 \n" /* Program RNR = 4. */
  79             "    ldmia r0!, {r4-r5}                           \n" /* Read first set of RBAR/RLAR registers from TCB. */
  80             "    ldr r2, =0xe000ed9c                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
  81             "    stmia r2!, {r4-r5}                           \n" /* Write first set of RBAR/RLAR registers. */
  82             "    movs r3, #5                                  \n" /* r3 = 5. */
  83             "    str r3, [r1]                                 \n" /* Program RNR = 5. */
  84             "    ldmia r0!, {r4-r5}                           \n" /* Read second set of RBAR/RLAR registers from TCB. */
  85             "    ldr r2, =0xe000ed9c                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
  86             "    stmia r2!, {r4-r5}                           \n" /* Write second set of RBAR/RLAR registers. */
  87             "    movs r3, #6                                  \n" /* r3 = 6. */
  88             "    str r3, [r1]                                 \n" /* Program RNR = 6. */
  89             "    ldmia r0!, {r4-r5}                           \n" /* Read third set of RBAR/RLAR registers from TCB. */
  90             "    ldr r2, =0xe000ed9c                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
  91             "    stmia r2!, {r4-r5}                           \n" /* Write third set of RBAR/RLAR registers. */
  92             "    movs r3, #7                                  \n" /* r3 = 6. */
  93             "    str r3, [r1]                                 \n" /* Program RNR = 7. */
  94             "    ldmia r0!, {r4-r5}                           \n" /* Read fourth set of RBAR/RLAR registers from TCB. */
  95             "    ldr r2, =0xe000ed9c                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
  96             "    stmia r2!, {r4-r5}                           \n" /* Write fourth set of RBAR/RLAR registers. */
  97             "                                                 \n"
  98             "   ldr r1, =0xe000ed94                           \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
  99             "   ldr r2, [r1]                                  \n" /* Read the value of MPU_CTRL. */
 100             "   movs r3, #1                                   \n" /* r3 = 1. */
 101             "   orrs r2, r3                                   \n" /* r2 = r2 | r3 i.e. Set the bit 0 in r2. */
 102             "   str r2, [r1]                                  \n" /* Enable MPU. */
 103             "   dsb                                           \n" /* Force memory writes before continuing. */
 104             "                                                 \n"
 105             " restore_context_first_task:                     \n"
 106             "    ldr r3, =pxCurrentTCB                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
 107             "    ldr r1, [r3]                                 \n" /* r1 = pxCurrentTCB.*/
 108             "    ldr r2, [r1]                                 \n" /* r2 = Location of saved context in TCB. */
 109             "                                                 \n"
 110             " restore_special_regs_first_task:                \n"
 111             "    subs r2, #20                                 \n"
 112             "    ldmia r2!, {r0, r3-r6}                       \n" /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, r6 = LR. */
 113             "    subs r2, #20                                 \n"
 114             "    msr psp, r3                                  \n"
 115             "    msr control, r5                              \n"
 116             "    mov lr, r6                                   \n"
 117             "    ldr r4, =xSecureContext                      \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
 118             "    str r0, [r4]                                 \n" /* Restore xSecureContext. */
 119             "                                                 \n"
 120             " restore_general_regs_first_task:                \n"
 121             "    subs r2, #32                                 \n"
 122             "    ldmia r2!, {r4-r7}                           \n" /* r4-r7 contain half of the hardware saved context. */
 123             "    stmia r3!, {r4-r7}                           \n" /* Copy half of the the hardware saved context on the task stack. */
 124             "    ldmia r2!, {r4-r7}                           \n" /* r4-r7 contain rest half of the hardware saved context. */
 125             "    stmia r3!, {r4-r7}                           \n" /* Copy rest half of the the hardware saved context on the task stack. */
 126             "    subs r2, #48                                 \n"
 127             "    ldmia r2!, {r4-r7}                           \n" /* Restore r8-r11. */
 128             "    mov r8, r4                                   \n" /* r8 = r4. */
 129             "    mov r9, r5                                   \n" /* r9 = r5. */
 130             "    mov r10, r6                                  \n" /* r10 = r6. */
 131             "    mov r11, r7                                  \n" /* r11 = r7. */
 132             "    subs r2, #32                                 \n"
 133             "    ldmia r2!, {r4-r7}                           \n" /* Restore r4-r7. */
 134             "    subs r2, #16                                 \n"
 135             "                                                 \n"
 136             " restore_context_done_first_task:                \n"
 137             "    str r2, [r1]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
 138             "    bx lr                                        \n"
 139         );
 140     }
 141
 142 #else /* configENABLE_MPU */
 143
 144     void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
 145     {
 146         __asm volatile
 147         (
 148             "   .syntax unified                                 \n"
 149             "                                                   \n"
 150             "   ldr  r2, =pxCurrentTCB                          \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
 151             "   ldr  r3, [r2]                                   \n" /* Read pxCurrentTCB. */
 152             "   ldr  r0, [r3]                                   \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
 153             "                                                   \n"
 154             "   ldm  r0!, {r1-r3}                               \n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
 155             "   ldr  r4, =xSecureContext                        \n"
 156             "   str  r1, [r4]                                   \n" /* Set xSecureContext to this task's value for the same. */
 157             "   movs r1, #2                                     \n" /* r1 = 2. */
 158             "   msr  CONTROL, r1                                \n" /* Switch to use PSP in the thread mode. */
 159             "   adds r0, #32                                    \n" /* Discard everything up to r0. */
 160             "   msr  psp, r0                                    \n" /* This is now the new top of stack to use in the task. */
 161             "   isb                                             \n"
 162             "   bx   r3                                         \n" /* Finally, branch to EXC_RETURN. */
 163         );
 164     }
 165
 166 #endif /* configENABLE_MPU */
 167 /*-----------------------------------------------------------*/
 168
 169 BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
 170 {
 171     __asm volatile
 172     (
 173         "   .syntax unified                                 \n"
 174         "                                                   \n"
 175         "   mrs r0, control                                 \n" /* r0 = CONTROL. */
 176         "   movs r1, #1                                     \n" /* r1 = 1. */
 177         "   tst r0, r1                                      \n" /* Perform r0 & r1 (bitwise AND) and update the conditions flag. */
 178         "   beq running_privileged                          \n" /* If the result of previous AND operation was 0, branch. */
 179         "   movs r0, #0                                     \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
 180         "   bx lr                                           \n" /* Return. */
 181         " running_privileged:                               \n"
 182         "   movs r0, #1                                     \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
 183         "   bx lr                                           \n" /* Return. */
 184         ::: "r0", "r1", "memory"
 185     );
 186 }
 187 /*-----------------------------------------------------------*/
 188
 189 void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
 190 {
 191     __asm volatile
 192     (
 193         "   .syntax unified                                 \n"
 194         "                                                   \n"
 195         "   mrs r0, control                                 \n" /* Read the CONTROL register. */
 196         "   movs r1, #1                                     \n" /* r1 = 1. */
 197         "   bics r0, r1                                     \n" /* Clear the bit 0. */
 198         "   msr control, r0                                 \n" /* Write back the new CONTROL value. */
 199         "   bx lr                                           \n" /* Return to the caller. */
 200         ::: "r0", "r1", "memory"
 201     );
 202 }
 203 /*-----------------------------------------------------------*/
 204
 205 void vResetPrivilege( void ) /* __attribute__ (( naked )) */
 206 {
 207     __asm volatile
 208     (
 209         "   .syntax unified                                 \n"
 210         "                                                   \n"
 211         "   mrs r0, control                                 \n" /* r0 = CONTROL. */
 212         "   movs r1, #1                                     \n" /* r1 = 1. */
 213         "   orrs r0, r1                                     \n" /* r0 = r0 | r1. */
 214         "   msr control, r0                                 \n" /* CONTROL = r0. */
 215         "   bx lr                                           \n" /* Return to the caller. */
 216         ::: "r0", "r1", "memory"
 217     );
 218 }
 219 /*-----------------------------------------------------------*/
 220
 221 void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
 222 {
 223     __asm volatile
 224     (
 225         "   .syntax unified                                 \n"
 226         "                                                   \n"
 227         "   ldr r0, =0xe000ed08                             \n" /* Use the NVIC offset register to locate the stack. */
 228         "   ldr r0, [r0]                                    \n" /* Read the VTOR register which gives the address of vector table. */
 229         "   ldr r0, [r0]                                    \n" /* The first entry in vector table is stack pointer. */
 230         "   msr msp, r0                                     \n" /* Set the MSP back to the start of the stack. */
 231         "   cpsie i                                         \n" /* Globally enable interrupts. */
 232         "   dsb                                             \n"
 233         "   isb                                             \n"
 234         "   svc %0                                          \n" /* System call to start the first task. */
 235         "   nop                                             \n"
 236         ::"i" ( portSVC_START_SCHEDULER ) : "memory"
 237     );
 238 }
 239 /*-----------------------------------------------------------*/
 240
 241 uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
 242 {
 243     __asm volatile
 244     (
 245         "   .syntax unified                                 \n"
 246         "                                                   \n"
 247         "   mrs r0, PRIMASK                                 \n"
 248         "   cpsid i                                         \n"
 249         "   bx lr                                           \n"
 250         ::: "memory"
 251     );
 252 }
 253 /*-----------------------------------------------------------*/
 254
 255 void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
 256 {
 257     __asm volatile
 258     (
 259         "   .syntax unified                                 \n"
 260         "                                                   \n"
 261         "   msr PRIMASK, r0                                 \n"
 262         "   bx lr                                           \n"
 263         ::: "memory"
 264     );
 265 }
 266 /*-----------------------------------------------------------*/
 267
 268 #if ( configENABLE_MPU == 1 )
 269
 270     void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
 271     {
 272         __asm volatile
 273         (
 274             " .syntax unified                                 \n"
 275             " .extern SecureContext_SaveContext               \n"
 276             " .extern SecureContext_LoadContext               \n"
 277             "                                                 \n"
 278             " ldr r3, =xSecureContext                         \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
 279             " ldr r0, [r3]                                    \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
 280             " ldr r3, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
 281             " ldr r1, [r3]                                    \n" /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later.*/
 282             " ldr r2, [r1]                                    \n" /* r2 = Location in TCB where the context should be saved. */
 283             "                                                 \n"
 284             " cbz r0, save_ns_context                         \n" /* No secure context to save. */
 285             " save_s_context:                                 \n"
 286             "    push {r0-r2, lr}                             \n"
 287             "    bl SecureContext_SaveContext                 \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
 288             "    pop {r0-r3}                                  \n" /* LR is now in r3. */
 289             "    mov lr, r3                                   \n" /* Restore LR. */
 290             "                                                 \n"
 291             " save_ns_context:                                \n"
 292             "    mov r3, lr                                   \n" /* r3 = LR (EXC_RETURN). */
 293             "    lsls r3, r3, #25                             \n" /* r3 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
 294             "    bmi save_special_regs                        \n" /* r3 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */
 295             "                                                 \n"
 296             " save_general_regs:                              \n"
 297             "    mrs r3, psp                                  \n"
 298             "    stmia r2!, {r4-r7}                           \n" /* Store r4-r7. */
 299             "    mov r4, r8                                   \n" /* r4 = r8. */
 300             "    mov r5, r9                                   \n" /* r5 = r9. */
 301             "    mov r6, r10                                  \n" /* r6 = r10. */
 302             "    mov r7, r11                                  \n" /* r7 = r11. */
 303             "    stmia r2!, {r4-r7}                           \n" /* Store r8-r11. */
 304             "    ldmia r3!, {r4-r7}                           \n" /* Copy half of the  hardware saved context into r4-r7. */
 305             "    stmia r2!, {r4-r7}                           \n" /* Store the hardware saved context. */
 306             "    ldmia r3!, {r4-r7}                           \n" /* Copy rest half of the  hardware saved context into r4-r7. */
 307             "    stmia r2!, {r4-r7}                           \n" /* Store the hardware saved context. */
 308             "                                                 \n"
 309             " save_special_regs:                              \n"
 310             "    mrs r3, psp                                  \n" /* r3 = PSP. */
 311             "    movs r4, #0                                  \n" /* r4 = 0. 0 is stored in the PSPLIM slot. */
 312             "    mrs r5, control                              \n" /* r5 = CONTROL. */
 313             "    mov r6, lr                                   \n" /* r6 = LR. */
 314             "    stmia r2!, {r0, r3-r6}                       \n" /* Store xSecureContext, original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
 315             "    str r2, [r1]                                 \n" /* Save the location from where the context should be restored as the first member of TCB. */
 316             "                                                 \n"
 317             " select_next_task:                               \n"
 318             "    cpsid i                                      \n"
 319             "    bl vTaskSwitchContext                        \n"
 320             "    cpsie i                                      \n"
 321             "                                                 \n"
 322             " program_mpu:                                    \n"
 323             "    ldr r3, =pxCurrentTCB                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
 324             "    ldr r0, [r3]                                 \n" /* r0 = pxCurrentTCB.*/
 325             "                                                 \n"
 326             "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
 327             "    ldr r1, =0xe000ed94                          \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
 328             "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
 329             "    movs r3, #1                                  \n" /* r3 = 1. */
 330             "    bics r2, r3                                  \n" /* r2 = r2 & ~r3 i.e. Clear the bit 0 in r2. */
 331             "    str r2, [r1]                                 \n" /* Disable MPU. */
 332             "                                                 \n"
 333             "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
 334             "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
 335             "    ldr r2, =0xe000edc0                          \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
 336             "    str r1, [r2]                                 \n" /* Program MAIR0. */
 337             "                                                 \n"
 338             "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
 339             "    ldr r1, =0xe000ed98                          \n" /* r1 = 0xe000ed98 [Location of RNR]. */
 340             "                                                 \n"
 341             "    movs r3, #4                                  \n" /* r3 = 4. */
 342             "    str r3, [r1]                                 \n" /* Program RNR = 4. */
 343             "    ldmia r0!, {r4-r5}                           \n" /* Read first set of RBAR/RLAR registers from TCB. */
 344             "    ldr r2, =0xe000ed9c                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
 345             "    stmia r2!, {r4-r5}                           \n" /* Write first set of RBAR/RLAR registers. */
 346             "    movs r3, #5                                  \n" /* r3 = 5. */
 347             "    str r3, [r1]                                 \n" /* Program RNR = 5. */
 348             "    ldmia r0!, {r4-r5}                           \n" /* Read second set of RBAR/RLAR registers from TCB. */
 349             "    ldr r2, =0xe000ed9c                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
 350             "    stmia r2!, {r4-r5}                           \n" /* Write second set of RBAR/RLAR registers. */
 351             "    movs r3, #6                                  \n" /* r3 = 6. */
 352             "    str r3, [r1]                                 \n" /* Program RNR = 6. */
 353             "    ldmia r0!, {r4-r5}                           \n" /* Read third set of RBAR/RLAR registers from TCB. */
 354             "    ldr r2, =0xe000ed9c                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
 355             "    stmia r2!, {r4-r5}                           \n" /* Write third set of RBAR/RLAR registers. */
 356             "    movs r3, #7                                  \n" /* r3 = 6. */
 357             "    str r3, [r1]                                 \n" /* Program RNR = 7. */
 358             "    ldmia r0!, {r4-r5}                           \n" /* Read fourth set of RBAR/RLAR registers from TCB. */
 359             "    ldr r2, =0xe000ed9c                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
 360             "    stmia r2!, {r4-r5}                           \n" /* Write fourth set of RBAR/RLAR registers. */
 361             "                                                 \n"
 362             "    ldr r1, =0xe000ed94                          \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
 363             "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
 364             "    movs r3, #1                                  \n" /* r3 = 1. */
 365             "    orrs r2, r3                                  \n" /* r2 = r2 | r3 i.e. Set the bit 0 in r2. */
 366             "    str r2, [r1]                                 \n" /* Enable MPU. */
 367             "    dsb                                          \n" /* Force memory writes before continuing. */
 368             "                                                 \n"
 369             " restore_context:                                \n"
 370             "    ldr r3, =pxCurrentTCB                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
 371             "    ldr r1, [r3]                                 \n" /* r1 = pxCurrentTCB.*/
 372             "    ldr r2, [r1]                                 \n" /* r2 = Location of saved context in TCB. */
 373             "                                                 \n"
 374             " restore_special_regs:                           \n"
 375             "    subs r2, #20                                 \n"
 376             "    ldmia r2!, {r0, r3-r6}                       \n" /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, r6 = LR. */
 377             "    subs r2, #20                                 \n"
 378             "    msr psp, r3                                  \n"
 379             "    msr control, r5                              \n"
 380             "    mov lr, r6                                   \n"
 381             "    ldr r4, =xSecureContext                      \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
 382             "    str r0, [r4]                                 \n" /* Restore xSecureContext. */
 383             "    cbz r0, restore_ns_context                   \n" /* No secure context to restore. */
 384             "                                                 \n"
 385             " restore_s_context:                              \n"
 386             "    push {r1-r3, lr}                             \n"
 387             "    bl SecureContext_LoadContext                 \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
 388             "    pop {r1-r4}                                  \n" /* LR is now in r4. */
 389             "    mov lr, r4                                   \n"
 390             "                                                 \n"
 391             " restore_ns_context:                             \n"
 392             "    mov r0, lr                                   \n" /* r0 = LR (EXC_RETURN). */
 393             "    lsls r0, r0, #25                             \n" /* r0 = r0 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
 394             "    bmi restore_context_done                     \n" /* r0 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */
 395             "                                                 \n"
 396             " restore_general_regs:                           \n"
 397             "    subs r2, #32                                 \n"
 398             "    ldmia r2!, {r4-r7}                           \n" /* r4-r7 contain half of the hardware saved context. */
 399             "    stmia r3!, {r4-r7}                           \n" /* Copy half of the the hardware saved context on the task stack. */
 400             "    ldmia r2!, {r4-r7}                           \n" /* r4-r7 contain rest half of the hardware saved context. */
 401             "    stmia r3!, {r4-r7}                           \n" /* Copy rest half of the the hardware saved context on the task stack. */
 402             "    subs r2, #48                                 \n"
 403             "    ldmia r2!, {r4-r7}                           \n" /* Restore r8-r11. */
 404             "    mov r8, r4                                   \n" /* r8 = r4. */
 405             "    mov r9, r5                                   \n" /* r9 = r5. */
 406             "    mov r10, r6                                  \n" /* r10 = r6. */
 407             "    mov r11, r7                                  \n" /* r11 = r7. */
 408             "    subs r2, #32                                 \n"
 409             "    ldmia r2!, {r4-r7}                           \n" /* Restore r4-r7. */
 410             "    subs r2, #16                                 \n"
 411             "                                                 \n"
 412             " restore_context_done:                           \n"
 413             "    str r2, [r1]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
 414             "    bx lr                                        \n"
 415         );
 416     }
 417
 418 #else /* configENABLE_MPU */
 419
 420     void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
 421     {
 422         __asm volatile
 423         (
 424             "   .syntax unified                                 \n"
 425             "   .extern SecureContext_SaveContext               \n"
 426             "   .extern SecureContext_LoadContext               \n"
 427             "                                                   \n"
 428             "   ldr r3, =xSecureContext                         \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
 429             "   ldr r0, [r3]                                    \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
 430             "   ldr r3, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
 431             "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later.*/
 432             "   mrs r2, psp                                     \n" /* Read PSP in r2. */
 433             "                                                   \n"
 434             "   cbz r0, save_ns_context                         \n" /* No secure context to save. */
 435             "   push {r0-r2, r14}                               \n"
 436             "   bl SecureContext_SaveContext                    \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
 437             "   pop {r0-r3}                                     \n" /* LR is now in r3. */
 438             "   mov lr, r3                                      \n" /* LR = r3. */
 439             "   lsls r1, r3, #25                                \n" /* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
 440             "   bpl save_ns_context                             \n" /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
 441             "   ldr r3, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
 442             "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB. */
 443             "   subs r2, r2, #12                                \n" /* Make space for xSecureContext, PSPLIM and LR on the stack. */
 444             "   str r2, [r1]                                    \n" /* Save the new top of stack in TCB. */
 445             "   movs r1, #0                                     \n" /* r1 = 0. 0 is stored in the PSPLIM slot. */
 446             "   mov r3, lr                                      \n" /* r3 = LR/EXC_RETURN. */
 447             "   stmia r2!, {r0, r1, r3}                         \n" /* Store xSecureContext, PSPLIM and LR on the stack. */
 448             "   b select_next_task                              \n"
 449             "                                                   \n"
 450             " save_ns_context:                                  \n"
 451             "   ldr r3, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
 452             "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB. */
 453             "   subs r2, r2, #44                                \n" /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
 454             "   str r2, [r1]                                    \n" /* Save the new top of stack in TCB. */
 455             "   movs r1, #0                                     \n" /* r1 = 0. 0 is stored in the PSPLIM slot. */
 456             "   mov r3, lr                                      \n" /* r3 = LR/EXC_RETURN. */
 457             "   stmia r2!, {r0, r1, r3-r7}                      \n" /* Store xSecureContext, PSPLIM, LR and the low registers that are not saved automatically. */
 458             "   mov r4, r8                                      \n" /* r4 = r8. */
 459             "   mov r5, r9                                      \n" /* r5 = r9. */
 460             "   mov r6, r10                                     \n" /* r6 = r10. */
 461             "   mov r7, r11                                     \n" /* r7 = r11. */
 462             "   stmia r2!, {r4-r7}                              \n" /* Store the high registers that are not saved automatically. */
 463             "                                                   \n"
 464             " select_next_task:                                 \n"
 465             "   cpsid i                                         \n"
 466             "   bl vTaskSwitchContext                           \n"
 467             "   cpsie i                                         \n"
 468             "                                                   \n"
 469             "   ldr r3, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
 470             "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB. */
 471             "   ldr r2, [r1]                                    \n" /* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */
 472             "                                                   \n"
 473             "   ldmia r2!, {r0, r1, r4}                         \n" /* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */
 474             "   mov lr, r4                                      \n" /* LR = r4. */
 475             "   ldr r3, =xSecureContext                         \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
 476             "   str r0, [r3]                                    \n" /* Restore the task's xSecureContext. */
 477             "   cbz r0, restore_ns_context                      \n" /* If there is no secure context for the task, restore the non-secure context. */
 478             "   ldr r3, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
 479             "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB. */
 480             "   push {r2, r4}                                   \n"
 481             "   bl SecureContext_LoadContext                    \n" /* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
 482             "   pop {r2, r4}                                    \n"
 483             "   mov lr, r4                                      \n" /* LR = r4. */
 484             "   lsls r1, r4, #25                                \n" /* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
 485             "   bpl restore_ns_context                          \n" /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
 486             "   msr psp, r2                                     \n" /* Remember the new top of stack for the task. */
 487             "   bx lr                                           \n"
 488             "                                                   \n"
 489             " restore_ns_context:                               \n"
 490             "   adds r2, r2, #16                                \n" /* Move to the high registers. */
 491             "   ldmia r2!, {r4-r7}                              \n" /* Restore the high registers that are not automatically restored. */
 492             "   mov r8, r4                                      \n" /* r8 = r4. */
 493             "   mov r9, r5                                      \n" /* r9 = r5. */
 494             "   mov r10, r6                                     \n" /* r10 = r6. */
 495             "   mov r11, r7                                     \n" /* r11 = r7. */
 496             "   msr psp, r2                                     \n" /* Remember the new top of stack for the task. */
 497             "   subs r2, r2, #32                                \n" /* Go back to the low registers. */
 498             "   ldmia r2!, {r4-r7}                              \n" /* Restore the low registers that are not automatically restored. */
 499             "   bx lr                                           \n"
 500         );
 501     }
 502
 503 #endif /* configENABLE_MPU */
 504 /*-----------------------------------------------------------*/
 505
 506 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 507
 508     void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
 509     {
 510         __asm volatile
 511         (
 512             ".syntax unified                \n"
 513             ".extern vPortSVCHandler_C      \n"
 514             ".extern vSystemCallEnter       \n"
 515             ".extern vSystemCallExit        \n"
 516             "                               \n"
 517             "movs r0, #4                    \n"
 518             "mov r1, lr                     \n"
 519             "tst r0, r1                     \n"
 520             "beq stack_on_msp               \n"
 521             "stack_on_psp:                  \n"
 522             "    mrs r0, psp                \n"
 523             "    b route_svc                \n"
 524             "stack_on_msp:                  \n"
 525             "    mrs r0, msp                \n"
 526             "    b route_svc                \n"
 527             "                               \n"
 528             "route_svc:                     \n"
 529             "    ldr r3, [r0, #24]          \n"
 530             "    subs r3, #2                \n"
 531             "    ldrb r2, [r3, #0]          \n"
 532             "    cmp r2, %0                 \n"
 533             "    blt system_call_enter      \n"
 534             "    cmp r2, %1                 \n"
 535             "    beq system_call_exit       \n"
 536             "    b vPortSVCHandler_C        \n"
 537             "                               \n"
 538             "system_call_enter:             \n"
 539             "    b vSystemCallEnter         \n"
 540             "system_call_exit:              \n"
 541             "    b vSystemCallExit          \n"
 542             "                               \n"
 543             : /* No outputs. */
 544             : "i" ( NUM_SYSTEM_CALLS ), "i" ( portSVC_SYSTEM_CALL_EXIT )
 545             : "r0", "r1", "r2", "r3", "memory"
 546         );
 547     }
 548
 549 #else /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 550
 551     void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
 552     {
 553         __asm volatile
 554         (
 555             "   .syntax unified                                 \n"
 556             "                                                   \n"
 557             "   movs r0, #4                                     \n"
 558             "   mov r1, lr                                      \n"
 559             "   tst r0, r1                                      \n"
 560             "   beq stacking_used_msp                           \n"
 561             "   mrs r0, psp                                     \n"
 562             "   ldr r2, =vPortSVCHandler_C                      \n"
 563             "   bx r2                                           \n"
 564             " stacking_used_msp:                                \n"
 565             "   mrs r0, msp                                     \n"
 566             "   ldr r2, =vPortSVCHandler_C                      \n"
 567             "   bx r2                                           \n"
 568         );
 569     }
 570
 571 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 572 /*-----------------------------------------------------------*/
 573
 574 void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) /* __attribute__ (( naked )) */
 575 {
 576     __asm volatile
 577     (
 578         "   .syntax unified                                 \n"
 579         "                                                   \n"
 580         "   svc %0                                          \n" /* Secure context is allocated in the supervisor call. */
 581         "   bx lr                                           \n" /* Return. */
 582         ::"i" ( portSVC_ALLOCATE_SECURE_CONTEXT ) : "memory"
 583     );
 584 }
 585 /*-----------------------------------------------------------*/
 586
 587 void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
 588 {
 589     __asm volatile
 590     (
 591         "   .syntax unified                                 \n"
 592         "                                                   \n"
 593         "   ldr r2, [r0]                                    \n" /* The first item in the TCB is the top of the stack. */
 594         "   ldr r1, [r2]                                    \n" /* The first item on the stack is the task's xSecureContext. */
 595         "   cmp r1, #0                                      \n" /* Raise svc if task's xSecureContext is not NULL. */
 596         "   bne free_secure_context                         \n" /* Branch if r1 != 0. */
 597         "   bx lr                                           \n" /* There is no secure context (xSecureContext is NULL). */
 598         " free_secure_context:                              \n"
 599         "   svc %0                                          \n" /* Secure context is freed in the supervisor call. */
 600         "   bx lr                                           \n" /* Return. */
 601         ::"i" ( portSVC_FREE_SECURE_CONTEXT ) : "memory"
 602     );
 603 }
 604 /*-----------------------------------------------------------*/