2 * FreeRTOS Kernel V11.2.0
3 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
5 * SPDX-License-Identifier: MIT
7 * Permission is hereby granted, free of charge, to any person obtaining a copy of
8 * this software and associated documentation files (the "Software"), to deal in
9 * the Software without restriction, including without limitation the rights to
10 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
11 * the Software, and to permit persons to whom the Software is furnished to do so,
12 * subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included in all
15 * copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
19 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
20 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
21 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
22 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * https://www.FreeRTOS.org
25 * https://github.com/FreeRTOS
33 #include <avr/interrupt.h>
39 /*-----------------------------------------------------------
40 * Implementation of functions defined in portable.h for the AVR port.
41 *----------------------------------------------------------*/
43 /* Start tasks with interrupts enabled. */
44 #define portFLAGS_INT_ENABLED ( ( StackType_t ) 0x80 )
46 #if defined( portUSE_WDTO )
47 #warning "Watchdog Timer used for scheduler."
48 #define portSCHEDULER_ISR WDT_vect
50 #elif defined( portUSE_TIMER0 )
51 /* Hardware constants for Timer0. */
52 #warning "Timer0 used for scheduler."
53 #define portSCHEDULER_ISR TIMER0_COMPA_vect
54 #define portCLEAR_COUNTER_ON_MATCH ( ( uint8_t ) _BV( WGM01 ) )
55 #define portPRESCALE_1024 ( ( uint8_t ) ( _BV( CS02 ) | _BV( CS00 ) ) )
56 #define portCLOCK_PRESCALER ( ( uint32_t ) 1024 )
57 #define portCOMPARE_MATCH_A_INTERRUPT_ENABLE ( ( uint8_t ) _BV( OCIE0A ) )
58 #define portOCRL OCR0A
59 #define portTCCRa TCCR0A
60 #define portTCCRb TCCR0B
61 #define portTIMSK TIMSK0
62 #define portTIFR TIFR0
64 #else /* if defined( portUSE_WDTO ) */
65 #error "No Timer defined for scheduler"
66 #endif /* if defined( portUSE_WDTO ) */
68 /*-----------------------------------------------------------*/
70 /* We require the address of the pxCurrentTCB variable, but don't want to know
71 * any details of its type. */
73 extern volatile TCB_t * volatile pxCurrentTCB;
75 /*-----------------------------------------------------------*/
78 * Enable the watchdog timer, configuring it for expire after
79 * (value) timeout (which is a combination of the WDP0
82 * This function is derived from <avr/wdt.h> but enables only
83 * the interrupt bit (WDIE), rather than the reset bit (WDE).
85 * Can't find it documented but the WDT, once enabled,
86 * rolls over and fires a new interrupt each time.
88 * See also the symbolic constants WDTO_15MS et al.
90 * Updated to match avr-libc 2.0.0
93 #if defined( portUSE_WDTO )
96 __attribute__( ( __always_inline__ ) )
97 void wdt_interrupt_enable( const uint8_t value )
99 if( _SFR_IO_REG_P( _WD_CONTROL_REG ) )
101 __asm__ __volatile__ (
102 "in __tmp_reg__,__SREG__" "\n\t"
106 "out __SREG__,__tmp_reg__" "\n\t"
109 : "I" ( _SFR_IO_ADDR( _WD_CONTROL_REG ) ),
110 "r" ( ( uint8_t ) ( _BV( _WD_CHANGE_BIT ) | _BV( WDE ) ) ),
111 "r" ( ( uint8_t ) ( ( value & 0x08 ? _WD_PS3_MASK : 0x00 ) |
112 _BV( WDIF ) | _BV( WDIE ) | ( value & 0x07 ) ) )
118 __asm__ __volatile__ (
119 "in __tmp_reg__,__SREG__" "\n\t"
123 "out __SREG__,__tmp_reg__" "\n\t"
126 : "n" ( _SFR_MEM_ADDR( _WD_CONTROL_REG ) ),
127 "r" ( ( uint8_t ) ( _BV( _WD_CHANGE_BIT ) | _BV( WDE ) ) ),
128 "r" ( ( uint8_t ) ( ( value & 0x08 ? _WD_PS3_MASK : 0x00 ) |
129 _BV( WDIF ) | _BV( WDIE ) | ( value & 0x07 ) ) )
134 #endif /* if defined( portUSE_WDTO ) */
136 /*-----------------------------------------------------------*/
139 * Enable the watchdog timer, configuring it for expire after
140 * (value) timeout (which is a combination of the WDP0
141 * through WDP3 bits).
143 * This function is derived from <avr/wdt.h> but enables both
144 * the reset bit (WDE), and the interrupt bit (WDIE).
146 * This will ensure that if the interrupt is not serviced
147 * before the second timeout, the AVR will reset.
149 * Servicing the interrupt automatically clears it,
150 * and ensures the AVR does not reset.
152 * Can't find it documented but the WDT, once enabled,
153 * rolls over and fires a new interrupt each time.
155 * See also the symbolic constants WDTO_15MS et al.
157 * Updated to match avr-libc 2.0.0
160 #if defined( portUSE_WDTO )
163 __attribute__( ( __always_inline__ ) )
164 void wdt_interrupt_reset_enable( const uint8_t value )
166 if( _SFR_IO_REG_P( _WD_CONTROL_REG ) )
168 __asm__ __volatile__ (
169 "in __tmp_reg__,__SREG__" "\n\t"
173 "out __SREG__,__tmp_reg__" "\n\t"
176 : "I" ( _SFR_IO_ADDR( _WD_CONTROL_REG ) ),
177 "r" ( ( uint8_t ) ( _BV( _WD_CHANGE_BIT ) | _BV( WDE ) ) ),
178 "r" ( ( uint8_t ) ( ( value & 0x08 ? _WD_PS3_MASK : 0x00 ) |
179 _BV( WDIF ) | _BV( WDIE ) | _BV( WDE ) | ( value & 0x07 ) ) )
185 __asm__ __volatile__ (
186 "in __tmp_reg__,__SREG__" "\n\t"
190 "out __SREG__,__tmp_reg__" "\n\t"
193 : "n" ( _SFR_MEM_ADDR( _WD_CONTROL_REG ) ),
194 "r" ( ( uint8_t ) ( _BV( _WD_CHANGE_BIT ) | _BV( WDE ) ) ),
195 "r" ( ( uint8_t ) ( ( value & 0x08 ? _WD_PS3_MASK : 0x00 ) |
196 _BV( WDIF ) | _BV( WDIE ) | _BV( WDE ) | ( value & 0x07 ) ) )
201 #endif /* if defined( portUSE_WDTO ) */
203 /*-----------------------------------------------------------*/
206 * Macro to save all the general purpose registers, the save the stack pointer
209 * The first thing we do is save the flags then disable interrupts. This is to
210 * guard our stack against having a context switch interrupt after we have already
211 * pushed the registers onto the stack - causing the 32 registers to be on the
214 * r1 is set to zero (__zero_reg__) as the compiler expects it to be thus, however
215 * some of the math routines make use of R1.
217 * r0 is set to __tmp_reg__ as the compiler expects it to be thus.
219 * #if defined(__AVR_HAVE_RAMPZ__)
220 * #define __RAMPZ__ 0x3B
223 * #if defined(__AVR_3_BYTE_PC__)
224 * #define __EIND__ 0x3C
227 * The interrupts will have been disabled during the call to portSAVE_CONTEXT()
228 * so we need not worry about reading/writing to the stack pointer.
230 #if defined( __AVR_3_BYTE_PC__ ) && defined( __AVR_HAVE_RAMPZ__ )
231 /* 3-Byte PC Save with RAMPZ */
232 #define portSAVE_CONTEXT() \
233 __asm__ __volatile__ ( "push __tmp_reg__ \n\t" \
234 "in __tmp_reg__, __SREG__ \n\t" \
236 "push __tmp_reg__ \n\t" \
237 "in __tmp_reg__, 0x3B \n\t" \
238 "push __tmp_reg__ \n\t" \
239 "in __tmp_reg__, 0x3C \n\t" \
240 "push __tmp_reg__ \n\t" \
241 "push __zero_reg__ \n\t" \
242 "clr __zero_reg__ \n\t" \
273 "lds r26, pxCurrentTCB \n\t" \
274 "lds r27, pxCurrentTCB + 1 \n\t" \
275 "in __tmp_reg__, __SP_L__ \n\t" \
276 "st x+, __tmp_reg__ \n\t" \
277 "in __tmp_reg__, __SP_H__ \n\t" \
278 "st x+, __tmp_reg__ \n\t" \
280 #elif defined( __AVR_HAVE_RAMPZ__ )
281 /* 2-Byte PC Save with RAMPZ */
282 #define portSAVE_CONTEXT() \
283 __asm__ __volatile__ ( "push __tmp_reg__ \n\t" \
284 "in __tmp_reg__, __SREG__ \n\t" \
286 "push __tmp_reg__ \n\t" \
287 "in __tmp_reg__, 0x3B \n\t" \
288 "push __tmp_reg__ \n\t" \
289 "push __zero_reg__ \n\t" \
290 "clr __zero_reg__ \n\t" \
321 "lds r26, pxCurrentTCB \n\t" \
322 "lds r27, pxCurrentTCB + 1 \n\t" \
323 "in __tmp_reg__, __SP_L__ \n\t" \
324 "st x+, __tmp_reg__ \n\t" \
325 "in __tmp_reg__, __SP_H__ \n\t" \
326 "st x+, __tmp_reg__ \n\t" \
328 #else /* if defined( __AVR_3_BYTE_PC__ ) && defined( __AVR_HAVE_RAMPZ__ ) */
330 #define portSAVE_CONTEXT() \
331 __asm__ __volatile__ ( "push __tmp_reg__ \n\t" \
332 "in __tmp_reg__, __SREG__ \n\t" \
334 "push __tmp_reg__ \n\t" \
335 "push __zero_reg__ \n\t" \
336 "clr __zero_reg__ \n\t" \
367 "lds r26, pxCurrentTCB \n\t" \
368 "lds r27, pxCurrentTCB + 1 \n\t" \
369 "in __tmp_reg__, __SP_L__ \n\t" \
370 "st x+, __tmp_reg__ \n\t" \
371 "in __tmp_reg__, __SP_H__ \n\t" \
372 "st x+, __tmp_reg__ \n\t" \
374 #endif /* if defined( __AVR_3_BYTE_PC__ ) && defined( __AVR_HAVE_RAMPZ__ ) */
377 * Opposite to portSAVE_CONTEXT(). Interrupts will have been disabled during
378 * the context save so we can write to the stack pointer.
380 #if defined( __AVR_3_BYTE_PC__ ) && defined( __AVR_HAVE_RAMPZ__ )
381 /* 3-Byte PC Restore with RAMPZ */
382 #define portRESTORE_CONTEXT() \
383 __asm__ __volatile__ ( "lds r26, pxCurrentTCB \n\t" \
384 "lds r27, pxCurrentTCB + 1 \n\t" \
386 "out __SP_L__, r28 \n\t" \
388 "out __SP_H__, r29 \n\t" \
419 "pop __zero_reg__ \n\t" \
420 "pop __tmp_reg__ \n\t" \
421 "out 0x3C, __tmp_reg__ \n\t" \
422 "pop __tmp_reg__ \n\t" \
423 "out 0x3B, __tmp_reg__ \n\t" \
424 "pop __tmp_reg__ \n\t" \
425 "out __SREG__, __tmp_reg__ \n\t" \
426 "pop __tmp_reg__ \n\t" \
428 #elif defined( __AVR_HAVE_RAMPZ__ )
429 /* 2-Byte PC Restore with RAMPZ */
430 #define portRESTORE_CONTEXT() \
431 __asm__ __volatile__ ( "lds r26, pxCurrentTCB \n\t" \
432 "lds r27, pxCurrentTCB + 1 \n\t" \
434 "out __SP_L__, r28 \n\t" \
436 "out __SP_H__, r29 \n\t" \
467 "pop __zero_reg__ \n\t" \
468 "pop __tmp_reg__ \n\t" \
469 "out 0x3B, __tmp_reg__ \n\t" \
470 "pop __tmp_reg__ \n\t" \
471 "out __SREG__, __tmp_reg__ \n\t" \
472 "pop __tmp_reg__ \n\t" \
474 #else /* if defined( __AVR_3_BYTE_PC__ ) && defined( __AVR_HAVE_RAMPZ__ ) */
475 /* 2-Byte PC Restore */
476 #define portRESTORE_CONTEXT() \
477 __asm__ __volatile__ ( "lds r26, pxCurrentTCB \n\t" \
478 "lds r27, pxCurrentTCB + 1 \n\t" \
480 "out __SP_L__, r28 \n\t" \
482 "out __SP_H__, r29 \n\t" \
513 "pop __zero_reg__ \n\t" \
514 "pop __tmp_reg__ \n\t" \
515 "out __SREG__, __tmp_reg__ \n\t" \
516 "pop __tmp_reg__ \n\t" \
518 #endif /* if defined( __AVR_3_BYTE_PC__ ) && defined( __AVR_HAVE_RAMPZ__ ) */
519 /*-----------------------------------------------------------*/
522 * Perform hardware setup to enable ticks from relevant Timer.
524 static void prvSetupTimerInterrupt( void );
525 /*-----------------------------------------------------------*/
528 * See header file for description.
530 StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
531 TaskFunction_t pxCode,
532 void * pvParameters )
536 /* Simulate how the stack would look after a call to vPortYield() generated by
539 /* The start of the task code will be popped off the stack last, so place
541 usAddress = ( uint16_t ) pxCode;
542 *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
546 *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
549 #if defined( __AVR_3_BYTE_PC__ )
551 /* The AVR ATmega2560/ATmega2561 have 256KBytes of program memory and a 17-bit
552 * program counter. When a code address is stored on the stack, it takes 3 bytes
553 * instead of 2 for the other ATmega* chips.
555 * Store 0 as the top byte since we force all task routines to the bottom 128K
556 * of flash. We do this by using the .lowtext label in the linker script.
558 * In order to do this properly, we would need to get a full 3-byte pointer to
559 * pxCode. That requires a change to GCC. Not likely to happen any time soon.
565 /* Next simulate the stack as if after a call to portSAVE_CONTEXT().
566 * portSAVE_CONTEXT places the flags on the stack immediately after r0
567 * to ensure the interrupts get disabled as soon as possible, and so ensuring
568 * the stack use is minimal should a context switch interrupt occur. */
569 *pxTopOfStack = ( StackType_t ) 0x00; /* R0 */
571 *pxTopOfStack = portFLAGS_INT_ENABLED;
574 #if defined( __AVR_3_BYTE_PC__ )
576 /* If we have an ATmega256x, we are also saving the EIND register.
577 * We should default to 0.
579 *pxTopOfStack = ( StackType_t ) 0x00; /* EIND */
583 #if defined( __AVR_HAVE_RAMPZ__ )
585 /* We are saving the RAMPZ register.
586 * We should default to 0.
588 *pxTopOfStack = ( StackType_t ) 0x00; /* RAMPZ */
592 /* Now the remaining registers. The compiler expects R1 to be 0. */
593 *pxTopOfStack = ( StackType_t ) 0x00; /* R1 */
595 /* Leave R2 - R23 untouched */
598 /* Place the parameter on the stack in the expected location. */
599 usAddress = ( uint16_t ) pvParameters;
600 *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
604 *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
606 /* Leave register R26 - R31 untouched */
611 /*-----------------------------------------------------------*/
613 BaseType_t xPortStartScheduler( void )
615 /* Setup the relevant timer hardware to generate the tick. */
616 prvSetupTimerInterrupt();
618 /* Restore the context of the first task that is going to run. */
619 portRESTORE_CONTEXT();
621 /* Simulate a function call end as generated by the compiler. We will now
622 * jump to the start of the task the context of which we have just restored. */
623 __asm__ __volatile__ ( "ret" );
625 /* Should not get here. */
628 /*-----------------------------------------------------------*/
630 void vPortEndScheduler( void )
632 /* It is unlikely that the ATmega port will get stopped. */
634 /*-----------------------------------------------------------*/
637 * Manual context switch. The first thing we do is save the registers so we
638 * can use a naked attribute.
640 void vPortYield( void ) __attribute__( ( hot, flatten, naked ) );
641 void vPortYield( void )
644 vTaskSwitchContext();
645 portRESTORE_CONTEXT();
647 __asm__ __volatile__ ( "ret" );
649 /*-----------------------------------------------------------*/
652 * Manual context switch callable from ISRs. The first thing we do is save
653 * the registers so we can use a naked attribute.
655 void vPortYieldFromISR( void ) __attribute__( ( hot, flatten, naked ) );
656 void vPortYieldFromISR( void )
659 vTaskSwitchContext();
660 portRESTORE_CONTEXT();
662 __asm__ __volatile__ ( "reti" );
664 /*-----------------------------------------------------------*/
667 * Context switch function used by the tick. This must be identical to
668 * vPortYield() from the call to vTaskSwitchContext() onwards. The only
669 * difference from vPortYield() is the tick count is incremented as the
670 * call comes from the tick ISR.
672 void vPortYieldFromTick( void ) __attribute__( ( hot, flatten, naked ) );
673 void vPortYieldFromTick( void )
677 if( xTaskIncrementTick() != pdFALSE )
679 vTaskSwitchContext();
682 portRESTORE_CONTEXT();
684 __asm__ __volatile__ ( "ret" );
686 /*-----------------------------------------------------------*/
688 #if defined( portUSE_WDTO )
691 * Setup WDT to generate a tick interrupt.
693 void prvSetupTimerInterrupt( void )
698 /* set up WDT Interrupt (rather than the WDT Reset). */
699 wdt_interrupt_enable( portUSE_WDTO );
702 #elif defined( portUSE_TIMER0 )
705 * Setup Timer0 compare match A to generate a tick interrupt.
707 static void prvSetupTimerInterrupt( void )
709 uint32_t ulCompareMatch;
712 /* Using 8bit Timer0 to generate the tick. Correct fuses must be
713 * selected for the configCPU_CLOCK_HZ clock.*/
715 ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ;
717 /* We only have 8 bits so have to scale 1024 to get our required tick rate. */
718 ulCompareMatch /= portCLOCK_PRESCALER;
720 /* Adjust for correct value. */
721 ulCompareMatch -= ( uint32_t ) 1;
723 /* Setup compare match value for compare match A. Interrupts are disabled
724 * before this is called so we need not worry here. */
725 ucLowByte = ( uint8_t ) ( ulCompareMatch & ( uint32_t ) 0xff );
726 portOCRL = ucLowByte;
728 /* Setup clock source and compare match behaviour. */
729 portTCCRa = portCLEAR_COUNTER_ON_MATCH;
730 portTCCRb = portPRESCALE_1024;
733 /* Enable the interrupt - this is okay as interrupt are currently globally disabled. */
734 ucLowByte = portTIMSK;
735 ucLowByte |= portCOMPARE_MATCH_A_INTERRUPT_ENABLE;
736 portTIMSK = ucLowByte;
739 #endif /* if defined( portUSE_WDTO ) */
741 /*-----------------------------------------------------------*/
743 #if configUSE_PREEMPTION == 1
746 * Tick ISR for preemptive scheduler. We can use a naked attribute as
747 * the context is saved at the start of vPortYieldFromTick(). The tick
748 * count is incremented after the context is saved.
750 * use ISR_NOBLOCK where there is an important timer running, that should preempt the scheduler.
753 ISR( portSCHEDULER_ISR, ISR_NAKED ) __attribute__( ( hot, flatten ) );
755 /* ISR(portSCHEDULER_ISR, ISR_NAKED ISR_NOBLOCK) __attribute__ ((hot, flatten));
757 ISR( portSCHEDULER_ISR )
759 vPortYieldFromTick();
760 __asm__ __volatile__ ( "reti" );
762 #else /* if configUSE_PREEMPTION == 1 */
765 * Tick ISR for the cooperative scheduler. All this does is increment the
766 * tick count. We don't need to switch context, this can only be done by
767 * manual calls to taskYIELD();
769 * use ISR_NOBLOCK where there is an important timer running, that should preempt the scheduler.
771 ISR( portSCHEDULER_ISR ) __attribute__( ( hot, flatten ) );
773 /* ISR(portSCHEDULER_ISR, ISR_NOBLOCK) __attribute__ ((hot, flatten));
775 ISR( portSCHEDULER_ISR )
777 xTaskIncrementTick();
779 #endif /* if configUSE_PREEMPTION == 1 */