2 * FreeRTOS Kernel V10.5.1
3 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
5 * SPDX-License-Identifier: MIT
7 * Permission is hereby granted, free of charge, to any person obtaining a copy of
8 * this software and associated documentation files (the "Software"), to deal in
9 * the Software without restriction, including without limitation the rights to
10 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
11 * the Software, and to permit persons to whom the Software is furnished to do so,
12 * subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included in all
15 * copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
19 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
20 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
21 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
22 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * https://www.FreeRTOS.org
25 * https://github.com/FreeRTOS
29 /* Standard includes. */
32 /* Scheduler includes. */
36 /* Critical nesting should be initialised to a non zero value so interrupts don't
37 accidentally get enabled before the scheduler is started. */
38 #define portINITIAL_CRITICAL_NESTING (( StackType_t ) 10)
40 /* The PSW value assigned to tasks when they start to run for the first time. */
41 #define portPSW (( StackType_t ) 0x00000000)
43 /* We require the address of the pxCurrentTCB variable, but don't want to know
44 any details of its type. */
46 extern volatile TCB_t * volatile pxCurrentTCB;
48 /* Keeps track of the nesting level of critical sections. */
49 volatile StackType_t usCriticalNesting = portINITIAL_CRITICAL_NESTING;
50 /*-----------------------------------------------------------*/
52 /* Sets up the timer to generate the tick interrupt. */
53 static void prvSetupTimerInterrupt( void );
55 /*-----------------------------------------------------------*/
56 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
58 *pxTopOfStack = ( StackType_t ) pxCode; /* Task function start address */
60 *pxTopOfStack = ( StackType_t ) pxCode; /* Task function start address */
62 *pxTopOfStack = portPSW; /* Initial PSW value */
64 *pxTopOfStack = ( StackType_t ) 0x20202020; /* Initial Value of R20 */
66 *pxTopOfStack = ( StackType_t ) 0x21212121; /* Initial Value of R21 */
68 *pxTopOfStack = ( StackType_t ) 0x22222222; /* Initial Value of R22 */
70 *pxTopOfStack = ( StackType_t ) 0x23232323; /* Initial Value of R23 */
72 *pxTopOfStack = ( StackType_t ) 0x24242424; /* Initial Value of R24 */
74 #if (__DATA_MODEL__ == 0) || (__DATA_MODEL__ == 1)
75 *pxTopOfStack = ( StackType_t ) 0x25252525; /* Initial Value of R25 */
77 #endif /* configDATA_MODE */
78 *pxTopOfStack = ( StackType_t ) 0x26262626; /* Initial Value of R26 */
80 *pxTopOfStack = ( StackType_t ) 0x27272727; /* Initial Value of R27 */
82 *pxTopOfStack = ( StackType_t ) 0x28282828; /* Initial Value of R28 */
84 *pxTopOfStack = ( StackType_t ) 0x29292929; /* Initial Value of R29 */
86 *pxTopOfStack = ( StackType_t ) 0x30303030; /* Initial Value of R30 */
88 *pxTopOfStack = ( StackType_t ) 0x19191919; /* Initial Value of R19 */
90 *pxTopOfStack = ( StackType_t ) 0x18181818; /* Initial Value of R18 */
92 *pxTopOfStack = ( StackType_t ) 0x17171717; /* Initial Value of R17 */
94 *pxTopOfStack = ( StackType_t ) 0x16161616; /* Initial Value of R16 */
96 *pxTopOfStack = ( StackType_t ) 0x15151515; /* Initial Value of R15 */
98 *pxTopOfStack = ( StackType_t ) 0x14141414; /* Initial Value of R14 */
100 *pxTopOfStack = ( StackType_t ) 0x13131313; /* Initial Value of R13 */
102 *pxTopOfStack = ( StackType_t ) 0x12121212; /* Initial Value of R12 */
104 *pxTopOfStack = ( StackType_t ) 0x11111111; /* Initial Value of R11 */
106 *pxTopOfStack = ( StackType_t ) 0x10101010; /* Initial Value of R10 */
108 *pxTopOfStack = ( StackType_t ) 0x99999999; /* Initial Value of R09 */
110 *pxTopOfStack = ( StackType_t ) 0x88888888; /* Initial Value of R08 */
112 *pxTopOfStack = ( StackType_t ) 0x77777777; /* Initial Value of R07 */
114 *pxTopOfStack = ( StackType_t ) 0x66666666; /* Initial Value of R06 */
116 *pxTopOfStack = ( StackType_t ) 0x55555555; /* Initial Value of R05 */
118 #if __DATA_MODEL__ == 0 || __DATA_MODEL__ == 1
119 *pxTopOfStack = ( StackType_t ) 0x44444444; /* Initial Value of R04 */
121 #endif /* configDATA_MODE */
122 *pxTopOfStack = ( StackType_t ) 0x22222222; /* Initial Value of R02 */
124 *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 is expected to hold the function parameter*/
126 *pxTopOfStack = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING;
129 * Return a pointer to the top of the stack we have generated so this can
130 * be stored in the task control block for the task.
134 /*-----------------------------------------------------------*/
136 BaseType_t xPortStartScheduler( void )
138 /* Setup the hardware to generate the tick. Interrupts are disabled when
139 this function is called. */
140 prvSetupTimerInterrupt();
142 /* Restore the context of the first task that is going to run. */
145 /* Should not get here as the tasks are now running! */
148 /*-----------------------------------------------------------*/
150 void vPortEndScheduler( void )
152 /* It is unlikely that the V850ES/Fx3 port will get stopped. If required simply
153 disable the tick interrupt here. */
155 /*-----------------------------------------------------------*/
158 * Hardware initialisation to generate the RTOS tick. This uses
160 static void prvSetupTimerInterrupt( void )
162 TM0CE = 0; /* TMM0 operation disable */
163 TM0EQMK0 = 1; /* INTTM0EQ0 interrupt disable */
164 TM0EQIF0 = 0; /* clear INTTM0EQ0 interrupt flag */
166 #ifdef __IAR_V850ES_Fx3__
168 TM0CMP0 = (((configCPU_CLOCK_HZ / configTICK_RATE_HZ) / 2)-1); /* divided by 2 because peripherals only run at CPU_CLOCK/2 */
172 TM0CMP0 = (configCPU_CLOCK_HZ / configTICK_RATE_HZ);
178 TM0EQIF0 = 0; /* clear INTTM0EQ0 interrupt flag */
179 TM0EQMK0 = 0; /* INTTM0EQ0 interrupt enable */
180 TM0CE = 1; /* TMM0 operation enable */
182 /*-----------------------------------------------------------*/