2 * FreeRTOS Kernel V10.5.1
3 * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
5 * SPDX-License-Identifier: MIT
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24 * https://www.FreeRTOS.org
25 * https://github.com/FreeRTOS
33 #include <avr/interrupt.h>
39 /*-----------------------------------------------------------
40 * Implementation of functions defined in portable.h for the AVR port.
41 *----------------------------------------------------------*/
43 /* Start tasks with interrupts enabled. */
44 #define portFLAGS_INT_ENABLED ( (StackType_t) 0x80 )
46 #if defined( portUSE_WDTO)
47 #warning "Watchdog Timer used for scheduler."
48 #define portSCHEDULER_ISR WDT_vect
50 #elif defined( portUSE_TIMER0 )
51 /* Hardware constants for Timer0. */
52 #warning "Timer0 used for scheduler."
53 #define portSCHEDULER_ISR TIMER0_COMPA_vect
54 #define portCLEAR_COUNTER_ON_MATCH ( (uint8_t) _BV(WGM01) )
55 #define portPRESCALE_1024 ( (uint8_t) (_BV(CS02)|_BV(CS00)) )
56 #define portCLOCK_PRESCALER ( (uint32_t) 1024 )
57 #define portCOMPARE_MATCH_A_INTERRUPT_ENABLE ( (uint8_t) _BV(OCIE0A) )
58 #define portOCRL OCR0A
59 #define portTCCRa TCCR0A
60 #define portTCCRb TCCR0B
61 #define portTIMSK TIMSK0
62 #define portTIFR TIFR0
65 #error "No Timer defined for scheduler"
68 /*-----------------------------------------------------------*/
70 /* We require the address of the pxCurrentTCB variable, but don't want to know
71 any details of its type. */
73 extern volatile TCB_t * volatile pxCurrentTCB;
75 /*-----------------------------------------------------------*/
78 Enable the watchdog timer, configuring it for expire after
79 (value) timeout (which is a combination of the WDP0
82 This function is derived from <avr/wdt.h> but enables only
83 the interrupt bit (WDIE), rather than the reset bit (WDE).
85 Can't find it documented but the WDT, once enabled,
86 rolls over and fires a new interrupt each time.
88 See also the symbolic constants WDTO_15MS et al.
90 Updated to match avr-libc 2.0.0
93 #if defined( portUSE_WDTO)
96 __attribute__ ((__always_inline__))
97 void wdt_interrupt_enable (const uint8_t value)
99 if (_SFR_IO_REG_P (_WD_CONTROL_REG))
101 __asm__ __volatile__ (
102 "in __tmp_reg__,__SREG__" "\n\t"
106 "out __SREG__,__tmp_reg__" "\n\t"
109 : "I" (_SFR_IO_ADDR(_WD_CONTROL_REG)),
110 "r" ((uint8_t)(_BV(_WD_CHANGE_BIT) | _BV(WDE))),
111 "r" ((uint8_t) ((value & 0x08 ? _WD_PS3_MASK : 0x00) |
112 _BV(WDIF) | _BV(WDIE) | (value & 0x07)) )
118 __asm__ __volatile__ (
119 "in __tmp_reg__,__SREG__" "\n\t"
123 "out __SREG__,__tmp_reg__" "\n\t"
126 : "n" (_SFR_MEM_ADDR(_WD_CONTROL_REG)),
127 "r" ((uint8_t)(_BV(_WD_CHANGE_BIT) | _BV(WDE))),
128 "r" ((uint8_t) ((value & 0x08 ? _WD_PS3_MASK : 0x00) |
129 _BV(WDIF) | _BV(WDIE) | (value & 0x07)) )
136 /*-----------------------------------------------------------*/
138 Enable the watchdog timer, configuring it for expire after
139 (value) timeout (which is a combination of the WDP0
142 This function is derived from <avr/wdt.h> but enables both
143 the reset bit (WDE), and the interrupt bit (WDIE).
145 This will ensure that if the interrupt is not serviced
146 before the second timeout, the AVR will reset.
148 Servicing the interrupt automatically clears it,
149 and ensures the AVR does not reset.
151 Can't find it documented but the WDT, once enabled,
152 rolls over and fires a new interrupt each time.
154 See also the symbolic constants WDTO_15MS et al.
156 Updated to match avr-libc 2.0.0
159 #if defined( portUSE_WDTO)
162 __attribute__ ((__always_inline__))
163 void wdt_interrupt_reset_enable (const uint8_t value)
165 if (_SFR_IO_REG_P (_WD_CONTROL_REG))
167 __asm__ __volatile__ (
168 "in __tmp_reg__,__SREG__" "\n\t"
172 "out __SREG__,__tmp_reg__" "\n\t"
175 : "I" (_SFR_IO_ADDR(_WD_CONTROL_REG)),
176 "r" ((uint8_t)(_BV(_WD_CHANGE_BIT) | _BV(WDE))),
177 "r" ((uint8_t) ((value & 0x08 ? _WD_PS3_MASK : 0x00) |
178 _BV(WDIF) | _BV(WDIE) | _BV(WDE) | (value & 0x07)) )
184 __asm__ __volatile__ (
185 "in __tmp_reg__,__SREG__" "\n\t"
189 "out __SREG__,__tmp_reg__" "\n\t"
192 : "n" (_SFR_MEM_ADDR(_WD_CONTROL_REG)),
193 "r" ((uint8_t)(_BV(_WD_CHANGE_BIT) | _BV(WDE))),
194 "r" ((uint8_t) ((value & 0x08 ? _WD_PS3_MASK : 0x00) |
195 _BV(WDIF) | _BV(WDIE) | _BV(WDE) | (value & 0x07)) )
202 /*-----------------------------------------------------------*/
205 * Macro to save all the general purpose registers, the save the stack pointer
208 * The first thing we do is save the flags then disable interrupts. This is to
209 * guard our stack against having a context switch interrupt after we have already
210 * pushed the registers onto the stack - causing the 32 registers to be on the
213 * r1 is set to zero (__zero_reg__) as the compiler expects it to be thus, however
214 * some of the math routines make use of R1.
216 * r0 is set to __tmp_reg__ as the compiler expects it to be thus.
218 * #if defined(__AVR_HAVE_RAMPZ__)
219 * #define __RAMPZ__ 0x3B
222 * #if defined(__AVR_3_BYTE_PC__)
223 * #define __EIND__ 0x3C
226 * The interrupts will have been disabled during the call to portSAVE_CONTEXT()
227 * so we need not worry about reading/writing to the stack pointer.
229 #if defined(__AVR_3_BYTE_PC__) && defined(__AVR_HAVE_RAMPZ__)
230 /* 3-Byte PC Save with RAMPZ */
231 #define portSAVE_CONTEXT() \
232 __asm__ __volatile__ ( "push __tmp_reg__ \n\t" \
233 "in __tmp_reg__, __SREG__ \n\t" \
235 "push __tmp_reg__ \n\t" \
236 "in __tmp_reg__, 0x3B \n\t" \
237 "push __tmp_reg__ \n\t" \
238 "in __tmp_reg__, 0x3C \n\t" \
239 "push __tmp_reg__ \n\t" \
240 "push __zero_reg__ \n\t" \
241 "clr __zero_reg__ \n\t" \
272 "lds r26, pxCurrentTCB \n\t" \
273 "lds r27, pxCurrentTCB + 1 \n\t" \
274 "in __tmp_reg__, __SP_L__ \n\t" \
275 "st x+, __tmp_reg__ \n\t" \
276 "in __tmp_reg__, __SP_H__ \n\t" \
277 "st x+, __tmp_reg__ \n\t" \
279 #elif defined(__AVR_HAVE_RAMPZ__)
280 /* 2-Byte PC Save with RAMPZ */
281 #define portSAVE_CONTEXT() \
282 __asm__ __volatile__ ( "push __tmp_reg__ \n\t" \
283 "in __tmp_reg__, __SREG__ \n\t" \
285 "push __tmp_reg__ \n\t" \
286 "in __tmp_reg__, 0x3B \n\t" \
287 "push __tmp_reg__ \n\t" \
288 "push __zero_reg__ \n\t" \
289 "clr __zero_reg__ \n\t" \
320 "lds r26, pxCurrentTCB \n\t" \
321 "lds r27, pxCurrentTCB + 1 \n\t" \
322 "in __tmp_reg__, __SP_L__ \n\t" \
323 "st x+, __tmp_reg__ \n\t" \
324 "in __tmp_reg__, __SP_H__ \n\t" \
325 "st x+, __tmp_reg__ \n\t" \
329 #define portSAVE_CONTEXT() \
330 __asm__ __volatile__ ( "push __tmp_reg__ \n\t" \
331 "in __tmp_reg__, __SREG__ \n\t" \
333 "push __tmp_reg__ \n\t" \
334 "push __zero_reg__ \n\t" \
335 "clr __zero_reg__ \n\t" \
366 "lds r26, pxCurrentTCB \n\t" \
367 "lds r27, pxCurrentTCB + 1 \n\t" \
368 "in __tmp_reg__, __SP_L__ \n\t" \
369 "st x+, __tmp_reg__ \n\t" \
370 "in __tmp_reg__, __SP_H__ \n\t" \
371 "st x+, __tmp_reg__ \n\t" \
376 * Opposite to portSAVE_CONTEXT(). Interrupts will have been disabled during
377 * the context save so we can write to the stack pointer.
379 #if defined(__AVR_3_BYTE_PC__) && defined(__AVR_HAVE_RAMPZ__)
380 /* 3-Byte PC Restore with RAMPZ */
381 #define portRESTORE_CONTEXT() \
382 __asm__ __volatile__ ( "lds r26, pxCurrentTCB \n\t" \
383 "lds r27, pxCurrentTCB + 1 \n\t" \
385 "out __SP_L__, r28 \n\t" \
387 "out __SP_H__, r29 \n\t" \
418 "pop __zero_reg__ \n\t" \
419 "pop __tmp_reg__ \n\t" \
420 "out 0x3C, __tmp_reg__ \n\t" \
421 "pop __tmp_reg__ \n\t" \
422 "out 0x3B, __tmp_reg__ \n\t" \
423 "pop __tmp_reg__ \n\t" \
424 "out __SREG__, __tmp_reg__ \n\t" \
425 "pop __tmp_reg__ \n\t" \
427 #elif defined(__AVR_HAVE_RAMPZ__)
428 /* 2-Byte PC Restore with RAMPZ */
429 #define portRESTORE_CONTEXT() \
430 __asm__ __volatile__ ( "lds r26, pxCurrentTCB \n\t" \
431 "lds r27, pxCurrentTCB + 1 \n\t" \
433 "out __SP_L__, r28 \n\t" \
435 "out __SP_H__, r29 \n\t" \
466 "pop __zero_reg__ \n\t" \
467 "pop __tmp_reg__ \n\t" \
468 "out 0x3B, __tmp_reg__ \n\t" \
469 "pop __tmp_reg__ \n\t" \
470 "out __SREG__, __tmp_reg__ \n\t" \
471 "pop __tmp_reg__ \n\t" \
474 /* 2-Byte PC Restore */
475 #define portRESTORE_CONTEXT() \
476 __asm__ __volatile__ ( "lds r26, pxCurrentTCB \n\t" \
477 "lds r27, pxCurrentTCB + 1 \n\t" \
479 "out __SP_L__, r28 \n\t" \
481 "out __SP_H__, r29 \n\t" \
512 "pop __zero_reg__ \n\t" \
513 "pop __tmp_reg__ \n\t" \
514 "out __SREG__, __tmp_reg__ \n\t" \
515 "pop __tmp_reg__ \n\t" \
518 /*-----------------------------------------------------------*/
521 * Perform hardware setup to enable ticks from relevant Timer.
523 static void prvSetupTimerInterrupt( void );
524 /*-----------------------------------------------------------*/
527 * See header file for description.
529 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
532 /* Simulate how the stack would look after a call to vPortYield() generated by
535 /* The start of the task code will be popped off the stack last, so place
537 usAddress = ( uint16_t ) pxCode;
538 *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
542 *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
545 #if defined(__AVR_3_BYTE_PC__)
546 /* The AVR ATmega2560/ATmega2561 have 256KBytes of program memory and a 17-bit
547 * program counter. When a code address is stored on the stack, it takes 3 bytes
548 * instead of 2 for the other ATmega* chips.
550 * Store 0 as the top byte since we force all task routines to the bottom 128K
551 * of flash. We do this by using the .lowtext label in the linker script.
553 * In order to do this properly, we would need to get a full 3-byte pointer to
554 * pxCode. That requires a change to GCC. Not likely to happen any time soon.
560 /* Next simulate the stack as if after a call to portSAVE_CONTEXT().
561 portSAVE_CONTEXT places the flags on the stack immediately after r0
562 to ensure the interrupts get disabled as soon as possible, and so ensuring
563 the stack use is minimal should a context switch interrupt occur. */
564 *pxTopOfStack = ( StackType_t ) 0x00; /* R0 */
566 *pxTopOfStack = portFLAGS_INT_ENABLED;
569 #if defined(__AVR_3_BYTE_PC__)
570 /* If we have an ATmega256x, we are also saving the EIND register.
571 * We should default to 0.
573 *pxTopOfStack = ( StackType_t ) 0x00; /* EIND */
577 #if defined(__AVR_HAVE_RAMPZ__)
578 /* We are saving the RAMPZ register.
579 * We should default to 0.
581 *pxTopOfStack = ( StackType_t ) 0x00; /* RAMPZ */
585 /* Now the remaining registers. The compiler expects R1 to be 0. */
586 *pxTopOfStack = ( StackType_t ) 0x00; /* R1 */
588 /* Leave R2 - R23 untouched */
591 /* Place the parameter on the stack in the expected location. */
592 usAddress = ( uint16_t ) pvParameters;
593 *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
597 *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
599 /* Leave register R26 - R31 untouched */
604 /*-----------------------------------------------------------*/
606 BaseType_t xPortStartScheduler( void )
608 /* Setup the relevant timer hardware to generate the tick. */
609 prvSetupTimerInterrupt();
611 /* Restore the context of the first task that is going to run. */
612 portRESTORE_CONTEXT();
614 /* Simulate a function call end as generated by the compiler. We will now
615 jump to the start of the task the context of which we have just restored. */
616 __asm__ __volatile__ ( "ret" );
618 /* Should not get here. */
621 /*-----------------------------------------------------------*/
623 void vPortEndScheduler( void )
625 /* It is unlikely that the ATmega port will get stopped. */
627 /*-----------------------------------------------------------*/
630 * Manual context switch. The first thing we do is save the registers so we
631 * can use a naked attribute.
633 void vPortYield( void ) __attribute__ ( ( hot, flatten, naked ) );
634 void vPortYield( void )
637 vTaskSwitchContext();
638 portRESTORE_CONTEXT();
640 __asm__ __volatile__ ( "ret" );
642 /*-----------------------------------------------------------*/
645 * Manual context switch callable from ISRs. The first thing we do is save
646 * the registers so we can use a naked attribute.
648 void vPortYieldFromISR(void) __attribute__ ( ( hot, flatten, naked ) );
649 void vPortYieldFromISR(void)
652 vTaskSwitchContext();
653 portRESTORE_CONTEXT();
655 __asm__ __volatile__ ( "reti" );
657 /*-----------------------------------------------------------*/
660 * Context switch function used by the tick. This must be identical to
661 * vPortYield() from the call to vTaskSwitchContext() onwards. The only
662 * difference from vPortYield() is the tick count is incremented as the
663 * call comes from the tick ISR.
665 void vPortYieldFromTick( void ) __attribute__ ( ( hot, flatten, naked ) );
666 void vPortYieldFromTick( void )
669 if( xTaskIncrementTick() != pdFALSE )
671 vTaskSwitchContext();
673 portRESTORE_CONTEXT();
675 __asm__ __volatile__ ( "ret" );
677 /*-----------------------------------------------------------*/
679 #if defined(portUSE_WDTO)
681 * Setup WDT to generate a tick interrupt.
683 void prvSetupTimerInterrupt( void )
688 /* set up WDT Interrupt (rather than the WDT Reset). */
689 wdt_interrupt_enable( portUSE_WDTO );
692 #elif defined (portUSE_TIMER0)
694 * Setup Timer0 compare match A to generate a tick interrupt.
696 static void prvSetupTimerInterrupt( void )
698 uint32_t ulCompareMatch;
701 /* Using 8bit Timer0 to generate the tick. Correct fuses must be
702 selected for the configCPU_CLOCK_HZ clock.*/
704 ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ;
706 /* We only have 8 bits so have to scale 1024 to get our required tick rate. */
707 ulCompareMatch /= portCLOCK_PRESCALER;
709 /* Adjust for correct value. */
710 ulCompareMatch -= ( uint32_t ) 1;
712 /* Setup compare match value for compare match A. Interrupts are disabled
713 before this is called so we need not worry here. */
714 ucLowByte = ( uint8_t ) ( ulCompareMatch & ( uint32_t ) 0xff );
715 portOCRL = ucLowByte;
717 /* Setup clock source and compare match behaviour. */
718 portTCCRa = portCLEAR_COUNTER_ON_MATCH;
719 portTCCRb = portPRESCALE_1024;
722 /* Enable the interrupt - this is okay as interrupt are currently globally disabled. */
723 ucLowByte = portTIMSK;
724 ucLowByte |= portCOMPARE_MATCH_A_INTERRUPT_ENABLE;
725 portTIMSK = ucLowByte;
730 /*-----------------------------------------------------------*/
732 #if configUSE_PREEMPTION == 1
735 * Tick ISR for preemptive scheduler. We can use a naked attribute as
736 * the context is saved at the start of vPortYieldFromTick(). The tick
737 * count is incremented after the context is saved.
739 * use ISR_NOBLOCK where there is an important timer running, that should preempt the scheduler.
742 ISR(portSCHEDULER_ISR, ISR_NAKED) __attribute__ ((hot, flatten));
743 /* ISR(portSCHEDULER_ISR, ISR_NAKED ISR_NOBLOCK) __attribute__ ((hot, flatten));
745 ISR(portSCHEDULER_ISR)
747 vPortYieldFromTick();
748 __asm__ __volatile__ ( "reti" );
753 * Tick ISR for the cooperative scheduler. All this does is increment the
754 * tick count. We don't need to switch context, this can only be done by
755 * manual calls to taskYIELD();
757 * use ISR_NOBLOCK where there is an important timer running, that should preempt the scheduler.
759 ISR(portSCHEDULER_ISR) __attribute__ ((hot, flatten));
760 /* ISR(portSCHEDULER_ISR, ISR_NOBLOCK) __attribute__ ((hot, flatten));
762 ISR(portSCHEDULER_ISR)
764 xTaskIncrementTick();