begriffs open source - cmsis-freertos/blob - Demo/RISC-V_RV32_SiFive_HiFive1-RevB_FreedomStudio/bsp/core.dts

   1 /dts-v1/;
   2 / {
   3         #address-cells = <1>;
   4         #size-cells = <1>;
   5         compatible = "sifive,hifive1-revb";
   6         model = "sifive,hifive1-revb";
   7         cpus {
   8                 #address-cells = <1>;
   9                 #size-cells = <0>;
  10                 compatible = "sifive,fe310-g000";
  11                 L6: cpu@0 {
  12                         clocks = <&hfclk>;
  13                         compatible = "sifive,rocket0", "riscv";
  14                         device_type = "cpu";
  15                         i-cache-block-size = <64>;
  16                         i-cache-sets = <128>;
  17                         i-cache-size = <16384>;
  18                         next-level-cache = <&spi0>;
  19                         reg = <0>;
  20                         riscv,isa = "rv32imac";
  21                         riscv,pmpregions = <8>;
  22                         sifive,itim = <&itim>;
  23                         sifive,dtim = <&dtim>;
  24                         status = "okay";
  25                         timebase-frequency = <16000000>;
  26                         hardware-exec-breakpoint-count = <4>;
  27                         hlic: interrupt-controller {
  28                                 #interrupt-cells = <1>;
  29                                 compatible = "riscv,cpu-intc";
  30                                 interrupt-controller;
  31                         };
  32                 };
  33         };
  34         soc {
  35                 #address-cells = <1>;
  36                 #size-cells = <1>;
  37                 #clock-cells = <1>;
  38                 compatible = "sifive,hifive1";
  39                 ranges;
  40                 hfxoscin: clock@0 {
  41                         #clock-cells = <0>;
  42                         compatible = "fixed-clock";
  43                         clock-frequency = <16000000>;
  44                 };
  45                 hfxoscout: clock@1 {
  46                         compatible = "sifive,fe310-g000,hfxosc";
  47                         clocks = <&hfxoscin>;
  48                         reg = <&prci 0x4>;
  49                         reg-names = "config";
  50                 };
  51                 hfroscin: clock@2 {
  52                         #clock-cells = <0>;
  53                         compatible = "fixed-clock";
  54                         clock-frequency = <72000000>;
  55                 };
  56                 hfroscout: clock@3 {
  57                         compatible = "sifive,fe310-g000,hfrosc";
  58                         clocks = <&hfroscin>;
  59                         reg = <&prci 0x0>;
  60                         reg-names = "config";
  61                 };
  62                 hfclk: clock@4 {
  63                         compatible = "sifive,fe310-g000,pll";
  64                         clocks = <&hfxoscout &hfroscout>;
  65                         clock-names = "pllref", "pllsel0";
  66                         reg = <&prci 0x8 &prci 0xc>;
  67                         reg-names = "config", "divider";
  68                         clock-frequency = <16000000>;
  69                 };
  70                 lfrosc: clock@5 {
  71                         #clock-cells = <0>;
  72                         compatible = "fixed-clock";
  73                         clock-frequency = <32768>;
  74                 };
  75                 psdlfaltclk: clock@6 {
  76                         #clock-cells = <0>;
  77                         compatible = "fixed-clock";
  78                         clock-frequency = <32768>;
  79                 };
  80                 lfclk: clock@7 {
  81                         compatible = "sifive,fe310-g000,lfrosc";
  82                         clocks = <&lfrosc &psdlfaltclk>;
  83                         clock-names = "lfrosc", "psdlfaltclk";
  84                         reg = <&aon 0x70 &aon 0x7C>;
  85                         reg-names = "config", "mux";
  86                 };
  87                 debug-controller@0 {
  88                         compatible = "sifive,debug-011", "riscv,debug-011";
  89                         interrupts-extended = <&hlic 65535>;
  90                         reg = <0x0 0x1000>;
  91                         reg-names = "control";
  92                 };
  93                 /* Missing: Error device */
  94                 maskrom@1000 {
  95                         reg = <0x1000 0x2000>;
  96                         reg-names = "mem";
  97                 };
  98                 otp@20000 {
  99                         reg = <0x20000 0x2000 0x10010000 0x1000>;
 100                         reg-names = "mem", "control";
 101                 };
 102                 clint: clint@2000000 {
 103                         compatible = "riscv,clint0";
 104                         interrupts-extended = <&hlic 3 &hlic 7>;
 105                         reg = <0x2000000 0x10000>;
 106                         reg-names = "control";
 107                 };
 108                 itim: itim@8000000 {
 109                         compatible = "sifive,itim0";
 110                         reg = <0x8000000 0x2000>;
 111                         reg-names = "mem";
 112                 };
 113                 plic: interrupt-controller@c000000 {
 114                         #interrupt-cells = <1>;
 115                         compatible = "riscv,plic0";
 116                         interrupt-controller;
 117                         interrupts-extended = <&hlic 11>;
 118                         reg = <0xc000000 0x4000000>;
 119                         reg-names = "control";
 120                         riscv,max-priority = <7>;
 121                         riscv,ndev = <52>;
 122                 };
 123                 aon: aon@10000000 {
 124                         compatible = "sifive,aon0";
 125                         reg = <0x10000000 0x8000>;
 126                         reg-names = "mem";
 127                         interrupt-parent = <&plic>;
 128                         interrupts = <1 2>;
 129                         clocks = <&lfclk>;
 130                 };
 131                 prci: prci@10008000 {
 132                         compatible = "sifive,fe310-g000,prci";
 133                         reg = <0x10008000 0x8000>;
 134                         reg-names = "mem";
 135                 };
 136                 gpio0: gpio@10012000 {
 137                         compatible = "sifive,gpio0";
 138                         interrupt-parent = <&plic>;
 139                         interrupts = <8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
 140                                       23 24 25 26 27 28 29 30 31 32 33 34 35 36
 141                                       27 28 29>;
 142                         reg = <0x10012000 0x1000>;
 143                         reg-names = "control";
 144                 };
 145                 led@0 {
 146                         compatible = "sifive,gpio-leds";
 147                         label = "LD0red";
 148                         gpios = <&gpio0 22>;
 149                         linux,default-trigger = "none";
 150                 };
 151                 led@1 {
 152                         compatible = "sifive,gpio-leds";
 153                         label = "LD0green";
 154                         gpios = <&gpio0 19>;
 155                         linux,default-trigger = "none";
 156                 };
 157                 led@2 {
 158                         compatible = "sifive,gpio-leds";
 159                         label = "LD0blue";
 160                         gpios = <&gpio0 21>;
 161                         linux,default-trigger = "none";
 162                 };
 163                 uart0: serial@10013000 {
 164                         compatible = "sifive,uart0";
 165                         interrupt-parent = <&plic>;
 166                         interrupts = <3>;
 167                         reg = <0x10013000 0x1000>;
 168                         reg-names = "control";
 169                         clocks = <&hfclk>;
 170                         pinmux = <&gpio0 0x0 0x30000>;
 171                 };
 172                 spi0: spi@10014000 {
 173                         compatible = "sifive,spi0";
 174                         interrupt-parent = <&plic>;
 175                         interrupts = <5>;
 176                         reg = <0x10014000 0x1000 0x20000000 0x7A120>;
 177                         reg-names = "control", "mem";
 178                         clocks = <&hfclk>;
 179                         pinmux = <&gpio0 0x0 0x0>;
 180                         #address-cells = <1>;
 181                         #size-cells = <1>;
 182                         flash@0 {
 183                                 compatible = "jedec,spi-nor";
 184                                 reg = <0x20000000 0x424000>;
 185                         };
 186                 };
 187                 pwm0: pwm@10015000 {
 188                         compatible = "sifive,pwm0";
 189                         sifive,comparator-widthbits = <8>;
 190                         sifive,ncomparators = <4>;
 191                         interrupt-parent = <&plic>;
 192                         interrupts = <40 41 42 43>;
 193                         reg = <0x10015000 0x1000>;
 194                         reg-names = "control";
 195                         clocks = <&hfclk>;
 196                         pinmux = <&gpio0 0x0F 0x0F>;
 197                 };
 198                 i2c0: i2c@10016000 {
 199                         compatible = "sifive,i2c0";
 200                         interrupt-parent = <&plic>;
 201                         interrupts = <52>;
 202                         reg = <0x10016000 0x1000>;
 203                         reg-names = "control";
 204                         clocks = <&hfclk>;
 205                         pinmux = <&gpio0 0x0 0x3000>;
 206                 };
 207                 uart1: serial@10023000 {
 208                         compatible = "sifive,uart0";
 209                         interrupt-parent = <&plic>;
 210                         interrupts = <4>;
 211                         reg = <0x10023000 0x1000>;
 212                         reg-names = "control";
 213                         clocks = <&hfclk>;
 214                         pinmux = <&gpio0 0x0 0x840000>;
 215                 };
 216                 spi1: spi@10024000 {
 217                         compatible = "sifive,spi0";
 218                         interrupt-parent = <&plic>;
 219                         interrupts = <6>;
 220                         reg = <0x10024000 0x1000>;
 221                         reg-names = "control";
 222                         clocks = <&hfclk>;
 223                         pinmux = <&gpio0 0x0 0x0003C>;
 224                 };
 225                 pwm1: pwm@10025000 {
 226                         compatible = "sifive,pwm0";
 227                         sifive,comparator-widthbits = <16>;
 228                         sifive,ncomparators = <4>;
 229                         interrupt-parent = <&plic>;
 230                         interrupts = <44 45 46 47>;
 231                         reg = <0x10025000 0x1000>;
 232                         reg-names = "control";
 233                         clocks = <&hfclk>;
 234                         pinmux = <&gpio0 0x780000 0x780000>;
 235                 };
 236                 spi2: spi@10034000 {
 237                         compatible = "sifive,spi0";
 238                         interrupt-parent = <&plic>;
 239                         interrupts = <7>;
 240                         reg = <0x10034000 0x1000>;
 241                         reg-names = "control";
 242                         clocks = <&hfclk>;
 243                         pinmux = <&gpio0 0x0 0xFC000000>;
 244                 };
 245                 pwm2: pwm@10035000 {
 246                         compatible = "sifive,pwm0";
 247                         sifive,comparator-widthbits = <16>;
 248                         sifive,ncomparators = <4>;
 249                         interrupt-parent = <&plic>;
 250                         interrupts = <48 49 50 51>;
 251                         reg = <0x10035000 0x1000>;
 252                         reg-names = "control";
 253                         clocks = <&hfclk>;
 254                         pinmux = <&gpio0 0x3C00 0x3C00>;
 255                 };
 256                 dtim: dtim@80000000 {
 257                         compatible = "sifive,dtim0";
 258                         reg = <0x80000000 0x4000>;
 259                         reg-names = "mem";
 260                 };
 261         };
 262 };