begriffs open source - cmsis-freertos/blob - Source/portable/GCC/ARM7_LPC23xx/portmacro.h

   1 /*
   2  * FreeRTOS Kernel V10.4.4
   3  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
   4  *
   5  * SPDX-License-Identifier: MIT
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy of
   8  * this software and associated documentation files (the "Software"), to deal in
   9  * the Software without restriction, including without limitation the rights to
  10  * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
  11  * the Software, and to permit persons to whom the Software is furnished to do so,
  12  * subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in all
  15  * copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
  19  * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
  20  * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
  21  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  22  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * https://www.FreeRTOS.org
  25  * https://github.com/FreeRTOS
  26  *
  27  */
  28
  29 /*
  30         Changes from V3.2.3
  31
  32         + Modified portENTER_SWITCHING_ISR() to allow use with GCC V4.0.1.
  33
  34         Changes from V3.2.4
  35
  36         + Removed the use of the %0 parameter within the assembler macros and
  37           replaced them with hard coded registers.  This will ensure the
  38           assembler does not select the link register as the temp register as
  39           was occasionally happening previously.
  40
  41         + The assembler statements are now included in a single asm block rather
  42           than each line having its own asm block.
  43
  44         Changes from V4.5.0
  45
  46         + Removed the portENTER_SWITCHING_ISR() and portEXIT_SWITCHING_ISR() macros
  47           and replaced them with portYIELD_FROM_ISR() macro.  Application code
  48           should now make use of the portSAVE_CONTEXT() and portRESTORE_CONTEXT()
  49           macros as per the V4.5.1 demo code.
  50 */
  51
  52 #ifndef PORTMACRO_H
  53 #define PORTMACRO_H
  54
  55 #ifdef __cplusplus
  56 extern "C" {
  57 #endif
  58
  59 /*-----------------------------------------------------------
  60  * Port specific definitions.
  61  *
  62  * The settings in this file configure FreeRTOS correctly for the
  63  * given hardware and compiler.
  64  *
  65  * These settings should not be altered.
  66  *-----------------------------------------------------------
  67  */
  68
  69 /* Type definitions. */
  70 #define portCHAR                char
  71 #define portFLOAT               float
  72 #define portDOUBLE              double
  73 #define portLONG                long
  74 #define portSHORT               short
  75 #define portSTACK_TYPE  uint32_t
  76 #define portBASE_TYPE   portLONG
  77
  78 typedef portSTACK_TYPE StackType_t;
  79 typedef long BaseType_t;
  80 typedef unsigned long UBaseType_t;
  81
  82 #if( configUSE_16_BIT_TICKS == 1 )
  83         typedef uint16_t TickType_t;
  84         #define portMAX_DELAY ( TickType_t ) 0xffff
  85 #else
  86         typedef uint32_t TickType_t;
  87         #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
  88 #endif
  89 /*-----------------------------------------------------------*/
  90
  91 /* Architecture specifics. */
  92 #define portSTACK_GROWTH                        ( -1 )
  93 #define portTICK_PERIOD_MS                      ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
  94 #define portBYTE_ALIGNMENT                      8
  95 #define portNOP()                                       __asm volatile ( "NOP" );
  96 /*-----------------------------------------------------------*/
  97
  98
  99 /* Scheduler utilities. */
 100
 101 /*
 102  * portRESTORE_CONTEXT, portRESTORE_CONTEXT, portENTER_SWITCHING_ISR
 103  * and portEXIT_SWITCHING_ISR can only be called from ARM mode, but
 104  * are included here for efficiency.  An attempt to call one from
 105  * THUMB mode code will result in a compile time error.
 106  */
 107
 108 #define portRESTORE_CONTEXT()                                                                                   \
 109 {                                                                                                                                               \
 110 extern volatile void * volatile pxCurrentTCB;                                                   \
 111 extern volatile uint32_t ulCriticalNesting;                                     \
 112                                                                                                                                                 \
 113         /* Set the LR to the task stack. */                                                                     \
 114         __asm volatile (                                                                                                        \
 115         "LDR            R0, =pxCurrentTCB                                                               \n\t"   \
 116         "LDR            R0, [R0]                                                                                \n\t"   \
 117         "LDR            LR, [R0]                                                                                \n\t"   \
 118                                                                                                                                                 \
 119         /* The critical nesting depth is the first item on the stack. */        \
 120         /* Load it into the ulCriticalNesting variable. */                                      \
 121         "LDR            R0, =ulCriticalNesting                                                  \n\t"   \
 122         "LDMFD  LR!, {R1}                                                                                       \n\t"   \
 123         "STR            R1, [R0]                                                                                \n\t"   \
 124                                                                                                                                                 \
 125         /* Get the SPSR from the stack. */                                                                      \
 126         "LDMFD  LR!, {R0}                                                                                       \n\t"   \
 127         "MSR            SPSR, R0                                                                                \n\t"   \
 128                                                                                                                                                 \
 129         /* Restore all system mode registers for the task. */                           \
 130         "LDMFD  LR, {R0-R14}^                                                                           \n\t"   \
 131         "NOP                                                                                                            \n\t"   \
 132                                                                                                                                                 \
 133         /* Restore the return address. */                                                                       \
 134         "LDR            LR, [LR, #+60]                                                                  \n\t"   \
 135                                                                                                                                                 \
 136         /* And return - correcting the offset in the LR to obtain the */        \
 137         /* correct address. */                                                                                          \
 138         "SUBS   PC, LR, #4                                                                                      \n\t"   \
 139         );                                                                                                                                      \
 140         ( void ) ulCriticalNesting;                                                                                     \
 141         ( void ) pxCurrentTCB;                                                                                          \
 142 }
 143 /*-----------------------------------------------------------*/
 144
 145 #define portSAVE_CONTEXT()                                                                                              \
 146 {                                                                                                                                               \
 147 extern volatile void * volatile pxCurrentTCB;                                                   \
 148 extern volatile uint32_t ulCriticalNesting;                                     \
 149                                                                                                                                                 \
 150         /* Push R0 as we are going to use the register. */                                      \
 151         __asm volatile (                                                                                                        \
 152         "STMDB  SP!, {R0}                                                                                       \n\t"   \
 153                                                                                                                                                 \
 154         /* Set R0 to point to the task stack pointer. */                                        \
 155         "STMDB  SP,{SP}^                                                                                        \n\t"   \
 156         "NOP                                                                                                            \n\t"   \
 157         "SUB    SP, SP, #4                                                                                      \n\t"   \
 158         "LDMIA  SP!,{R0}                                                                                        \n\t"   \
 159                                                                                                                                                 \
 160         /* Push the return address onto the stack. */                                           \
 161         "STMDB  R0!, {LR}                                                                                       \n\t"   \
 162                                                                                                                                                 \
 163         /* Now we have saved LR we can use it instead of R0. */                         \
 164         "MOV    LR, R0                                                                                          \n\t"   \
 165                                                                                                                                                 \
 166         /* Pop R0 so we can save it onto the system mode stack. */                      \
 167         "LDMIA  SP!, {R0}                                                                                       \n\t"   \
 168                                                                                                                                                 \
 169         /* Push all the system mode registers onto the task stack. */           \
 170         "STMDB  LR,{R0-LR}^                                                                                     \n\t"   \
 171         "NOP                                                                                                            \n\t"   \
 172         "SUB    LR, LR, #60                                                                                     \n\t"   \
 173                                                                                                                                                 \
 174         /* Push the SPSR onto the task stack. */                                                        \
 175         "MRS    R0, SPSR                                                                                        \n\t"   \
 176         "STMDB  LR!, {R0}                                                                                       \n\t"   \
 177                                                                                                                                                 \
 178         "LDR    R0, =ulCriticalNesting                                                          \n\t"   \
 179         "LDR    R0, [R0]                                                                                        \n\t"   \
 180         "STMDB  LR!, {R0}                                                                                       \n\t"   \
 181                                                                                                                                                 \
 182         /* Store the new top of stack for the task. */                                          \
 183         "LDR    R0, =pxCurrentTCB                                                                       \n\t"   \
 184         "LDR    R0, [R0]                                                                                        \n\t"   \
 185         "STR    LR, [R0]                                                                                        \n\t"   \
 186         );                                                                                                                                      \
 187         ( void ) ulCriticalNesting;                                                                                     \
 188         ( void ) pxCurrentTCB;                                                                                          \
 189 }
 190
 191
 192 #define portYIELD_FROM_ISR()            vTaskSwitchContext()
 193 #define portYIELD()                                     __asm volatile ( "SWI 0" )
 194 /*-----------------------------------------------------------*/
 195
 196
 197 /* Critical section management. */
 198
 199 /*
 200  * The interrupt management utilities can only be called from ARM mode.  When
 201  * THUMB_INTERWORK is defined the utilities are defined as functions in
 202  * portISR.c to ensure a switch to ARM mode.  When THUMB_INTERWORK is not
 203  * defined then the utilities are defined as macros here - as per other ports.
 204  */
 205
 206 #ifdef THUMB_INTERWORK
 207
 208         extern void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
 209         extern void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
 210
 211         #define portDISABLE_INTERRUPTS()        vPortDisableInterruptsFromThumb()
 212         #define portENABLE_INTERRUPTS()         vPortEnableInterruptsFromThumb()
 213
 214 #else
 215
 216         #define portDISABLE_INTERRUPTS()                                                                                        \
 217                 __asm volatile (                                                                                                                        \
 218                         "STMDB  SP!, {R0}               \n\t"   /* Push R0.                                             */      \
 219                         "MRS    R0, CPSR                \n\t"   /* Get CPSR.                                    */      \
 220                         "ORR    R0, R0, #0xC0   \n\t"   /* Disable IRQ, FIQ.                    */      \
 221                         "MSR    CPSR, R0                \n\t"   /* Write back modified value.   */      \
 222                         "LDMIA  SP!, {R0}                       " )     /* Pop R0.                                              */
 223
 224         #define portENABLE_INTERRUPTS()                                                                                         \
 225                 __asm volatile (                                                                                                                        \
 226                         "STMDB  SP!, {R0}               \n\t"   /* Push R0.                                             */      \
 227                         "MRS    R0, CPSR                \n\t"   /* Get CPSR.                                    */      \
 228                         "BIC    R0, R0, #0xC0   \n\t"   /* Enable IRQ, FIQ.                             */      \
 229                         "MSR    CPSR, R0                \n\t"   /* Write back modified value.   */      \
 230                         "LDMIA  SP!, {R0}                       " )     /* Pop R0.                                              */
 231
 232 #endif /* THUMB_INTERWORK */
 233
 234 extern void vPortEnterCritical( void );
 235 extern void vPortExitCritical( void );
 236
 237 #define portENTER_CRITICAL()            vPortEnterCritical();
 238 #define portEXIT_CRITICAL()                     vPortExitCritical();
 239 /*-----------------------------------------------------------*/
 240
 241 /* Task function macros as described on the FreeRTOS.org WEB site. */
 242 #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
 243 #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
 244
 245 #ifdef __cplusplus
 246 }
 247 #endif
 248
 249 #endif /* PORTMACRO_H */
 250