begriffs open source - cmsis-freertos/blob - Source/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.s

   1 /*
   2  * FreeRTOS Kernel V10.4.4
   3  * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
   4  *
   5  * SPDX-License-Identifier: MIT
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy of
   8  * this software and associated documentation files (the "Software"), to deal in
   9  * the Software without restriction, including without limitation the rights to
  10  * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
  11  * the Software, and to permit persons to whom the Software is furnished to do so,
  12  * subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in all
  15  * copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
  19  * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
  20  * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
  21  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  22  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * https://www.FreeRTOS.org
  25  * https://github.com/FreeRTOS
  26  *
  27  */
  28 /* Including FreeRTOSConfig.h here will cause build errors if the header file
  29 contains code not understood by the assembler - for example the 'extern' keyword.
  30 To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so
  31 the code is included in C files but excluded by the preprocessor in assembly
  32 files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */
  33 #include "FreeRTOSConfig.h"
  34
  35         EXTERN pxCurrentTCB
  36         EXTERN vTaskSwitchContext
  37         EXTERN vPortSVCHandler_C
  38
  39         PUBLIC xIsPrivileged
  40         PUBLIC vResetPrivilege
  41         PUBLIC vRestoreContextOfFirstTask
  42         PUBLIC vRaisePrivilege
  43         PUBLIC vStartFirstTask
  44         PUBLIC ulSetInterruptMask
  45         PUBLIC vClearInterruptMask
  46         PUBLIC PendSV_Handler
  47         PUBLIC SVC_Handler
  48 /*-----------------------------------------------------------*/
  49
  50 /*---------------- Unprivileged Functions -------------------*/
  51
  52 /*-----------------------------------------------------------*/
  53
  54         SECTION .text:CODE:NOROOT(2)
  55         THUMB
  56 /*-----------------------------------------------------------*/
  57
  58 xIsPrivileged:
  59         mrs r0, control                                                 /* r0 = CONTROL. */
  60         tst r0, #1                                                              /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
  61         ite ne
  62         movne r0, #0                                                    /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
  63         moveq r0, #1                                                    /* CONTROL[0]==0. Return true to indicate that the processor is not privileged. */
  64         bx lr                                                                   /* Return. */
  65 /*-----------------------------------------------------------*/
  66
  67 vResetPrivilege:
  68         mrs r0, control                                                 /* r0 = CONTROL. */
  69         orr r0, r0, #1                                                  /* r0 = r0 | 1. */
  70         msr control, r0                                                 /* CONTROL = r0. */
  71         bx lr                                                                   /* Return to the caller. */
  72 /*-----------------------------------------------------------*/
  73
  74 /*----------------- Privileged Functions --------------------*/
  75
  76 /*-----------------------------------------------------------*/
  77
  78         SECTION privileged_functions:CODE:NOROOT(2)
  79         THUMB
  80 /*-----------------------------------------------------------*/
  81
  82 vRestoreContextOfFirstTask:
  83         ldr  r2, =pxCurrentTCB                                  /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
  84         ldr  r1, [r2]                                                   /* Read pxCurrentTCB. */
  85         ldr  r0, [r1]                                                   /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
  86
  87 #if ( configENABLE_MPU == 1 )
  88         dmb                                                                             /* Complete outstanding transfers before disabling MPU. */
  89         ldr r2, =0xe000ed94                                             /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
  90         ldr r4, [r2]                                                    /* Read the value of MPU_CTRL. */
  91         bic r4, r4, #1                                                  /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
  92         str r4, [r2]                                                    /* Disable MPU. */
  93
  94         adds r1, #4                                                             /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
  95         ldr r3, [r1]                                                    /* r3 = *r1 i.e. r3 = MAIR0. */
  96         ldr r2, =0xe000edc0                                             /* r2 = 0xe000edc0 [Location of MAIR0]. */
  97         str r3, [r2]                                                    /* Program MAIR0. */
  98         ldr r2, =0xe000ed98                                             /* r2 = 0xe000ed98 [Location of RNR]. */
  99         movs r3, #4                                                             /* r3 = 4. */
 100         str r3, [r2]                                                    /* Program RNR = 4. */
 101         adds r1, #4                                                             /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
 102         ldr r2, =0xe000ed9c                                             /* r2 = 0xe000ed9c [Location of RBAR]. */
 103         ldmia r1!, {r4-r11}                                             /* Read 4 sets of RBAR/RLAR registers from TCB. */
 104         stmia r2!, {r4-r11}                                             /* Write 4 set of RBAR/RLAR registers using alias registers. */
 105
 106         ldr r2, =0xe000ed94                                             /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
 107         ldr r4, [r2]                                                    /* Read the value of MPU_CTRL. */
 108         orr r4, r4, #1                                                  /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
 109         str r4, [r2]                                                    /* Enable MPU. */
 110         dsb                                                                             /* Force memory writes before continuing. */
 111 #endif /* configENABLE_MPU */
 112
 113 #if ( configENABLE_MPU == 1 )
 114         ldm  r0!, {r1-r3}                                               /* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */
 115         msr  psplim, r1                                                 /* Set this task's PSPLIM value. */
 116         msr  control, r2                                                /* Set this task's CONTROL value. */
 117         adds r0, #32                                                    /* Discard everything up to r0. */
 118         msr  psp, r0                                                    /* This is now the new top of stack to use in the task. */
 119         isb
 120         mov  r0, #0
 121         msr  basepri, r0                                                /* Ensure that interrupts are enabled when the first task starts. */
 122         bx   r3                                                                 /* Finally, branch to EXC_RETURN. */
 123 #else /* configENABLE_MPU */
 124         ldm  r0!, {r1-r2}                                               /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
 125         msr  psplim, r1                                                 /* Set this task's PSPLIM value. */
 126         movs r1, #2                                                             /* r1 = 2. */
 127         msr  CONTROL, r1                                                /* Switch to use PSP in the thread mode. */
 128         adds r0, #32                                                    /* Discard everything up to r0. */
 129         msr  psp, r0                                                    /* This is now the new top of stack to use in the task. */
 130         isb
 131         mov  r0, #0
 132         msr  basepri, r0                                                /* Ensure that interrupts are enabled when the first task starts. */
 133         bx   r2                                                                 /* Finally, branch to EXC_RETURN. */
 134 #endif /* configENABLE_MPU */
 135 /*-----------------------------------------------------------*/
 136
 137 vRaisePrivilege:
 138         mrs  r0, control                                                /* Read the CONTROL register. */
 139         bic r0, r0, #1                                                  /* Clear the bit 0. */
 140         msr  control, r0                                                /* Write back the new CONTROL value. */
 141         bx lr                                                                   /* Return to the caller. */
 142 /*-----------------------------------------------------------*/
 143
 144 vStartFirstTask:
 145         ldr r0, =0xe000ed08                                             /* Use the NVIC offset register to locate the stack. */
 146         ldr r0, [r0]                                                    /* Read the VTOR register which gives the address of vector table. */
 147         ldr r0, [r0]                                                    /* The first entry in vector table is stack pointer. */
 148         msr msp, r0                                                             /* Set the MSP back to the start of the stack. */
 149         cpsie i                                                                 /* Globally enable interrupts. */
 150         cpsie f
 151         dsb
 152         isb
 153         svc 2                                                                   /* System call to start the first task. portSVC_START_SCHEDULER = 2. */
 154 /*-----------------------------------------------------------*/
 155
 156 ulSetInterruptMask:
 157         mrs r0, basepri                                                 /* r0 = basepri. Return original basepri value. */
 158         mov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY
 159         msr basepri, r1                                                 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
 160         dsb
 161         isb
 162         bx lr                                                                   /* Return. */
 163 /*-----------------------------------------------------------*/
 164
 165 vClearInterruptMask:
 166         msr basepri, r0                                                 /* basepri = ulMask. */
 167         dsb
 168         isb
 169         bx lr                                                                   /* Return. */
 170 /*-----------------------------------------------------------*/
 171
 172 PendSV_Handler:
 173         mrs r0, psp                                                             /* Read PSP in r0. */
 174 #if ( configENABLE_FPU == 1 )
 175         tst lr, #0x10                                                   /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
 176         it eq
 177         vstmdbeq r0!, {s16-s31}                                 /* Store the FPU registers which are not saved automatically. */
 178 #endif /* configENABLE_FPU */
 179 #if ( configENABLE_MPU == 1 )
 180         mrs r1, psplim                                                  /* r1 = PSPLIM. */
 181         mrs r2, control                                                 /* r2 = CONTROL. */
 182         mov r3, lr                                                              /* r3 = LR/EXC_RETURN. */
 183         stmdb r0!, {r1-r11}                                             /* Store on the stack - PSPLIM, CONTROL, LR and registers that are not automatically saved. */
 184 #else /* configENABLE_MPU */
 185         mrs r2, psplim                                                  /* r2 = PSPLIM. */
 186         mov r3, lr                                                              /* r3 = LR/EXC_RETURN. */
 187         stmdb r0!, {r2-r11}                                             /* Store on the stack - PSPLIM, LR and registers that are not automatically. */
 188 #endif /* configENABLE_MPU */
 189
 190         ldr r2, =pxCurrentTCB                                   /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
 191         ldr r1, [r2]                                                    /* Read pxCurrentTCB. */
 192         str r0, [r1]                                                    /* Save the new top of stack in TCB. */
 193
 194         mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
 195         msr basepri, r0                                                 /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
 196         dsb
 197         isb
 198         bl vTaskSwitchContext
 199         mov r0, #0                                                              /* r0 = 0. */
 200         msr basepri, r0                                                 /* Enable interrupts. */
 201
 202         ldr r2, =pxCurrentTCB                                   /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
 203         ldr r1, [r2]                                                    /* Read pxCurrentTCB. */
 204         ldr r0, [r1]                                                    /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
 205
 206 #if ( configENABLE_MPU == 1 )
 207         dmb                                                                             /* Complete outstanding transfers before disabling MPU. */
 208         ldr r2, =0xe000ed94                                             /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
 209         ldr r4, [r2]                                                    /* Read the value of MPU_CTRL. */
 210         bic r4, r4, #1                                                  /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
 211         str r4, [r2]                                                    /* Disable MPU. */
 212
 213         adds r1, #4                                                             /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
 214         ldr r3, [r1]                                                    /* r3 = *r1 i.e. r3 = MAIR0. */
 215         ldr r2, =0xe000edc0                                             /* r2 = 0xe000edc0 [Location of MAIR0]. */
 216         str r3, [r2]                                                    /* Program MAIR0. */
 217         ldr r2, =0xe000ed98                                             /* r2 = 0xe000ed98 [Location of RNR]. */
 218         movs r3, #4                                                             /* r3 = 4. */
 219         str r3, [r2]                                                    /* Program RNR = 4. */
 220         adds r1, #4                                                             /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
 221         ldr r2, =0xe000ed9c                                             /* r2 = 0xe000ed9c [Location of RBAR]. */
 222         ldmia r1!, {r4-r11}                                             /* Read 4 sets of RBAR/RLAR registers from TCB. */
 223         stmia r2!, {r4-r11}                                             /* Write 4 set of RBAR/RLAR registers using alias registers. */
 224
 225         ldr r2, =0xe000ed94                                             /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
 226         ldr r4, [r2]                                                    /* Read the value of MPU_CTRL. */
 227         orr r4, r4, #1                                                  /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
 228         str r4, [r2]                                                    /* Enable MPU. */
 229         dsb                                                                             /* Force memory writes before continuing. */
 230 #endif /* configENABLE_MPU */
 231
 232 #if ( configENABLE_MPU == 1 )
 233         ldmia r0!, {r1-r11}                                             /* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r11 restored. */
 234 #else /* configENABLE_MPU */
 235         ldmia r0!, {r2-r11}                                             /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */
 236 #endif /* configENABLE_MPU */
 237
 238 #if ( configENABLE_FPU == 1 )
 239         tst r3, #0x10                                                   /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
 240         it eq
 241         vldmiaeq r0!, {s16-s31}                                 /* Restore the FPU registers which are not restored automatically. */
 242 #endif /* configENABLE_FPU */
 243
 244  #if ( configENABLE_MPU == 1 )
 245         msr psplim, r1                                                  /* Restore the PSPLIM register value for the task. */
 246         msr control, r2                                                 /* Restore the CONTROL register value for the task. */
 247 #else /* configENABLE_MPU */
 248         msr psplim, r2                                                  /* Restore the PSPLIM register value for the task. */
 249 #endif /* configENABLE_MPU */
 250         msr psp, r0                                                             /* Remember the new top of stack for the task. */
 251         bx r3
 252 /*-----------------------------------------------------------*/
 253
 254 SVC_Handler:
 255         tst lr, #4
 256         ite eq
 257         mrseq r0, msp
 258         mrsne r0, psp
 259         b vPortSVCHandler_C
 260 /*-----------------------------------------------------------*/
 261
 262         END