1 /*******************************************************************/
3 /* This file is automatically generated by linker script generator.*/
7 /* Copyright (c) 2010 Xilinx, Inc. All rights reserved. */
9 /* Description : Cortex-A9 Linker Script */
11 /*******************************************************************/
13 _STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x2000;
14 _HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x2000;
16 _ABORT_STACK_SIZE = DEFINED(_ABORT_STACK_SIZE) ? _ABORT_STACK_SIZE : 1024;
17 _SUPERVISOR_STACK_SIZE = DEFINED(_SUPERVISOR_STACK_SIZE) ? _SUPERVISOR_STACK_SIZE : 2048;
18 _IRQ_STACK_SIZE = DEFINED(_IRQ_STACK_SIZE) ? _IRQ_STACK_SIZE : 1024;
19 _FIQ_STACK_SIZE = DEFINED(_FIQ_STACK_SIZE) ? _FIQ_STACK_SIZE : 1024;
20 _UNDEF_STACK_SIZE = DEFINED(_UNDEF_STACK_SIZE) ? _UNDEF_STACK_SIZE : 1024;
22 /* Define Memories in the system */
26 ps7_ddr_0_S_AXI_BASEADDR : ORIGIN = 0x100000, LENGTH = 0x3FF00000
27 ps7_qspi_linear_0_S_AXI_BASEADDR : ORIGIN = 0xFC000000, LENGTH = 0x1000000
28 ps7_ram_0_S_AXI_BASEADDR : ORIGIN = 0x0, LENGTH = 0x30000
29 ps7_ram_1_S_AXI_BASEADDR : ORIGIN = 0xFFFF0000, LENGTH = 0xFE00
32 /* Specify the default entry point to the program */
36 /* Define the sections, and where they are mapped in memory */
54 *(.gnu.linkonce.armextab.*)
55 } > ps7_ddr_0_S_AXI_BASEADDR
59 } > ps7_ddr_0_S_AXI_BASEADDR
63 } > ps7_ddr_0_S_AXI_BASEADDR
71 } > ps7_ddr_0_S_AXI_BASEADDR
78 } > ps7_ddr_0_S_AXI_BASEADDR
86 } > ps7_ddr_0_S_AXI_BASEADDR
92 *(.gnu.linkonce.sb2.*)
94 } > ps7_ddr_0_S_AXI_BASEADDR
105 } > ps7_ddr_0_S_AXI_BASEADDR
112 } > ps7_ddr_0_S_AXI_BASEADDR
116 } > ps7_ddr_0_S_AXI_BASEADDR
120 ___CTORS_LIST___ = .;
121 KEEP (*crtbegin.o(.ctors))
122 KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors))
123 KEEP (*(SORT(.ctors.*)))
127 } > ps7_ddr_0_S_AXI_BASEADDR
131 ___DTORS_LIST___ = .;
132 KEEP (*crtbegin.o(.dtors))
133 KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors))
134 KEEP (*(SORT(.dtors.*)))
138 } > ps7_ddr_0_S_AXI_BASEADDR
144 } > ps7_ddr_0_S_AXI_BASEADDR
148 } > ps7_ddr_0_S_AXI_BASEADDR
151 __eh_framehdr_start = .;
153 __eh_framehdr_end = .;
154 } > ps7_ddr_0_S_AXI_BASEADDR
156 .gcc_except_table : {
158 } > ps7_ddr_0_S_AXI_BASEADDR
160 .mmu_tbl (ALIGN(16384)) : {
164 } > ps7_ddr_0_S_AXI_BASEADDR
169 *(.gnu.linkonce.armexidix.*.*)
171 } > ps7_ddr_0_S_AXI_BASEADDR
174 __preinit_array_start = .;
175 KEEP (*(SORT(.preinit_array.*)))
176 KEEP (*(.preinit_array))
177 __preinit_array_end = .;
178 } > ps7_ddr_0_S_AXI_BASEADDR
181 __init_array_start = .;
182 KEEP (*(SORT(.init_array.*)))
183 KEEP (*(.init_array))
184 __init_array_end = .;
185 } > ps7_ddr_0_S_AXI_BASEADDR
188 __fini_array_start = .;
189 KEEP (*(SORT(.fini_array.*)))
190 KEEP (*(.fini_array))
191 __fini_array_end = .;
192 } > ps7_ddr_0_S_AXI_BASEADDR
195 __ARM.attributes_start = .;
197 __ARM.attributes_end = .;
198 } > ps7_ddr_0_S_AXI_BASEADDR
206 } > ps7_ddr_0_S_AXI_BASEADDR
212 *(.gnu.linkonce.sb.*)
214 } > ps7_ddr_0_S_AXI_BASEADDR
220 *(.gnu.linkonce.td.*)
222 } > ps7_ddr_0_S_AXI_BASEADDR
228 *(.gnu.linkonce.tb.*)
230 } > ps7_ddr_0_S_AXI_BASEADDR
239 } > ps7_ddr_0_S_AXI_BASEADDR
241 _SDA_BASE_ = __sdata_start + ((__sbss_end - __sdata_start) / 2 );
243 _SDA2_BASE_ = __sdata2_start + ((__sbss2_end - __sdata2_start) / 2 );
245 /* Generate Stack and Heap definitions */
255 } > ps7_ddr_0_S_AXI_BASEADDR
266 . += _IRQ_STACK_SIZE;
269 _supervisor_stack_end = .;
270 . += _SUPERVISOR_STACK_SIZE;
272 __supervisor_stack = .;
273 _abort_stack_end = .;
274 . += _ABORT_STACK_SIZE;
278 . += _FIQ_STACK_SIZE;
281 _undef_stack_end = .;
282 . += _UNDEF_STACK_SIZE;
285 } > ps7_ddr_0_S_AXI_BASEADDR