begriffs open source - cmsis-freertos/blob - Demo/CORTEX_AT91SAM3U256_IAR/system/board_memories.c

   1 /* ----------------------------------------------------------------------------
   2  *         ATMEL Microcontroller Software Support
   3  * ----------------------------------------------------------------------------
   4  * Copyright (c) 2009, Atmel Corporation
   5  *
   6  * All rights reserved.
   7  *
   8  * Redistribution and use in source and binary forms, with or without
   9  * modification, are permitted provided that the following conditions are met:
  10  *
  11  * - Redistributions of source code must retain the above copyright notice,
  12  * this list of conditions and the disclaimer below.
  13  *
  14  * Atmel's name may not be used to endorse or promote products derived from
  15  * this software without specific prior written permission.
  16  *
  17  * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
  18  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
  20  * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
  21  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
  23  * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  24  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  25  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
  26  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  * ----------------------------------------------------------------------------
  28  */
  29
  30 /*
  31     Title: Memories implementation
  32 */
  33
  34 //------------------------------------------------------------------------------
  35 //         Headers
  36 //------------------------------------------------------------------------------
  37
  38 #include <board.h>
  39
  40 //------------------------------------------------------------------------------
  41 //         Exported functions
  42 //------------------------------------------------------------------------------
  43 //------------------------------------------------------------------------------
  44 /// Dummy function to initialize and configure the SDRAM
  45 //------------------------------------------------------------------------------
  46 void BOARD_ConfigureSdram(unsigned char busWidth)
  47 {
  48 }
  49
  50 //------------------------------------------------------------------------------
  51 /// Configures the EBI for NandFlash access. Pins must be configured after or
  52 /// before calling this function.
  53 //------------------------------------------------------------------------------
  54 void BOARD_ConfigureNandFlash(unsigned char busWidth)
  55 {
  56     AT91PS_HSMC4 pHSMC4 = AT91C_BASE_HSMC4;
  57     AT91PS_HSMC4_CS pSMC = AT91C_BASE_HSMC4_CS1;
  58
  59     // Open EBI clock
  60     AT91C_BASE_PMC->PMC_PCER = (1<< AT91C_ID_HSMC4);
  61
  62 #ifdef CHIP_NAND_CTRL
  63     // Enable the Nand Flash Controller
  64     pHSMC4 ->HSMC4_CTRL = AT91C_HSMC4_NFCEN;
  65 #endif
  66
  67     pSMC->HSMC4_SETUP = 0
  68                     | ((0 <<  0) & AT91C_HSMC4_NWE_SETUP)
  69                     | ((1 <<  8) & AT91C_HSMC4_NCS_WR_SETUP)
  70                     | ((0 << 16) & AT91C_HSMC4_NRD_SETUP)
  71                     | ((1 << 24) & AT91C_HSMC4_NCS_RD_SETUP);
  72
  73     pSMC->HSMC4_PULSE = 0
  74                     | ((2 <<  0) & AT91C_HSMC4_NWE_PULSE)
  75                     | ((3 <<  8) & AT91C_HSMC4_NCS_WR_PULSE)
  76                     | ((3 << 16) & AT91C_HSMC4_NRD_PULSE)
  77                     | ((4 << 24) & AT91C_HSMC4_NCS_RD_PULSE);
  78
  79     pSMC->HSMC4_CYCLE = 0
  80                   | ((4 <<  0) & AT91C_HSMC4_NWE_CYCLE)
  81                   | ((7 << 16) & AT91C_HSMC4_NRD_CYCLE);
  82
  83     pSMC->HSMC4_TIMINGS = 0
  84                     | ((1 <<  0) & AT91C_HSMC4_TCLR) // CLE to REN
  85                     | ((2 <<  4) & AT91C_HSMC4_TADL) // ALE to Data
  86                     | ((1 <<  8) & AT91C_HSMC4_TAR)  // ALE to REN
  87                     | ((1 << 16) & AT91C_HSMC4_TRR)  // Ready to REN
  88                     | ((2 << 24) & AT91C_HSMC4_TWB)  // WEN to REN
  89                     | (7<<28)
  90                     |(AT91C_HSMC4_NFSEL)              // Nand Flash Timing
  91                     ;
  92
  93
  94     if (busWidth == 8) {
  95         pSMC->HSMC4_MODE = AT91C_HSMC4_DBW_WIDTH_EIGTH_BITS | AT91C_HSMC4_READ_MODE | AT91C_HSMC4_WRITE_MODE;
  96     }
  97     else if (busWidth == 16) {
  98         pSMC->HSMC4_MODE = AT91C_HSMC4_DBW_WIDTH_SIXTEEN_BITS | AT91C_HSMC4_READ_MODE | AT91C_HSMC4_WRITE_MODE;
  99     }
 100 }
 101