1 //*****************************************************************************
3 // hw_can.h - Defines and macros used when accessing the can.
5 // Copyright (c) 2006-2008 Luminary Micro, Inc. All rights reserved.
7 // Software License Agreement
9 // Luminary Micro, Inc. (LMI) is supplying this software for use solely and
10 // exclusively on LMI's microcontroller products.
12 // The software is owned by LMI and/or its suppliers, and is protected under
13 // applicable copyright laws. All rights are reserved. You may not combine
14 // this software with "viral" open-source software in order to form a larger
15 // program. Any use in violation of the foregoing restrictions may subject
16 // the user to criminal sanctions under applicable laws, as well as to civil
17 // liability for the breach of the terms and conditions of this license.
19 // THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
20 // OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
21 // MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
22 // LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
23 // CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
25 // This is part of revision 2523 of the Stellaris Peripheral Driver Library.
27 //*****************************************************************************
32 //*****************************************************************************
34 // The following are defines for the CAN register offsets.
36 //*****************************************************************************
37 #define CAN_O_CTL 0x00000000 // Control register
38 #define CAN_O_STS 0x00000004 // Status register
39 #define CAN_O_ERR 0x00000008 // Error register
40 #define CAN_O_BIT 0x0000000C // Bit Timing register
41 #define CAN_O_INT 0x00000010 // Interrupt register
42 #define CAN_O_TST 0x00000014 // Test register
43 #define CAN_O_BRPE 0x00000018 // Baud Rate Prescaler register
44 #define CAN_O_IF1CRQ 0x00000020 // Interface 1 Command Request reg.
45 #define CAN_O_IF1CMSK 0x00000024 // Interface 1 Command Mask reg.
46 #define CAN_O_IF1MSK1 0x00000028 // Interface 1 Mask 1 register
47 #define CAN_O_IF1MSK2 0x0000002C // Interface 1 Mask 2 register
48 #define CAN_O_IF1ARB1 0x00000030 // Interface 1 Arbitration 1 reg.
49 #define CAN_O_IF1ARB2 0x00000034 // Interface 1 Arbitration 2 reg.
50 #define CAN_O_IF1MCTL 0x00000038 // Interface 1 Message Control reg.
51 #define CAN_O_IF1DA1 0x0000003C // Interface 1 DataA 1 register
52 #define CAN_O_IF1DA2 0x00000040 // Interface 1 DataA 2 register
53 #define CAN_O_IF1DB1 0x00000044 // Interface 1 DataB 1 register
54 #define CAN_O_IF1DB2 0x00000048 // Interface 1 DataB 2 register
55 #define CAN_O_IF2CRQ 0x00000080 // Interface 2 Command Request reg.
56 #define CAN_O_IF2CMSK 0x00000084 // Interface 2 Command Mask reg.
57 #define CAN_O_IF2MSK1 0x00000088 // Interface 2 Mask 1 register
58 #define CAN_O_IF2MSK2 0x0000008C // Interface 2 Mask 2 register
59 #define CAN_O_IF2ARB1 0x00000090 // Interface 2 Arbitration 1 reg.
60 #define CAN_O_IF2ARB2 0x00000094 // Interface 2 Arbitration 2 reg.
61 #define CAN_O_IF2MCTL 0x00000098 // Interface 2 Message Control reg.
62 #define CAN_O_IF2DA1 0x0000009C // Interface 2 DataA 1 register
63 #define CAN_O_IF2DA2 0x000000A0 // Interface 2 DataA 2 register
64 #define CAN_O_IF2DB1 0x000000A4 // Interface 2 DataB 1 register
65 #define CAN_O_IF2DB2 0x000000A8 // Interface 2 DataB 2 register
66 #define CAN_O_TXRQ1 0x00000100 // Transmission Request 1 register
67 #define CAN_O_TXRQ2 0x00000104 // Transmission Request 2 register
68 #define CAN_O_NWDA1 0x00000120 // New Data 1 register
69 #define CAN_O_NWDA2 0x00000124 // New Data 2 register
70 #define CAN_O_MSG1INT 0x00000140 // CAN Message 1 Interrupt Pending
71 #define CAN_O_MSG2INT 0x00000144 // CAN Message 2 Interrupt Pending
72 #define CAN_O_MSG1VAL 0x00000160 // CAN Message 1 Valid
73 #define CAN_O_MSG2VAL 0x00000164 // CAN Message 2 Valid
75 //*****************************************************************************
77 // The following are defines for the bit fields in the CAN_CTL register.
79 //*****************************************************************************
80 #define CAN_CTL_TEST 0x00000080 // Test mode enable
81 #define CAN_CTL_CCE 0x00000040 // Configuration change enable
82 #define CAN_CTL_DAR 0x00000020 // Disable automatic retransmission
83 #define CAN_CTL_EIE 0x00000008 // Error interrupt enable
84 #define CAN_CTL_SIE 0x00000004 // Status change interrupt enable
85 #define CAN_CTL_IE 0x00000002 // Module interrupt enable
86 #define CAN_CTL_INIT 0x00000001 // Initialization
88 //*****************************************************************************
90 // The following are defines for the bit fields in the CAN_STS register.
92 //*****************************************************************************
93 #define CAN_STS_BOFF 0x00000080 // Bus Off status
94 #define CAN_STS_EWARN 0x00000040 // Error Warning status
95 #define CAN_STS_EPASS 0x00000020 // Error Passive status
96 #define CAN_STS_RXOK 0x00000010 // Received Message Successful
97 #define CAN_STS_TXOK 0x00000008 // Transmitted Message Successful
98 #define CAN_STS_LEC_M 0x00000007 // Last Error Code
99 #define CAN_STS_LEC_NONE 0x00000000 // No error
100 #define CAN_STS_LEC_STUFF 0x00000001 // Stuff error
101 #define CAN_STS_LEC_FORM 0x00000002 // Form(at) error
102 #define CAN_STS_LEC_ACK 0x00000003 // Ack error
103 #define CAN_STS_LEC_BIT1 0x00000004 // Bit 1 error
104 #define CAN_STS_LEC_BIT0 0x00000005 // Bit 0 error
105 #define CAN_STS_LEC_CRC 0x00000006 // CRC error
106 #define CAN_STS_LEC_NOEVENT 0x00000007 // Unused
108 //*****************************************************************************
110 // The following are defines for the bit fields in the CAN_ERR register.
112 //*****************************************************************************
113 #define CAN_ERR_RP 0x00008000 // Receive error passive status
114 #define CAN_ERR_REC_M 0x00007F00 // Receive Error Counter.
115 #define CAN_ERR_TEC_M 0x000000FF // Transmit Error Counter.
116 #define CAN_ERR_REC_S 8 // Receive error counter bit pos
117 #define CAN_ERR_TEC_S 0 // Transmit error counter bit pos
119 //*****************************************************************************
121 // The following are defines for the bit fields in the CAN_BIT register.
123 //*****************************************************************************
124 #define CAN_BIT_TSEG2_M 0x00007000 // Time Segment after Sample Point.
125 #define CAN_BIT_TSEG1_M 0x00000F00 // Time Segment Before Sample
127 #define CAN_BIT_SJW_M 0x000000C0 // (Re)Synchronization Jump Width.
128 #define CAN_BIT_BRP_M 0x0000003F // Baud Rate Prescalar.
129 #define CAN_BIT_TSEG2_S 12
130 #define CAN_BIT_TSEG1_S 8
131 #define CAN_BIT_SJW_S 6
132 #define CAN_BIT_BRP_S 0
134 //*****************************************************************************
136 // The following are defines for the bit fields in the CAN_INT register.
138 //*****************************************************************************
139 #define CAN_INT_INTID_M 0x0000FFFF // Interrupt Identifier.
140 #define CAN_INT_INTID_NONE 0x00000000 // No Interrupt Pending
141 #define CAN_INT_INTID_STATUS 0x00008000 // Status Interrupt
143 //*****************************************************************************
145 // The following are defines for the bit fields in the CAN_TST register.
147 //*****************************************************************************
148 #define CAN_TST_RX 0x00000080 // CAN_RX pin status
149 #define CAN_TST_TX_M 0x00000060 // Overide control of CAN_TX pin
150 #define CAN_TST_TX_CANCTL 0x00000000 // CAN core controls CAN_TX
151 #define CAN_TST_TX_SAMPLE 0x00000020 // Sample Point on CAN_TX
152 #define CAN_TST_TX_DOMINANT 0x00000040 // Dominant value on CAN_TX
153 #define CAN_TST_TX_RECESSIVE 0x00000060 // Recessive value on CAN_TX
154 #define CAN_TST_LBACK 0x00000010 // Loop back mode
155 #define CAN_TST_SILENT 0x00000008 // Silent mode
156 #define CAN_TST_BASIC 0x00000004 // Basic mode
158 //*****************************************************************************
160 // The following are defines for the bit fields in the CAN_BRPE register.
162 //*****************************************************************************
163 #define CAN_BRPE_BRPE_M 0x0000000F // Baud Rate Prescalar Extension.
164 #define CAN_BRPE_BRPE_S 0
166 //*****************************************************************************
168 // The following are defines for the bit fields in the CAN_TXRQ1 register.
170 //*****************************************************************************
171 #define CAN_TXRQ1_TXRQST_M 0x0000FFFF // Transmission Request Bits.
172 #define CAN_TXRQ1_TXRQST_S 0
174 //*****************************************************************************
176 // The following are defines for the bit fields in the CAN_TXRQ2 register.
178 //*****************************************************************************
179 #define CAN_TXRQ2_TXRQST_M 0x0000FFFF // Transmission Request Bits.
180 #define CAN_TXRQ2_TXRQST_S 0
182 //*****************************************************************************
184 // The following are defines for the bit fields in the CAN_NWDA1 register.
186 //*****************************************************************************
187 #define CAN_NWDA1_NEWDAT_M 0x0000FFFF // New Data Bits.
188 #define CAN_NWDA1_NEWDAT_S 0
190 //*****************************************************************************
192 // The following are defines for the bit fields in the CAN_NWDA2 register.
194 //*****************************************************************************
195 #define CAN_NWDA2_NEWDAT_M 0x0000FFFF // New Data Bits.
196 #define CAN_NWDA2_NEWDAT_S 0
198 //*****************************************************************************
200 // The following are defines for the bit fields in the CAN_O_IF1CRQ register.
202 //*****************************************************************************
203 #define CAN_IF1CRQ_BUSY 0x00008000 // Busy Flag.
204 #define CAN_IF1CRQ_MNUM_M 0x0000003F // Message Number.
205 #define CAN_IF1CRQ_MNUM_RSVD 0x00000000 // 0 is not a valid message number;
206 // it is interpreted as 0x20, or
209 //*****************************************************************************
211 // The following are defines for the bit fields in the CAN_O_IF1CMSK register.
213 //*****************************************************************************
214 #define CAN_IF1CMSK_WRNRD 0x00000080 // Write, Not Read.
215 #define CAN_IF1CMSK_MASK 0x00000040 // Access Mask Bits.
216 #define CAN_IF1CMSK_ARB 0x00000020 // Access Arbitration Bits.
217 #define CAN_IF1CMSK_CONTROL 0x00000010 // Access Control Bits.
218 #define CAN_IF1CMSK_CLRINTPND 0x00000008 // Clear Interrupt Pending Bit.
219 #define CAN_IF1CMSK_NEWDAT 0x00000004 // Access New Data.
220 #define CAN_IF1CMSK_TXRQST 0x00000004 // Access Transmission Request.
221 #define CAN_IF1CMSK_DATAA 0x00000002 // Access Data Byte 0 to 3.
222 #define CAN_IF1CMSK_DATAB 0x00000001 // Access Data Byte 4 to 7.
224 //*****************************************************************************
226 // The following are defines for the bit fields in the CAN_O_IF1MSK1 register.
228 //*****************************************************************************
229 #define CAN_IF1MSK1_IDMSK_M 0x0000FFFF // Identifier Mask.
230 #define CAN_IF1MSK1_IDMSK_S 0
232 //*****************************************************************************
234 // The following are defines for the bit fields in the CAN_O_IF1MSK2 register.
236 //*****************************************************************************
237 #define CAN_IF1MSK2_MXTD 0x00008000 // Mask Extended Identifier.
238 #define CAN_IF1MSK2_MDIR 0x00004000 // Mask Message Direction.
239 #define CAN_IF1MSK2_IDMSK_M 0x00001FFF // Identifier Mask.
240 #define CAN_IF1MSK2_IDMSK_S 0
242 //*****************************************************************************
244 // The following are defines for the bit fields in the CAN_O_IF1ARB1 register.
246 //*****************************************************************************
247 #define CAN_IF1ARB1_ID_M 0x0000FFFF // Message Identifier.
248 #define CAN_IF1ARB1_ID_S 0
250 //*****************************************************************************
252 // The following are defines for the bit fields in the CAN_O_IF1ARB2 register.
254 //*****************************************************************************
255 #define CAN_IF1ARB2_MSGVAL 0x00008000 // Message Valid.
256 #define CAN_IF1ARB2_XTD 0x00004000 // Extended Identifier.
257 #define CAN_IF1ARB2_DIR 0x00002000 // Message Direction.
258 #define CAN_IF1ARB2_ID_M 0x00001FFF // Message Identifier.
259 #define CAN_IF1ARB2_ID_S 0
261 //*****************************************************************************
263 // The following are defines for the bit fields in the CAN_O_IF1MCTL register.
265 //*****************************************************************************
266 #define CAN_IF1MCTL_NEWDAT 0x00008000 // New Data.
267 #define CAN_IF1MCTL_MSGLST 0x00004000 // Message Lost.
268 #define CAN_IF1MCTL_INTPND 0x00002000 // Interrupt Pending.
269 #define CAN_IF1MCTL_UMASK 0x00001000 // Use Acceptance Mask.
270 #define CAN_IF1MCTL_TXIE 0x00000800 // Transmit Interrupt Enable.
271 #define CAN_IF1MCTL_RXIE 0x00000400 // Receive Interrupt Enable.
272 #define CAN_IF1MCTL_RMTEN 0x00000200 // Remote Enable.
273 #define CAN_IF1MCTL_TXRQST 0x00000100 // Transmit Request.
274 #define CAN_IF1MCTL_EOB 0x00000080 // End of Buffer.
275 #define CAN_IF1MCTL_DLC_M 0x0000000F // Data Length Code.
276 #define CAN_IF1MCTL_DLC_S 0
278 //*****************************************************************************
280 // The following are defines for the bit fields in the CAN_O_IF1DA1 register.
282 //*****************************************************************************
283 #define CAN_IF1DA1_DATA_M 0x0000FFFF // Data.
284 #define CAN_IF1DA1_DATA_S 0
286 //*****************************************************************************
288 // The following are defines for the bit fields in the CAN_O_IF1DA2 register.
290 //*****************************************************************************
291 #define CAN_IF1DA2_DATA_M 0x0000FFFF // Data.
292 #define CAN_IF1DA2_DATA_S 0
294 //*****************************************************************************
296 // The following are defines for the bit fields in the CAN_O_IF1DB1 register.
298 //*****************************************************************************
299 #define CAN_IF1DB1_DATA_M 0x0000FFFF // Data.
300 #define CAN_IF1DB1_DATA_S 0
302 //*****************************************************************************
304 // The following are defines for the bit fields in the CAN_O_IF1DB2 register.
306 //*****************************************************************************
307 #define CAN_IF1DB2_DATA_M 0x0000FFFF // Data.
308 #define CAN_IF1DB2_DATA_S 0
310 //*****************************************************************************
312 // The following are defines for the bit fields in the CAN_O_IF2CRQ register.
314 //*****************************************************************************
315 #define CAN_IF2CRQ_BUSY 0x00008000 // Busy Flag.
316 #define CAN_IF2CRQ_MNUM_M 0x0000003F // Message Number.
317 #define CAN_IF2CRQ_MNUM_RSVD 0x00000000 // 0 is not a valid message number;
318 // it is interpreted as 0x20, or
321 //*****************************************************************************
323 // The following are defines for the bit fields in the CAN_O_IF2CMSK register.
325 //*****************************************************************************
326 #define CAN_IF2CMSK_WRNRD 0x00000080 // Write, Not Read.
327 #define CAN_IF2CMSK_MASK 0x00000040 // Access Mask Bits.
328 #define CAN_IF2CMSK_ARB 0x00000020 // Access Arbitration Bits.
329 #define CAN_IF2CMSK_CONTROL 0x00000010 // Access Control Bits.
330 #define CAN_IF2CMSK_CLRINTPND 0x00000008 // Clear Interrupt Pending Bit.
331 #define CAN_IF2CMSK_NEWDAT 0x00000004 // Access New Data.
332 #define CAN_IF2CMSK_TXRQST 0x00000004 // Access Transmission Request.
333 #define CAN_IF2CMSK_DATAA 0x00000002 // Access Data Byte 0 to 3.
334 #define CAN_IF2CMSK_DATAB 0x00000001 // Access Data Byte 4 to 7.
336 //*****************************************************************************
338 // The following are defines for the bit fields in the CAN_O_IF2MSK1 register.
340 //*****************************************************************************
341 #define CAN_IF2MSK1_IDMSK_M 0x0000FFFF // Identifier Mask.
342 #define CAN_IF2MSK1_IDMSK_S 0
344 //*****************************************************************************
346 // The following are defines for the bit fields in the CAN_O_IF2MSK2 register.
348 //*****************************************************************************
349 #define CAN_IF2MSK2_MXTD 0x00008000 // Mask Extended Identifier.
350 #define CAN_IF2MSK2_MDIR 0x00004000 // Mask Message Direction.
351 #define CAN_IF2MSK2_IDMSK_M 0x00001FFF // Identifier Mask.
352 #define CAN_IF2MSK2_IDMSK_S 0
354 //*****************************************************************************
356 // The following are defines for the bit fields in the CAN_O_IF2ARB1 register.
358 //*****************************************************************************
359 #define CAN_IF2ARB1_ID_M 0x0000FFFF // Message Identifier.
360 #define CAN_IF2ARB1_ID_S 0
362 //*****************************************************************************
364 // The following are defines for the bit fields in the CAN_O_IF2ARB2 register.
366 //*****************************************************************************
367 #define CAN_IF2ARB2_MSGVAL 0x00008000 // Message Valid.
368 #define CAN_IF2ARB2_XTD 0x00004000 // Extended Identifier.
369 #define CAN_IF2ARB2_DIR 0x00002000 // Message Direction.
370 #define CAN_IF2ARB2_ID_M 0x00001FFF // Message Identifier.
371 #define CAN_IF2ARB2_ID_S 0
373 //*****************************************************************************
375 // The following are defines for the bit fields in the CAN_O_IF2MCTL register.
377 //*****************************************************************************
378 #define CAN_IF2MCTL_NEWDAT 0x00008000 // New Data.
379 #define CAN_IF2MCTL_MSGLST 0x00004000 // Message Lost.
380 #define CAN_IF2MCTL_INTPND 0x00002000 // Interrupt Pending.
381 #define CAN_IF2MCTL_UMASK 0x00001000 // Use Acceptance Mask.
382 #define CAN_IF2MCTL_TXIE 0x00000800 // Transmit Interrupt Enable.
383 #define CAN_IF2MCTL_RXIE 0x00000400 // Receive Interrupt Enable.
384 #define CAN_IF2MCTL_RMTEN 0x00000200 // Remote Enable.
385 #define CAN_IF2MCTL_TXRQST 0x00000100 // Transmit Request.
386 #define CAN_IF2MCTL_EOB 0x00000080 // End of Buffer.
387 #define CAN_IF2MCTL_DLC_M 0x0000000F // Data Length Code.
388 #define CAN_IF2MCTL_DLC_S 0
390 //*****************************************************************************
392 // The following are defines for the bit fields in the CAN_O_IF2DA1 register.
394 //*****************************************************************************
395 #define CAN_IF2DA1_DATA_M 0x0000FFFF // Data.
396 #define CAN_IF2DA1_DATA_S 0
398 //*****************************************************************************
400 // The following are defines for the bit fields in the CAN_O_IF2DA2 register.
402 //*****************************************************************************
403 #define CAN_IF2DA2_DATA_M 0x0000FFFF // Data.
404 #define CAN_IF2DA2_DATA_S 0
406 //*****************************************************************************
408 // The following are defines for the bit fields in the CAN_O_IF2DB1 register.
410 //*****************************************************************************
411 #define CAN_IF2DB1_DATA_M 0x0000FFFF // Data.
412 #define CAN_IF2DB1_DATA_S 0
414 //*****************************************************************************
416 // The following are defines for the bit fields in the CAN_O_IF2DB2 register.
418 //*****************************************************************************
419 #define CAN_IF2DB2_DATA_M 0x0000FFFF // Data.
420 #define CAN_IF2DB2_DATA_S 0
422 //*****************************************************************************
424 // The following are defines for the bit fields in the CAN_O_MSG1INT register.
426 //*****************************************************************************
427 #define CAN_MSG1INT_INTPND_M 0x0000FFFF // Interrupt Pending Bits.
428 #define CAN_MSG1INT_INTPND_S 0
430 //*****************************************************************************
432 // The following are defines for the bit fields in the CAN_O_MSG2INT register.
434 //*****************************************************************************
435 #define CAN_MSG2INT_INTPND_M 0x0000FFFF // Interrupt Pending Bits.
436 #define CAN_MSG2INT_INTPND_S 0
438 //*****************************************************************************
440 // The following are defines for the bit fields in the CAN_O_MSG1VAL register.
442 //*****************************************************************************
443 #define CAN_MSG1VAL_MSGVAL_M 0x0000FFFF // Message Valid Bits.
444 #define CAN_MSG1VAL_MSGVAL_S 0
446 //*****************************************************************************
448 // The following are defines for the bit fields in the CAN_O_MSG2VAL register.
450 //*****************************************************************************
451 #define CAN_MSG2VAL_MSGVAL_M 0x0000FFFF // Message Valid Bits.
452 #define CAN_MSG2VAL_MSGVAL_S 0
454 //*****************************************************************************
456 // The following definitions are deprecated.
458 //*****************************************************************************
461 //*****************************************************************************
463 // The following are deprecated defines for the CAN register offsets.
465 //*****************************************************************************
466 #define CAN_O_MSGINT1 0x00000140 // Intr. Pending in Msg Obj 1 reg.
467 #define CAN_O_MSGINT2 0x00000144 // Intr. Pending in Msg Obj 2 reg.
468 #define CAN_O_MSGVAL1 0x00000160 // Message Valid in Msg Obj 1 reg.
469 #define CAN_O_MSGVAL2 0x00000164 // Message Valid in Msg Obj 2 reg.
471 //*****************************************************************************
473 // The following are deprecated defines for the reset values of the can
476 //*****************************************************************************
477 #define CAN_RV_IF1MSK2 0x0000FFFF
478 #define CAN_RV_IF1MSK1 0x0000FFFF
479 #define CAN_RV_IF2MSK1 0x0000FFFF
480 #define CAN_RV_IF2MSK2 0x0000FFFF
481 #define CAN_RV_BIT 0x00002301
482 #define CAN_RV_CTL 0x00000001
483 #define CAN_RV_IF1CRQ 0x00000001
484 #define CAN_RV_IF2CRQ 0x00000001
485 #define CAN_RV_TXRQ2 0x00000000
486 #define CAN_RV_IF2DB1 0x00000000
487 #define CAN_RV_INT 0x00000000
488 #define CAN_RV_IF1DB2 0x00000000
489 #define CAN_RV_BRPE 0x00000000
490 #define CAN_RV_IF2DA2 0x00000000
491 #define CAN_RV_MSGVAL2 0x00000000
492 #define CAN_RV_TXRQ1 0x00000000
493 #define CAN_RV_IF1MCTL 0x00000000
494 #define CAN_RV_IF1DB1 0x00000000
495 #define CAN_RV_STS 0x00000000
496 #define CAN_RV_MSGINT1 0x00000000
497 #define CAN_RV_IF1DA2 0x00000000
498 #define CAN_RV_TST 0x00000000
499 #define CAN_RV_IF1ARB1 0x00000000
500 #define CAN_RV_IF1ARB2 0x00000000
501 #define CAN_RV_NWDA2 0x00000000
502 #define CAN_RV_IF2CMSK 0x00000000
503 #define CAN_RV_NWDA1 0x00000000
504 #define CAN_RV_IF1DA1 0x00000000
505 #define CAN_RV_IF2DA1 0x00000000
506 #define CAN_RV_IF2MCTL 0x00000000
507 #define CAN_RV_MSGVAL1 0x00000000
508 #define CAN_RV_IF1CMSK 0x00000000
509 #define CAN_RV_ERR 0x00000000
510 #define CAN_RV_IF2ARB2 0x00000000
511 #define CAN_RV_MSGINT2 0x00000000
512 #define CAN_RV_IF2ARB1 0x00000000
513 #define CAN_RV_IF2DB2 0x00000000
515 //*****************************************************************************
517 // The following are deprecated defines for the bit fields in the CAN_STS
520 //*****************************************************************************
521 #define CAN_STS_LEC_MSK 0x00000007 // Last Error Code
523 //*****************************************************************************
525 // The following are deprecated defines for the bit fields in the CAN_ERR
528 //*****************************************************************************
529 #define CAN_ERR_REC_MASK 0x00007F00 // Receive error counter status
530 #define CAN_ERR_TEC_MASK 0x000000FF // Transmit error counter status
531 #define CAN_ERR_REC_SHIFT 8 // Receive error counter bit pos
532 #define CAN_ERR_TEC_SHIFT 0 // Transmit error counter bit pos
534 //*****************************************************************************
536 // The following are deprecated defines for the bit fields in the CAN_BIT
539 //*****************************************************************************
540 #define CAN_BIT_TSEG2 0x00007000 // Time segment after sample point
541 #define CAN_BIT_TSEG1 0x00000F00 // Time segment before sample point
542 #define CAN_BIT_SJW 0x000000C0 // (Re)Synchronization jump width
543 #define CAN_BIT_BRP 0x0000003F // Baud rate prescaler
545 //*****************************************************************************
547 // The following are deprecated defines for the bit fields in the CAN_INT
550 //*****************************************************************************
551 #define CAN_INT_INTID_MSK 0x0000FFFF // Interrupt Identifier
553 //*****************************************************************************
555 // The following are deprecated defines for the bit fields in the CAN_TST
558 //*****************************************************************************
559 #define CAN_TST_TX_MSK 0x00000060 // Overide control of CAN_TX pin
561 //*****************************************************************************
563 // The following are deprecated defines for the bit fields in the CAN_BRPE
566 //*****************************************************************************
567 #define CAN_BRPE_BRPE 0x0000000F // Baud rate prescaler extension
569 //*****************************************************************************
571 // The following are deprecated defines for the bit fields in the CAN_IF1CRQ
572 // and CAN_IF1CRQ registers.
573 // Note: All bits may not be available in all registers
575 //*****************************************************************************
576 #define CAN_IFCRQ_BUSY 0x00008000 // Busy flag status
577 #define CAN_IFCRQ_MNUM_MSK 0x0000003F // Message Number
579 //*****************************************************************************
581 // The following are deprecated defines for the bit fields in the CAN_IF1CMSK
582 // and CAN_IF2CMSK registers.
583 // Note: All bits may not be available in all registers
585 //*****************************************************************************
586 #define CAN_IFCMSK_WRNRD 0x00000080 // Write, not Read
587 #define CAN_IFCMSK_MASK 0x00000040 // Access Mask Bits
588 #define CAN_IFCMSK_ARB 0x00000020 // Access Arbitration Bits
589 #define CAN_IFCMSK_CONTROL 0x00000010 // Access Control Bits
590 #define CAN_IFCMSK_CLRINTPND 0x00000008 // Clear interrupt pending Bit
591 #define CAN_IFCMSK_TXRQST 0x00000004 // Access Tx request bit (WRNRD=1)
592 #define CAN_IFCMSK_NEWDAT 0x00000004 // Access New Data bit (WRNRD=0)
593 #define CAN_IFCMSK_DATAA 0x00000002 // DataA access - bytes 0 to 3
594 #define CAN_IFCMSK_DATAB 0x00000001 // DataB access - bytes 4 to 7
596 //*****************************************************************************
598 // The following are deprecated defines for the bit fields in the CAN_IF1MSK1
599 // and CAN_IF2MSK1 registers.
600 // Note: All bits may not be available in all registers
602 //*****************************************************************************
603 #define CAN_IFMSK1_MSK 0x0000FFFF // Identifier Mask
605 //*****************************************************************************
607 // The following are deprecated defines for the bit fields in the CAN_IF1MSK2
608 // and CAN_IF2MSK2 registers.
609 // Note: All bits may not be available in all registers
611 //*****************************************************************************
612 #define CAN_IFMSK2_MXTD 0x00008000 // Mask extended identifier
613 #define CAN_IFMSK2_MDIR 0x00004000 // Mask message direction
614 #define CAN_IFMSK2_MSK 0x00001FFF // Mask identifier
616 //*****************************************************************************
618 // The following are deprecated defines for the bit fields in the CAN_IF1ARB1
619 // and CAN_IF2ARB1 registers.
620 // Note: All bits may not be available in all registers
622 //*****************************************************************************
623 #define CAN_IFARB1_ID 0x0000FFFF // Identifier
625 //*****************************************************************************
627 // The following are deprecated defines for the bit fields in the CAN_IF1ARB2
628 // and CAN_IF2ARB2 registers.
629 // Note: All bits may not be available in all registers
631 //*****************************************************************************
632 #define CAN_IFARB2_MSGVAL 0x00008000 // Message valid
633 #define CAN_IFARB2_XTD 0x00004000 // Extended identifier
634 #define CAN_IFARB2_DIR 0x00002000 // Message direction
635 #define CAN_IFARB2_ID 0x00001FFF // Message identifier
637 //*****************************************************************************
639 // The following are deprecated defines for the bit fields in the CAN_IF1MCTL
640 // and CAN_IF2MCTL registers.
641 // Note: All bits may not be available in all registers
643 //*****************************************************************************
644 #define CAN_IFMCTL_NEWDAT 0x00008000 // New Data
645 #define CAN_IFMCTL_MSGLST 0x00004000 // Message lost
646 #define CAN_IFMCTL_INTPND 0x00002000 // Interrupt pending
647 #define CAN_IFMCTL_UMASK 0x00001000 // Use acceptance mask
648 #define CAN_IFMCTL_TXIE 0x00000800 // Transmit interrupt enable
649 #define CAN_IFMCTL_RXIE 0x00000400 // Receive interrupt enable
650 #define CAN_IFMCTL_RMTEN 0x00000200 // Remote enable
651 #define CAN_IFMCTL_TXRQST 0x00000100 // Transmit request
652 #define CAN_IFMCTL_EOB 0x00000080 // End of buffer
653 #define CAN_IFMCTL_DLC 0x0000000F // Data length code
655 //*****************************************************************************
657 // The following are deprecated defines for the bit fields in the CAN_IF1DA1
658 // and CAN_IF2DA1 registers.
659 // Note: All bits may not be available in all registers
661 //*****************************************************************************
662 #define CAN_IFDA1_DATA 0x0000FFFF // Data - bytes 1 and 0
664 //*****************************************************************************
666 // The following are deprecated defines for the bit fields in the CAN_IF1DA2
667 // and CAN_IF2DA2 registers.
668 // Note: All bits may not be available in all registers
670 //*****************************************************************************
671 #define CAN_IFDA2_DATA 0x0000FFFF // Data - bytes 3 and 2
673 //*****************************************************************************
675 // The following are deprecated defines for the bit fields in the CAN_IF1DB1
676 // and CAN_IF2DB1 registers.
677 // Note: All bits may not be available in all registers
679 //*****************************************************************************
680 #define CAN_IFDB1_DATA 0x0000FFFF // Data - bytes 5 and 4
682 //*****************************************************************************
684 // The following are deprecated defines for the bit fields in the CAN_IF1DB2
685 // and CAN_IF2DB2 registers.
686 // Note: All bits may not be available in all registers
688 //*****************************************************************************
689 #define CAN_IFDB2_DATA 0x0000FFFF // Data - bytes 7 and 6
691 //*****************************************************************************
693 // The following are deprecated defines for the bit fields in the CAN_TXRQ1
696 //*****************************************************************************
697 #define CAN_TXRQ1_TXRQST 0x0000FFFF // Transmission Request Bits
699 //*****************************************************************************
701 // The following are deprecated defines for the bit fields in the CAN_TXRQ2
704 //*****************************************************************************
705 #define CAN_TXRQ2_TXRQST 0x0000FFFF // Transmission Request Bits
707 //*****************************************************************************
709 // The following are deprecated defines for the bit fields in the CAN_NWDA1
712 //*****************************************************************************
713 #define CAN_NWDA1_NEWDATA 0x0000FFFF // New Data Bits
715 //*****************************************************************************
717 // The following are deprecated defines for the bit fields in the CAN_NWDA2
720 //*****************************************************************************
721 #define CAN_NWDA2_NEWDATA 0x0000FFFF // New Data Bits
723 //*****************************************************************************
725 // The following are deprecated defines for the bit fields in the CAN_MSGINT1
728 //*****************************************************************************
729 #define CAN_MSGINT1_INTPND 0x0000FFFF // Interrupt Pending Bits
731 //*****************************************************************************
733 // The following are deprecated defines for the bit fields in the CAN_MSGINT2
736 //*****************************************************************************
737 #define CAN_MSGINT2_INTPND 0x0000FFFF // Interrupt Pending Bits
739 //*****************************************************************************
741 // The following are deprecated defines for the bit fields in the CAN_MSGVAL1
744 //*****************************************************************************
745 #define CAN_MSGVAL1_MSGVAL 0x0000FFFF // Message Valid Bits
747 //*****************************************************************************
749 // The following are deprecated defines for the bit fields in the CAN_MSGVAL2
752 //*****************************************************************************
753 #define CAN_MSGVAL2_MSGVAL 0x0000FFFF // Message Valid Bits
757 #endif // __HW_CAN_H__
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