begriffs open source - cmsis-freertos/blob - Source/portable/GCC/ARM_CA53_64_BIT/portmacro.h

   1 /*
   2     FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd.
   3     All rights reserved
   4
   5     VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
   6
   7     This file is part of the FreeRTOS distribution.
   8
   9     FreeRTOS is free software; you can redistribute it and/or modify it under
  10     the terms of the GNU General Public License (version 2) as published by the
  11     Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
  12
  13     ***************************************************************************
  14     >>!   NOTE: The modification to the GPL is included to allow you to     !<<
  15     >>!   distribute a combined work that includes FreeRTOS without being   !<<
  16     >>!   obliged to provide the source code for proprietary components     !<<
  17     >>!   outside of the FreeRTOS kernel.                                   !<<
  18     ***************************************************************************
  19
  20     FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
  21     WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
  22     FOR A PARTICULAR PURPOSE.  Full license text is available on the following
  23     link: http://www.freertos.org/a00114.html
  24
  25     ***************************************************************************
  26      *                                                                       *
  27      *    FreeRTOS provides completely free yet professionally developed,    *
  28      *    robust, strictly quality controlled, supported, and cross          *
  29      *    platform software that is more than just the market leader, it     *
  30      *    is the industry's de facto standard.                               *
  31      *                                                                       *
  32      *    Help yourself get started quickly while simultaneously helping     *
  33      *    to support the FreeRTOS project by purchasing a FreeRTOS           *
  34      *    tutorial book, reference manual, or both:                          *
  35      *    http://www.FreeRTOS.org/Documentation                              *
  36      *                                                                       *
  37     ***************************************************************************
  38
  39     http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
  40     the FAQ page "My application does not run, what could be wrong?".  Have you
  41     defined configASSERT()?
  42
  43     http://www.FreeRTOS.org/support - In return for receiving this top quality
  44     embedded software for free we request you assist our global community by
  45     participating in the support forum.
  46
  47     http://www.FreeRTOS.org/training - Investing in training allows your team to
  48     be as productive as possible as early as possible.  Now you can receive
  49     FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
  50     Ltd, and the world's leading authority on the world's leading RTOS.
  51
  52     http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
  53     including FreeRTOS+Trace - an indispensable productivity tool, a DOS
  54     compatible FAT file system, and our tiny thread aware UDP/IP stack.
  55
  56     http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
  57     Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
  58
  59     http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
  60     Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS
  61     licenses offer ticketed support, indemnification and commercial middleware.
  62
  63     http://www.SafeRTOS.com - High Integrity Systems also provide a safety
  64     engineered and independently SIL3 certified version for use in safety and
  65     mission critical applications that require provable dependability.
  66
  67     1 tab == 4 spaces!
  68 */
  69
  70 #ifndef PORTMACRO_H
  71 #define PORTMACRO_H
  72
  73 #ifdef __cplusplus
  74         extern "C" {
  75 #endif
  76
  77 /*-----------------------------------------------------------
  78  * Port specific definitions.
  79  *
  80  * The settings in this file configure FreeRTOS correctly for the given hardware
  81  * and compiler.
  82  *
  83  * These settings should not be altered.
  84  *-----------------------------------------------------------
  85  */
  86
  87 /* Type definitions. */
  88 #define portCHAR                char
  89 #define portFLOAT               float
  90 #define portDOUBLE              double
  91 #define portLONG                long
  92 #define portSHORT               short
  93 #define portSTACK_TYPE  size_t
  94 #define portBASE_TYPE   long
  95
  96 typedef portSTACK_TYPE StackType_t;
  97 typedef portBASE_TYPE BaseType_t;
  98 typedef uint64_t UBaseType_t;
  99
 100 typedef uint64_t TickType_t;
 101 #define portMAX_DELAY ( ( TickType_t ) 0xffffffffffffffff )
 102
 103 /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
 104 not need to be guarded with a critical section. */
 105 #define portTICK_TYPE_IS_ATOMIC 1
 106
 107 /*-----------------------------------------------------------*/
 108
 109 /* Hardware specifics. */
 110 #define portSTACK_GROWTH                        ( -1 )
 111 #define portTICK_PERIOD_MS                      ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
 112 #define portBYTE_ALIGNMENT                      16
 113 #define portPOINTER_SIZE_TYPE           uint64_t
 114
 115 /*-----------------------------------------------------------*/
 116
 117 /* Task utilities. */
 118
 119 /* Called at the end of an ISR that can cause a context switch. */
 120 #define portEND_SWITCHING_ISR( xSwitchRequired )\
 121 {                                                                                               \
 122 extern uint64_t ullPortYieldRequired;                   \
 123                                                                                                 \
 124         if( xSwitchRequired != pdFALSE )                        \
 125         {                                                                                       \
 126                 ullPortYieldRequired = pdTRUE;                  \
 127         }                                                                                       \
 128 }
 129
 130 #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
 131 #define portYIELD() __asm volatile ( "SMC 0" )
 132
 133 /*-----------------------------------------------------------
 134  * Critical section control
 135  *----------------------------------------------------------*/
 136
 137 extern void vPortEnterCritical( void );
 138 extern void vPortExitCritical( void );
 139 extern UBaseType_t uxPortSetInterruptMask( void );
 140 extern void vPortClearInterruptMask( UBaseType_t uxNewMaskValue );
 141 extern void vPortInstallFreeRTOSVectorTable( void );
 142
 143 #define portDISABLE_INTERRUPTS()                                                                        \
 144         __asm volatile ( "MSR DAIFSET, #2" );                                                   \
 145         __asm volatile ( "DSB SY" );                                                                    \
 146         __asm volatile ( "ISB SY" );
 147
 148 #define portENABLE_INTERRUPTS()                                                                         \
 149         __asm volatile ( "MSR DAIFCLR, #2" );                                                   \
 150         __asm volatile ( "DSB SY" );                                                                    \
 151         __asm volatile ( "ISB SY" );
 152
 153
 154 /* These macros do not globally disable/enable interrupts.  They do mask off
 155 interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */
 156 #define portENTER_CRITICAL()            vPortEnterCritical();
 157 #define portEXIT_CRITICAL()                     vPortExitCritical();
 158 #define portSET_INTERRUPT_MASK_FROM_ISR()               uxPortSetInterruptMask()
 159 #define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)    vPortClearInterruptMask(x)
 160
 161 /*-----------------------------------------------------------*/
 162
 163 /* Task function macros as described on the FreeRTOS.org WEB site.  These are
 164 not required for this port but included in case common demo code that uses these
 165 macros is used. */
 166 #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )      void vFunction( void *pvParameters )
 167 #define portTASK_FUNCTION( vFunction, pvParameters )    void vFunction( void *pvParameters )
 168
 169 /* Prototype of the FreeRTOS tick handler.  This must be installed as the
 170 handler for whichever peripheral is used to generate the RTOS tick. */
 171 void FreeRTOS_Tick_Handler( void );
 172
 173 /* Any task that uses the floating point unit MUST call vPortTaskUsesFPU()
 174 before any floating point instructions are executed. */
 175 void vPortTaskUsesFPU( void );
 176 #define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()
 177
 178 #define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL )
 179 #define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL )
 180
 181 /* Architecture specific optimisations. */
 182 #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
 183         #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
 184 #endif
 185
 186 #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
 187
 188         /* Store/clear the ready priorities in a bit map. */
 189         #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
 190         #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
 191
 192         /*-----------------------------------------------------------*/
 193
 194         #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __builtin_clz( uxReadyPriorities ) )
 195
 196 #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
 197
 198 #ifdef configASSERT
 199         void vPortValidateInterruptPriority( void );
 200         #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()      vPortValidateInterruptPriority()
 201 #endif /* configASSERT */
 202
 203 #define portNOP() __asm volatile( "NOP" )
 204 #define portINLINE __inline
 205
 206 #ifdef __cplusplus
 207         } /* extern C */
 208 #endif
 209
 210
 211 /* The number of bits to shift for an interrupt priority is dependent on the
 212 number of bits implemented by the interrupt controller. */
 213 #if configUNIQUE_INTERRUPT_PRIORITIES == 16
 214         #define portPRIORITY_SHIFT 4
 215         #define portMAX_BINARY_POINT_VALUE      3
 216 #elif configUNIQUE_INTERRUPT_PRIORITIES == 32
 217         #define portPRIORITY_SHIFT 3
 218         #define portMAX_BINARY_POINT_VALUE      2
 219 #elif configUNIQUE_INTERRUPT_PRIORITIES == 64
 220         #define portPRIORITY_SHIFT 2
 221         #define portMAX_BINARY_POINT_VALUE      1
 222 #elif configUNIQUE_INTERRUPT_PRIORITIES == 128
 223         #define portPRIORITY_SHIFT 1
 224         #define portMAX_BINARY_POINT_VALUE      0
 225 #elif configUNIQUE_INTERRUPT_PRIORITIES == 256
 226         #define portPRIORITY_SHIFT 0
 227         #define portMAX_BINARY_POINT_VALUE      0
 228 #else
 229         #error Invalid configUNIQUE_INTERRUPT_PRIORITIES setting.  configUNIQUE_INTERRUPT_PRIORITIES must be set to the number of unique priorities implemented by the target hardware
 230 #endif
 231
 232 /* Interrupt controller access addresses. */
 233 #define portICCPMR_PRIORITY_MASK_OFFSET                                                 ( 0x04 )
 234 #define portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET                                 ( 0x0C )
 235 #define portICCEOIR_END_OF_INTERRUPT_OFFSET                                     ( 0x10 )
 236 #define portICCBPR_BINARY_POINT_OFFSET                                                  ( 0x08 )
 237 #define portICCRPR_RUNNING_PRIORITY_OFFSET                                              ( 0x14 )
 238
 239 #define portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS          ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET )
 240 #define portICCPMR_PRIORITY_MASK_REGISTER                                       ( *( ( volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) ) )
 241 #define portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS       ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET )
 242 #define portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS           ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCEOIR_END_OF_INTERRUPT_OFFSET )
 243 #define portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS                       ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET )
 244 #define portICCBPR_BINARY_POINT_REGISTER                                        ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCBPR_BINARY_POINT_OFFSET ) ) )
 245 #define portICCRPR_RUNNING_PRIORITY_REGISTER                            ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCRPR_RUNNING_PRIORITY_OFFSET ) ) )
 246
 247 #endif /* PORTMACRO_H */
 248