1 /* - ---------------------------------------------------------------------------- */
2 /* - ATMEL Microcontroller Software Support - ROUSSET - */
3 /* - ---------------------------------------------------------------------------- */
4 /* - DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
5 /* - IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
6 /* - MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
7 /* - DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
8 /* - INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
9 /* - LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
10 /* - OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
11 /* - LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
12 /* - NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
13 /* - EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
14 /* - ---------------------------------------------------------------------------- */
15 /* - File Name : AT91SAM7X256.h */
16 /* - Object : AT91SAM7X256 definitions */
17 /* - Generated : AT91 SW Application Group 05/20/2005 (16:22:29) */
19 /* - CVS Reference : /AT91SAM7X256.pl/1.11/Tue May 10 12:15:32 2005// */
20 /* - CVS Reference : /SYS_SAM7X.pl/1.3/Tue Feb 1 17:01:43 2005// */
21 /* - CVS Reference : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005// */
22 /* - CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 13:58:10 2005// */
23 /* - CVS Reference : /RSTC_SAM7X.pl/1.1/Tue Feb 1 16:16:26 2005// */
24 /* - CVS Reference : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005// */
25 /* - CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005// */
26 /* - CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005// */
27 /* - CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005// */
28 /* - CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004// */
29 /* - CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004// */
30 /* - CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004// */
31 /* - CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005// */
32 /* - CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005// */
33 /* - CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005// */
34 /* - CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005// */
35 /* - CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004// */
36 /* - CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004// */
37 /* - CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004// */
38 /* - CVS Reference : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005// */
39 /* - CVS Reference : /CAN_6019B.pl/1.1/Tue Mar 8 12:42:22 2005// */
40 /* - CVS Reference : /EMACB_6119A.pl/1.5/Thu Feb 3 15:52:04 2005// */
41 /* - CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003// */
42 /* - CVS Reference : /AES_6149A.pl/1.10/Mon Feb 7 09:44:25 2005// */
43 /* - CVS Reference : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005// */
44 /* - ---------------------------------------------------------------------------- */
46 #ifndef AT91SAM7X256_H
47 #define AT91SAM7X256_H
49 typedef volatile unsigned int AT91_REG; /* Hardware register definition */
51 /* ***************************************************************************** */
52 /* SOFTWARE API DEFINITION FOR System Peripherals */
53 /* ***************************************************************************** */
54 typedef struct _AT91S_SYS
56 AT91_REG AIC_SMR[ 32 ]; /* Source Mode Register */
57 AT91_REG AIC_SVR[ 32 ]; /* Source Vector Register */
58 AT91_REG AIC_IVR; /* IRQ Vector Register */
59 AT91_REG AIC_FVR; /* FIQ Vector Register */
60 AT91_REG AIC_ISR; /* Interrupt Status Register */
61 AT91_REG AIC_IPR; /* Interrupt Pending Register */
62 AT91_REG AIC_IMR; /* Interrupt Mask Register */
63 AT91_REG AIC_CISR; /* Core Interrupt Status Register */
64 AT91_REG Reserved0[ 2 ]; /* */
65 AT91_REG AIC_IECR; /* Interrupt Enable Command Register */
66 AT91_REG AIC_IDCR; /* Interrupt Disable Command Register */
67 AT91_REG AIC_ICCR; /* Interrupt Clear Command Register */
68 AT91_REG AIC_ISCR; /* Interrupt Set Command Register */
69 AT91_REG AIC_EOICR; /* End of Interrupt Command Register */
70 AT91_REG AIC_SPU; /* Spurious Vector Register */
71 AT91_REG AIC_DCR; /* Debug Control Register (Protect) */
72 AT91_REG Reserved1[ 1 ]; /* */
73 AT91_REG AIC_FFER; /* Fast Forcing Enable Register */
74 AT91_REG AIC_FFDR; /* Fast Forcing Disable Register */
75 AT91_REG AIC_FFSR; /* Fast Forcing Status Register */
76 AT91_REG Reserved2[ 45 ]; /* */
77 AT91_REG DBGU_CR; /* Control Register */
78 AT91_REG DBGU_MR; /* Mode Register */
79 AT91_REG DBGU_IER; /* Interrupt Enable Register */
80 AT91_REG DBGU_IDR; /* Interrupt Disable Register */
81 AT91_REG DBGU_IMR; /* Interrupt Mask Register */
82 AT91_REG DBGU_CSR; /* Channel Status Register */
83 AT91_REG DBGU_RHR; /* Receiver Holding Register */
84 AT91_REG DBGU_THR; /* Transmitter Holding Register */
85 AT91_REG DBGU_BRGR; /* Baud Rate Generator Register */
86 AT91_REG Reserved3[ 7 ]; /* */
87 AT91_REG DBGU_CIDR; /* Chip ID Register */
88 AT91_REG DBGU_EXID; /* Chip ID Extension Register */
89 AT91_REG DBGU_FNTR; /* Force NTRST Register */
90 AT91_REG Reserved4[ 45 ]; /* */
91 AT91_REG DBGU_RPR; /* Receive Pointer Register */
92 AT91_REG DBGU_RCR; /* Receive Counter Register */
93 AT91_REG DBGU_TPR; /* Transmit Pointer Register */
94 AT91_REG DBGU_TCR; /* Transmit Counter Register */
95 AT91_REG DBGU_RNPR; /* Receive Next Pointer Register */
96 AT91_REG DBGU_RNCR; /* Receive Next Counter Register */
97 AT91_REG DBGU_TNPR; /* Transmit Next Pointer Register */
98 AT91_REG DBGU_TNCR; /* Transmit Next Counter Register */
99 AT91_REG DBGU_PTCR; /* PDC Transfer Control Register */
100 AT91_REG DBGU_PTSR; /* PDC Transfer Status Register */
101 AT91_REG Reserved5[ 54 ]; /* */
102 AT91_REG PIOA_PER; /* PIO Enable Register */
103 AT91_REG PIOA_PDR; /* PIO Disable Register */
104 AT91_REG PIOA_PSR; /* PIO Status Register */
105 AT91_REG Reserved6[ 1 ]; /* */
106 AT91_REG PIOA_OER; /* Output Enable Register */
107 AT91_REG PIOA_ODR; /* Output Disable Registerr */
108 AT91_REG PIOA_OSR; /* Output Status Register */
109 AT91_REG Reserved7[ 1 ]; /* */
110 AT91_REG PIOA_IFER; /* Input Filter Enable Register */
111 AT91_REG PIOA_IFDR; /* Input Filter Disable Register */
112 AT91_REG PIOA_IFSR; /* Input Filter Status Register */
113 AT91_REG Reserved8[ 1 ]; /* */
114 AT91_REG PIOA_SODR; /* Set Output Data Register */
115 AT91_REG PIOA_CODR; /* Clear Output Data Register */
116 AT91_REG PIOA_ODSR; /* Output Data Status Register */
117 AT91_REG PIOA_PDSR; /* Pin Data Status Register */
118 AT91_REG PIOA_IER; /* Interrupt Enable Register */
119 AT91_REG PIOA_IDR; /* Interrupt Disable Register */
120 AT91_REG PIOA_IMR; /* Interrupt Mask Register */
121 AT91_REG PIOA_ISR; /* Interrupt Status Register */
122 AT91_REG PIOA_MDER; /* Multi-driver Enable Register */
123 AT91_REG PIOA_MDDR; /* Multi-driver Disable Register */
124 AT91_REG PIOA_MDSR; /* Multi-driver Status Register */
125 AT91_REG Reserved9[ 1 ]; /* */
126 AT91_REG PIOA_PPUDR; /* Pull-up Disable Register */
127 AT91_REG PIOA_PPUER; /* Pull-up Enable Register */
128 AT91_REG PIOA_PPUSR; /* Pull-up Status Register */
129 AT91_REG Reserved10[ 1 ]; /* */
130 AT91_REG PIOA_ASR; /* Select A Register */
131 AT91_REG PIOA_BSR; /* Select B Register */
132 AT91_REG PIOA_ABSR; /* AB Select Status Register */
133 AT91_REG Reserved11[ 9 ]; /* */
134 AT91_REG PIOA_OWER; /* Output Write Enable Register */
135 AT91_REG PIOA_OWDR; /* Output Write Disable Register */
136 AT91_REG PIOA_OWSR; /* Output Write Status Register */
137 AT91_REG Reserved12[ 85 ]; /* */
138 AT91_REG PIOB_PER; /* PIO Enable Register */
139 AT91_REG PIOB_PDR; /* PIO Disable Register */
140 AT91_REG PIOB_PSR; /* PIO Status Register */
141 AT91_REG Reserved13[ 1 ]; /* */
142 AT91_REG PIOB_OER; /* Output Enable Register */
143 AT91_REG PIOB_ODR; /* Output Disable Registerr */
144 AT91_REG PIOB_OSR; /* Output Status Register */
145 AT91_REG Reserved14[ 1 ]; /* */
146 AT91_REG PIOB_IFER; /* Input Filter Enable Register */
147 AT91_REG PIOB_IFDR; /* Input Filter Disable Register */
148 AT91_REG PIOB_IFSR; /* Input Filter Status Register */
149 AT91_REG Reserved15[ 1 ]; /* */
150 AT91_REG PIOB_SODR; /* Set Output Data Register */
151 AT91_REG PIOB_CODR; /* Clear Output Data Register */
152 AT91_REG PIOB_ODSR; /* Output Data Status Register */
153 AT91_REG PIOB_PDSR; /* Pin Data Status Register */
154 AT91_REG PIOB_IER; /* Interrupt Enable Register */
155 AT91_REG PIOB_IDR; /* Interrupt Disable Register */
156 AT91_REG PIOB_IMR; /* Interrupt Mask Register */
157 AT91_REG PIOB_ISR; /* Interrupt Status Register */
158 AT91_REG PIOB_MDER; /* Multi-driver Enable Register */
159 AT91_REG PIOB_MDDR; /* Multi-driver Disable Register */
160 AT91_REG PIOB_MDSR; /* Multi-driver Status Register */
161 AT91_REG Reserved16[ 1 ]; /* */
162 AT91_REG PIOB_PPUDR; /* Pull-up Disable Register */
163 AT91_REG PIOB_PPUER; /* Pull-up Enable Register */
164 AT91_REG PIOB_PPUSR; /* Pull-up Status Register */
165 AT91_REG Reserved17[ 1 ]; /* */
166 AT91_REG PIOB_ASR; /* Select A Register */
167 AT91_REG PIOB_BSR; /* Select B Register */
168 AT91_REG PIOB_ABSR; /* AB Select Status Register */
169 AT91_REG Reserved18[ 9 ]; /* */
170 AT91_REG PIOB_OWER; /* Output Write Enable Register */
171 AT91_REG PIOB_OWDR; /* Output Write Disable Register */
172 AT91_REG PIOB_OWSR; /* Output Write Status Register */
173 AT91_REG Reserved19[ 341 ]; /* */
174 AT91_REG PMC_SCER; /* System Clock Enable Register */
175 AT91_REG PMC_SCDR; /* System Clock Disable Register */
176 AT91_REG PMC_SCSR; /* System Clock Status Register */
177 AT91_REG Reserved20[ 1 ]; /* */
178 AT91_REG PMC_PCER; /* Peripheral Clock Enable Register */
179 AT91_REG PMC_PCDR; /* Peripheral Clock Disable Register */
180 AT91_REG PMC_PCSR; /* Peripheral Clock Status Register */
181 AT91_REG Reserved21[ 1 ]; /* */
182 AT91_REG PMC_MOR; /* Main Oscillator Register */
183 AT91_REG PMC_MCFR; /* Main Clock Frequency Register */
184 AT91_REG Reserved22[ 1 ]; /* */
185 AT91_REG PMC_PLLR; /* PLL Register */
186 AT91_REG PMC_MCKR; /* Master Clock Register */
187 AT91_REG Reserved23[ 3 ]; /* */
188 AT91_REG PMC_PCKR[ 4 ]; /* Programmable Clock Register */
189 AT91_REG Reserved24[ 4 ]; /* */
190 AT91_REG PMC_IER; /* Interrupt Enable Register */
191 AT91_REG PMC_IDR; /* Interrupt Disable Register */
192 AT91_REG PMC_SR; /* Status Register */
193 AT91_REG PMC_IMR; /* Interrupt Mask Register */
194 AT91_REG Reserved25[ 36 ]; /* */
195 AT91_REG RSTC_RCR; /* Reset Control Register */
196 AT91_REG RSTC_RSR; /* Reset Status Register */
197 AT91_REG RSTC_RMR; /* Reset Mode Register */
198 AT91_REG Reserved26[ 5 ]; /* */
199 AT91_REG RTTC_RTMR; /* Real-time Mode Register */
200 AT91_REG RTTC_RTAR; /* Real-time Alarm Register */
201 AT91_REG RTTC_RTVR; /* Real-time Value Register */
202 AT91_REG RTTC_RTSR; /* Real-time Status Register */
203 AT91_REG PITC_PIMR; /* Period Interval Mode Register */
204 AT91_REG PITC_PISR; /* Period Interval Status Register */
205 AT91_REG PITC_PIVR; /* Period Interval Value Register */
206 AT91_REG PITC_PIIR; /* Period Interval Image Register */
207 AT91_REG WDTC_WDCR; /* Watchdog Control Register */
208 AT91_REG WDTC_WDMR; /* Watchdog Mode Register */
209 AT91_REG WDTC_WDSR; /* Watchdog Status Register */
210 AT91_REG Reserved27[ 5 ]; /* */
211 AT91_REG VREG_MR; /* Voltage Regulator Mode Register */
212 } AT91S_SYS, * AT91PS_SYS;
215 /* ***************************************************************************** */
216 /* SOFTWARE API DEFINITION FOR Advanced Interrupt Controller */
217 /* ***************************************************************************** */
218 typedef struct _AT91S_AIC
220 AT91_REG AIC_SMR[ 32 ]; /* Source Mode Register */
221 AT91_REG AIC_SVR[ 32 ]; /* Source Vector Register */
222 AT91_REG AIC_IVR; /* IRQ Vector Register */
223 AT91_REG AIC_FVR; /* FIQ Vector Register */
224 AT91_REG AIC_ISR; /* Interrupt Status Register */
225 AT91_REG AIC_IPR; /* Interrupt Pending Register */
226 AT91_REG AIC_IMR; /* Interrupt Mask Register */
227 AT91_REG AIC_CISR; /* Core Interrupt Status Register */
228 AT91_REG Reserved0[ 2 ]; /* */
229 AT91_REG AIC_IECR; /* Interrupt Enable Command Register */
230 AT91_REG AIC_IDCR; /* Interrupt Disable Command Register */
231 AT91_REG AIC_ICCR; /* Interrupt Clear Command Register */
232 AT91_REG AIC_ISCR; /* Interrupt Set Command Register */
233 AT91_REG AIC_EOICR; /* End of Interrupt Command Register */
234 AT91_REG AIC_SPU; /* Spurious Vector Register */
235 AT91_REG AIC_DCR; /* Debug Control Register (Protect) */
236 AT91_REG Reserved1[ 1 ]; /* */
237 AT91_REG AIC_FFER; /* Fast Forcing Enable Register */
238 AT91_REG AIC_FFDR; /* Fast Forcing Disable Register */
239 AT91_REG AIC_FFSR; /* Fast Forcing Status Register */
240 } AT91S_AIC, * AT91PS_AIC;
242 /* -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- */
243 #define AT91C_AIC_PRIOR ( ( unsigned int ) 0x7 << 0 ) /* (AIC) Priority Level */
244 #define AT91C_AIC_PRIOR_LOWEST ( ( unsigned int ) 0x0 ) /* (AIC) Lowest priority level */
245 #define AT91C_AIC_PRIOR_HIGHEST ( ( unsigned int ) 0x7 ) /* (AIC) Highest priority level */
246 #define AT91C_AIC_SRCTYPE ( ( unsigned int ) 0x3 << 5 ) /* (AIC) Interrupt Source Type */
247 #define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL ( ( unsigned int ) 0x0 << 5 ) /* (AIC) Internal Sources Code Label High-level Sensitive */
248 #define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL ( ( unsigned int ) 0x0 << 5 ) /* (AIC) External Sources Code Label Low-level Sensitive */
249 #define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE ( ( unsigned int ) 0x1 << 5 ) /* (AIC) Internal Sources Code Label Positive Edge triggered */
250 #define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE ( ( unsigned int ) 0x1 << 5 ) /* (AIC) External Sources Code Label Negative Edge triggered */
251 #define AT91C_AIC_SRCTYPE_HIGH_LEVEL ( ( unsigned int ) 0x2 << 5 ) /* (AIC) Internal Or External Sources Code Label High-level Sensitive */
252 #define AT91C_AIC_SRCTYPE_POSITIVE_EDGE ( ( unsigned int ) 0x3 << 5 ) /* (AIC) Internal Or External Sources Code Label Positive Edge triggered */
253 /* -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- */
254 #define AT91C_AIC_NFIQ ( ( unsigned int ) 0x1 << 0 ) /* (AIC) NFIQ Status */
255 #define AT91C_AIC_NIRQ ( ( unsigned int ) 0x1 << 1 ) /* (AIC) NIRQ Status */
256 /* -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- */
257 #define AT91C_AIC_DCR_PROT ( ( unsigned int ) 0x1 << 0 ) /* (AIC) Protection Mode */
258 #define AT91C_AIC_DCR_GMSK ( ( unsigned int ) 0x1 << 1 ) /* (AIC) General Mask */
260 /* ***************************************************************************** */
261 /* SOFTWARE API DEFINITION FOR Peripheral DMA Controller */
262 /* ***************************************************************************** */
263 typedef struct _AT91S_PDC
265 AT91_REG PDC_RPR; /* Receive Pointer Register */
266 AT91_REG PDC_RCR; /* Receive Counter Register */
267 AT91_REG PDC_TPR; /* Transmit Pointer Register */
268 AT91_REG PDC_TCR; /* Transmit Counter Register */
269 AT91_REG PDC_RNPR; /* Receive Next Pointer Register */
270 AT91_REG PDC_RNCR; /* Receive Next Counter Register */
271 AT91_REG PDC_TNPR; /* Transmit Next Pointer Register */
272 AT91_REG PDC_TNCR; /* Transmit Next Counter Register */
273 AT91_REG PDC_PTCR; /* PDC Transfer Control Register */
274 AT91_REG PDC_PTSR; /* PDC Transfer Status Register */
275 } AT91S_PDC, * AT91PS_PDC;
277 /* -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- */
278 #define AT91C_PDC_RXTEN ( ( unsigned int ) 0x1 << 0 ) /* (PDC) Receiver Transfer Enable */
279 #define AT91C_PDC_RXTDIS ( ( unsigned int ) 0x1 << 1 ) /* (PDC) Receiver Transfer Disable */
280 #define AT91C_PDC_TXTEN ( ( unsigned int ) 0x1 << 8 ) /* (PDC) Transmitter Transfer Enable */
281 #define AT91C_PDC_TXTDIS ( ( unsigned int ) 0x1 << 9 ) /* (PDC) Transmitter Transfer Disable */
282 /* -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- */
284 /* ***************************************************************************** */
285 /* SOFTWARE API DEFINITION FOR Debug Unit */
286 /* ***************************************************************************** */
287 typedef struct _AT91S_DBGU
289 AT91_REG DBGU_CR; /* Control Register */
290 AT91_REG DBGU_MR; /* Mode Register */
291 AT91_REG DBGU_IER; /* Interrupt Enable Register */
292 AT91_REG DBGU_IDR; /* Interrupt Disable Register */
293 AT91_REG DBGU_IMR; /* Interrupt Mask Register */
294 AT91_REG DBGU_CSR; /* Channel Status Register */
295 AT91_REG DBGU_RHR; /* Receiver Holding Register */
296 AT91_REG DBGU_THR; /* Transmitter Holding Register */
297 AT91_REG DBGU_BRGR; /* Baud Rate Generator Register */
298 AT91_REG Reserved0[ 7 ]; /* */
299 AT91_REG DBGU_CIDR; /* Chip ID Register */
300 AT91_REG DBGU_EXID; /* Chip ID Extension Register */
301 AT91_REG DBGU_FNTR; /* Force NTRST Register */
302 AT91_REG Reserved1[ 45 ]; /* */
303 AT91_REG DBGU_RPR; /* Receive Pointer Register */
304 AT91_REG DBGU_RCR; /* Receive Counter Register */
305 AT91_REG DBGU_TPR; /* Transmit Pointer Register */
306 AT91_REG DBGU_TCR; /* Transmit Counter Register */
307 AT91_REG DBGU_RNPR; /* Receive Next Pointer Register */
308 AT91_REG DBGU_RNCR; /* Receive Next Counter Register */
309 AT91_REG DBGU_TNPR; /* Transmit Next Pointer Register */
310 AT91_REG DBGU_TNCR; /* Transmit Next Counter Register */
311 AT91_REG DBGU_PTCR; /* PDC Transfer Control Register */
312 AT91_REG DBGU_PTSR; /* PDC Transfer Status Register */
313 } AT91S_DBGU, * AT91PS_DBGU;
315 /* -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- */
316 #define AT91C_US_RSTRX ( ( unsigned int ) 0x1 << 2 ) /* (DBGU) Reset Receiver */
317 #define AT91C_US_RSTTX ( ( unsigned int ) 0x1 << 3 ) /* (DBGU) Reset Transmitter */
318 #define AT91C_US_RXEN ( ( unsigned int ) 0x1 << 4 ) /* (DBGU) Receiver Enable */
319 #define AT91C_US_RXDIS ( ( unsigned int ) 0x1 << 5 ) /* (DBGU) Receiver Disable */
320 #define AT91C_US_TXEN ( ( unsigned int ) 0x1 << 6 ) /* (DBGU) Transmitter Enable */
321 #define AT91C_US_TXDIS ( ( unsigned int ) 0x1 << 7 ) /* (DBGU) Transmitter Disable */
322 #define AT91C_US_RSTSTA ( ( unsigned int ) 0x1 << 8 ) /* (DBGU) Reset Status Bits */
323 /* -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- */
324 #define AT91C_US_PAR ( ( unsigned int ) 0x7 << 9 ) /* (DBGU) Parity type */
325 #define AT91C_US_PAR_EVEN ( ( unsigned int ) 0x0 << 9 ) /* (DBGU) Even Parity */
326 #define AT91C_US_PAR_ODD ( ( unsigned int ) 0x1 << 9 ) /* (DBGU) Odd Parity */
327 #define AT91C_US_PAR_SPACE ( ( unsigned int ) 0x2 << 9 ) /* (DBGU) Parity forced to 0 (Space) */
328 #define AT91C_US_PAR_MARK ( ( unsigned int ) 0x3 << 9 ) /* (DBGU) Parity forced to 1 (Mark) */
329 #define AT91C_US_PAR_NONE ( ( unsigned int ) 0x4 << 9 ) /* (DBGU) No Parity */
330 #define AT91C_US_PAR_MULTI_DROP ( ( unsigned int ) 0x6 << 9 ) /* (DBGU) Multi-drop mode */
331 #define AT91C_US_CHMODE ( ( unsigned int ) 0x3 << 14 ) /* (DBGU) Channel Mode */
332 #define AT91C_US_CHMODE_NORMAL ( ( unsigned int ) 0x0 << 14 ) /* (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. */
333 #define AT91C_US_CHMODE_AUTO ( ( unsigned int ) 0x1 << 14 ) /* (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. */
334 #define AT91C_US_CHMODE_LOCAL ( ( unsigned int ) 0x2 << 14 ) /* (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. */
335 #define AT91C_US_CHMODE_REMOTE ( ( unsigned int ) 0x3 << 14 ) /* (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. */
336 /* -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- */
337 #define AT91C_US_RXRDY ( ( unsigned int ) 0x1 << 0 ) /* (DBGU) RXRDY Interrupt */
338 #define AT91C_US_TXRDY ( ( unsigned int ) 0x1 << 1 ) /* (DBGU) TXRDY Interrupt */
339 #define AT91C_US_ENDRX ( ( unsigned int ) 0x1 << 3 ) /* (DBGU) End of Receive Transfer Interrupt */
340 #define AT91C_US_ENDTX ( ( unsigned int ) 0x1 << 4 ) /* (DBGU) End of Transmit Interrupt */
341 #define AT91C_US_OVRE ( ( unsigned int ) 0x1 << 5 ) /* (DBGU) Overrun Interrupt */
342 #define AT91C_US_FRAME ( ( unsigned int ) 0x1 << 6 ) /* (DBGU) Framing Error Interrupt */
343 #define AT91C_US_PARE ( ( unsigned int ) 0x1 << 7 ) /* (DBGU) Parity Error Interrupt */
344 #define AT91C_US_TXEMPTY ( ( unsigned int ) 0x1 << 9 ) /* (DBGU) TXEMPTY Interrupt */
345 #define AT91C_US_TXBUFE ( ( unsigned int ) 0x1 << 11 ) /* (DBGU) TXBUFE Interrupt */
346 #define AT91C_US_RXBUFF ( ( unsigned int ) 0x1 << 12 ) /* (DBGU) RXBUFF Interrupt */
347 #define AT91C_US_COMM_TX ( ( unsigned int ) 0x1 << 30 ) /* (DBGU) COMM_TX Interrupt */
348 #define AT91C_US_COMM_RX ( ( unsigned int ) 0x1 << 31 ) /* (DBGU) COMM_RX Interrupt */
349 /* -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- */
350 /* -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- */
351 /* -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- */
352 /* -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- */
353 #define AT91C_US_FORCE_NTRST ( ( unsigned int ) 0x1 << 0 ) /* (DBGU) Force NTRST in JTAG */
355 /* ***************************************************************************** */
356 /* SOFTWARE API DEFINITION FOR Parallel Input Output Controller */
357 /* ***************************************************************************** */
358 typedef struct _AT91S_PIO
360 AT91_REG PIO_PER; /* PIO Enable Register */
361 AT91_REG PIO_PDR; /* PIO Disable Register */
362 AT91_REG PIO_PSR; /* PIO Status Register */
363 AT91_REG Reserved0[ 1 ]; /* */
364 AT91_REG PIO_OER; /* Output Enable Register */
365 AT91_REG PIO_ODR; /* Output Disable Registerr */
366 AT91_REG PIO_OSR; /* Output Status Register */
367 AT91_REG Reserved1[ 1 ]; /* */
368 AT91_REG PIO_IFER; /* Input Filter Enable Register */
369 AT91_REG PIO_IFDR; /* Input Filter Disable Register */
370 AT91_REG PIO_IFSR; /* Input Filter Status Register */
371 AT91_REG Reserved2[ 1 ]; /* */
372 AT91_REG PIO_SODR; /* Set Output Data Register */
373 AT91_REG PIO_CODR; /* Clear Output Data Register */
374 AT91_REG PIO_ODSR; /* Output Data Status Register */
375 AT91_REG PIO_PDSR; /* Pin Data Status Register */
376 AT91_REG PIO_IER; /* Interrupt Enable Register */
377 AT91_REG PIO_IDR; /* Interrupt Disable Register */
378 AT91_REG PIO_IMR; /* Interrupt Mask Register */
379 AT91_REG PIO_ISR; /* Interrupt Status Register */
380 AT91_REG PIO_MDER; /* Multi-driver Enable Register */
381 AT91_REG PIO_MDDR; /* Multi-driver Disable Register */
382 AT91_REG PIO_MDSR; /* Multi-driver Status Register */
383 AT91_REG Reserved3[ 1 ]; /* */
384 AT91_REG PIO_PPUDR; /* Pull-up Disable Register */
385 AT91_REG PIO_PPUER; /* Pull-up Enable Register */
386 AT91_REG PIO_PPUSR; /* Pull-up Status Register */
387 AT91_REG Reserved4[ 1 ]; /* */
388 AT91_REG PIO_ASR; /* Select A Register */
389 AT91_REG PIO_BSR; /* Select B Register */
390 AT91_REG PIO_ABSR; /* AB Select Status Register */
391 AT91_REG Reserved5[ 9 ]; /* */
392 AT91_REG PIO_OWER; /* Output Write Enable Register */
393 AT91_REG PIO_OWDR; /* Output Write Disable Register */
394 AT91_REG PIO_OWSR; /* Output Write Status Register */
395 } AT91S_PIO, * AT91PS_PIO;
398 /* ***************************************************************************** */
399 /* SOFTWARE API DEFINITION FOR Clock Generator Controller */
400 /* ***************************************************************************** */
401 typedef struct _AT91S_CKGR
403 AT91_REG CKGR_MOR; /* Main Oscillator Register */
404 AT91_REG CKGR_MCFR; /* Main Clock Frequency Register */
405 AT91_REG Reserved0[ 1 ]; /* */
406 AT91_REG CKGR_PLLR; /* PLL Register */
407 } AT91S_CKGR, * AT91PS_CKGR;
409 /* -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- */
410 #define AT91C_CKGR_MOSCEN ( ( unsigned int ) 0x1 << 0 ) /* (CKGR) Main Oscillator Enable */
411 #define AT91C_CKGR_OSCBYPASS ( ( unsigned int ) 0x1 << 1 ) /* (CKGR) Main Oscillator Bypass */
412 #define AT91C_CKGR_OSCOUNT ( ( unsigned int ) 0xFF << 8 ) /* (CKGR) Main Oscillator Start-up Time */
413 /* -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- */
414 #define AT91C_CKGR_MAINF ( ( unsigned int ) 0xFFFF << 0 ) /* (CKGR) Main Clock Frequency */
415 #define AT91C_CKGR_MAINRDY ( ( unsigned int ) 0x1 << 16 ) /* (CKGR) Main Clock Ready */
416 /* -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- */
417 #define AT91C_CKGR_DIV ( ( unsigned int ) 0xFF << 0 ) /* (CKGR) Divider Selected */
418 #define AT91C_CKGR_DIV_0 ( ( unsigned int ) 0x0 ) /* (CKGR) Divider output is 0 */
419 #define AT91C_CKGR_DIV_BYPASS ( ( unsigned int ) 0x1 ) /* (CKGR) Divider is bypassed */
420 #define AT91C_CKGR_PLLCOUNT ( ( unsigned int ) 0x3F << 8 ) /* (CKGR) PLL Counter */
421 #define AT91C_CKGR_OUT ( ( unsigned int ) 0x3 << 14 ) /* (CKGR) PLL Output Frequency Range */
422 #define AT91C_CKGR_OUT_0 ( ( unsigned int ) 0x0 << 14 ) /* (CKGR) Please refer to the PLL datasheet */
423 #define AT91C_CKGR_OUT_1 ( ( unsigned int ) 0x1 << 14 ) /* (CKGR) Please refer to the PLL datasheet */
424 #define AT91C_CKGR_OUT_2 ( ( unsigned int ) 0x2 << 14 ) /* (CKGR) Please refer to the PLL datasheet */
425 #define AT91C_CKGR_OUT_3 ( ( unsigned int ) 0x3 << 14 ) /* (CKGR) Please refer to the PLL datasheet */
426 #define AT91C_CKGR_MUL ( ( unsigned int ) 0x7FF << 16 ) /* (CKGR) PLL Multiplier */
427 #define AT91C_CKGR_USBDIV ( ( unsigned int ) 0x3 << 28 ) /* (CKGR) Divider for USB Clocks */
428 #define AT91C_CKGR_USBDIV_0 ( ( unsigned int ) 0x0 << 28 ) /* (CKGR) Divider output is PLL clock output */
429 #define AT91C_CKGR_USBDIV_1 ( ( unsigned int ) 0x1 << 28 ) /* (CKGR) Divider output is PLL clock output divided by 2 */
430 #define AT91C_CKGR_USBDIV_2 ( ( unsigned int ) 0x2 << 28 ) /* (CKGR) Divider output is PLL clock output divided by 4 */
432 /* ***************************************************************************** */
433 /* SOFTWARE API DEFINITION FOR Power Management Controller */
434 /* ***************************************************************************** */
435 typedef struct _AT91S_PMC
437 AT91_REG PMC_SCER; /* System Clock Enable Register */
438 AT91_REG PMC_SCDR; /* System Clock Disable Register */
439 AT91_REG PMC_SCSR; /* System Clock Status Register */
440 AT91_REG Reserved0[ 1 ]; /* */
441 AT91_REG PMC_PCER; /* Peripheral Clock Enable Register */
442 AT91_REG PMC_PCDR; /* Peripheral Clock Disable Register */
443 AT91_REG PMC_PCSR; /* Peripheral Clock Status Register */
444 AT91_REG Reserved1[ 1 ]; /* */
445 AT91_REG PMC_MOR; /* Main Oscillator Register */
446 AT91_REG PMC_MCFR; /* Main Clock Frequency Register */
447 AT91_REG Reserved2[ 1 ]; /* */
448 AT91_REG PMC_PLLR; /* PLL Register */
449 AT91_REG PMC_MCKR; /* Master Clock Register */
450 AT91_REG Reserved3[ 3 ]; /* */
451 AT91_REG PMC_PCKR[ 4 ]; /* Programmable Clock Register */
452 AT91_REG Reserved4[ 4 ]; /* */
453 AT91_REG PMC_IER; /* Interrupt Enable Register */
454 AT91_REG PMC_IDR; /* Interrupt Disable Register */
455 AT91_REG PMC_SR; /* Status Register */
456 AT91_REG PMC_IMR; /* Interrupt Mask Register */
457 } AT91S_PMC, * AT91PS_PMC;
459 /* -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- */
460 #define AT91C_PMC_PCK ( ( unsigned int ) 0x1 << 0 ) /* (PMC) Processor Clock */
461 #define AT91C_PMC_UDP ( ( unsigned int ) 0x1 << 7 ) /* (PMC) USB Device Port Clock */
462 #define AT91C_PMC_PCK0 ( ( unsigned int ) 0x1 << 8 ) /* (PMC) Programmable Clock Output */
463 #define AT91C_PMC_PCK1 ( ( unsigned int ) 0x1 << 9 ) /* (PMC) Programmable Clock Output */
464 #define AT91C_PMC_PCK2 ( ( unsigned int ) 0x1 << 10 ) /* (PMC) Programmable Clock Output */
465 #define AT91C_PMC_PCK3 ( ( unsigned int ) 0x1 << 11 ) /* (PMC) Programmable Clock Output */
466 /* -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- */
467 /* -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- */
468 /* -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- */
469 /* -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- */
470 /* -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- */
471 /* -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- */
472 #define AT91C_PMC_CSS ( ( unsigned int ) 0x3 << 0 ) /* (PMC) Programmable Clock Selection */
473 #define AT91C_PMC_CSS_SLOW_CLK ( ( unsigned int ) 0x0 ) /* (PMC) Slow Clock is selected */
474 #define AT91C_PMC_CSS_MAIN_CLK ( ( unsigned int ) 0x1 ) /* (PMC) Main Clock is selected */
475 #define AT91C_PMC_CSS_PLL_CLK ( ( unsigned int ) 0x3 ) /* (PMC) Clock from PLL is selected */
476 #define AT91C_PMC_PRES ( ( unsigned int ) 0x7 << 2 ) /* (PMC) Programmable Clock Prescaler */
477 #define AT91C_PMC_PRES_CLK ( ( unsigned int ) 0x0 << 2 ) /* (PMC) Selected clock */
478 #define AT91C_PMC_PRES_CLK_2 ( ( unsigned int ) 0x1 << 2 ) /* (PMC) Selected clock divided by 2 */
479 #define AT91C_PMC_PRES_CLK_4 ( ( unsigned int ) 0x2 << 2 ) /* (PMC) Selected clock divided by 4 */
480 #define AT91C_PMC_PRES_CLK_8 ( ( unsigned int ) 0x3 << 2 ) /* (PMC) Selected clock divided by 8 */
481 #define AT91C_PMC_PRES_CLK_16 ( ( unsigned int ) 0x4 << 2 ) /* (PMC) Selected clock divided by 16 */
482 #define AT91C_PMC_PRES_CLK_32 ( ( unsigned int ) 0x5 << 2 ) /* (PMC) Selected clock divided by 32 */
483 #define AT91C_PMC_PRES_CLK_64 ( ( unsigned int ) 0x6 << 2 ) /* (PMC) Selected clock divided by 64 */
484 /* -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- */
485 /* -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- */
486 #define AT91C_PMC_MOSCS ( ( unsigned int ) 0x1 << 0 ) /* (PMC) MOSC Status/Enable/Disable/Mask */
487 #define AT91C_PMC_LOCK ( ( unsigned int ) 0x1 << 2 ) /* (PMC) PLL Status/Enable/Disable/Mask */
488 #define AT91C_PMC_MCKRDY ( ( unsigned int ) 0x1 << 3 ) /* (PMC) MCK_RDY Status/Enable/Disable/Mask */
489 #define AT91C_PMC_PCK0RDY ( ( unsigned int ) 0x1 << 8 ) /* (PMC) PCK0_RDY Status/Enable/Disable/Mask */
490 #define AT91C_PMC_PCK1RDY ( ( unsigned int ) 0x1 << 9 ) /* (PMC) PCK1_RDY Status/Enable/Disable/Mask */
491 #define AT91C_PMC_PCK2RDY ( ( unsigned int ) 0x1 << 10 ) /* (PMC) PCK2_RDY Status/Enable/Disable/Mask */
492 #define AT91C_PMC_PCK3RDY ( ( unsigned int ) 0x1 << 11 ) /* (PMC) PCK3_RDY Status/Enable/Disable/Mask */
493 /* -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- */
494 /* -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- */
495 /* -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- */
497 /* ***************************************************************************** */
498 /* SOFTWARE API DEFINITION FOR Reset Controller Interface */
499 /* ***************************************************************************** */
500 typedef struct _AT91S_RSTC
502 AT91_REG RSTC_RCR; /* Reset Control Register */
503 AT91_REG RSTC_RSR; /* Reset Status Register */
504 AT91_REG RSTC_RMR; /* Reset Mode Register */
505 } AT91S_RSTC, * AT91PS_RSTC;
507 /* -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- */
508 #define AT91C_RSTC_PROCRST ( ( unsigned int ) 0x1 << 0 ) /* (RSTC) Processor Reset */
509 #define AT91C_RSTC_PERRST ( ( unsigned int ) 0x1 << 2 ) /* (RSTC) Peripheral Reset */
510 #define AT91C_RSTC_EXTRST ( ( unsigned int ) 0x1 << 3 ) /* (RSTC) External Reset */
511 #define AT91C_RSTC_KEY ( ( unsigned int ) 0xFF << 24 ) /* (RSTC) Password */
512 /* -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- */
513 #define AT91C_RSTC_URSTS ( ( unsigned int ) 0x1 << 0 ) /* (RSTC) User Reset Status */
514 #define AT91C_RSTC_BODSTS ( ( unsigned int ) 0x1 << 1 ) /* (RSTC) Brownout Detection Status */
515 #define AT91C_RSTC_RSTTYP ( ( unsigned int ) 0x7 << 8 ) /* (RSTC) Reset Type */
516 #define AT91C_RSTC_RSTTYP_POWERUP ( ( unsigned int ) 0x0 << 8 ) /* (RSTC) Power-up Reset. VDDCORE rising. */
517 #define AT91C_RSTC_RSTTYP_WAKEUP ( ( unsigned int ) 0x1 << 8 ) /* (RSTC) WakeUp Reset. VDDCORE rising. */
518 #define AT91C_RSTC_RSTTYP_WATCHDOG ( ( unsigned int ) 0x2 << 8 ) /* (RSTC) Watchdog Reset. Watchdog overflow occurred. */
519 #define AT91C_RSTC_RSTTYP_SOFTWARE ( ( unsigned int ) 0x3 << 8 ) /* (RSTC) Software Reset. Processor reset required by the software. */
520 #define AT91C_RSTC_RSTTYP_USER ( ( unsigned int ) 0x4 << 8 ) /* (RSTC) User Reset. NRST pin detected low. */
521 #define AT91C_RSTC_RSTTYP_BROWNOUT ( ( unsigned int ) 0x5 << 8 ) /* (RSTC) Brownout Reset occurred. */
522 #define AT91C_RSTC_NRSTL ( ( unsigned int ) 0x1 << 16 ) /* (RSTC) NRST pin level */
523 #define AT91C_RSTC_SRCMP ( ( unsigned int ) 0x1 << 17 ) /* (RSTC) Software Reset Command in Progress. */
524 /* -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- */
525 #define AT91C_RSTC_URSTEN ( ( unsigned int ) 0x1 << 0 ) /* (RSTC) User Reset Enable */
526 #define AT91C_RSTC_URSTIEN ( ( unsigned int ) 0x1 << 4 ) /* (RSTC) User Reset Interrupt Enable */
527 #define AT91C_RSTC_ERSTL ( ( unsigned int ) 0xF << 8 ) /* (RSTC) User Reset Enable */
528 #define AT91C_RSTC_BODIEN ( ( unsigned int ) 0x1 << 16 ) /* (RSTC) Brownout Detection Interrupt Enable */
530 /* ***************************************************************************** */
531 /* SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface */
532 /* ***************************************************************************** */
533 typedef struct _AT91S_RTTC
535 AT91_REG RTTC_RTMR; /* Real-time Mode Register */
536 AT91_REG RTTC_RTAR; /* Real-time Alarm Register */
537 AT91_REG RTTC_RTVR; /* Real-time Value Register */
538 AT91_REG RTTC_RTSR; /* Real-time Status Register */
539 } AT91S_RTTC, * AT91PS_RTTC;
541 /* -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- */
542 #define AT91C_RTTC_RTPRES ( ( unsigned int ) 0xFFFF << 0 ) /* (RTTC) Real-time Timer Prescaler Value */
543 #define AT91C_RTTC_ALMIEN ( ( unsigned int ) 0x1 << 16 ) /* (RTTC) Alarm Interrupt Enable */
544 #define AT91C_RTTC_RTTINCIEN ( ( unsigned int ) 0x1 << 17 ) /* (RTTC) Real Time Timer Increment Interrupt Enable */
545 #define AT91C_RTTC_RTTRST ( ( unsigned int ) 0x1 << 18 ) /* (RTTC) Real Time Timer Restart */
546 /* -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- */
547 #define AT91C_RTTC_ALMV ( ( unsigned int ) 0x0 << 0 ) /* (RTTC) Alarm Value */
548 /* -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- */
549 #define AT91C_RTTC_CRTV ( ( unsigned int ) 0x0 << 0 ) /* (RTTC) Current Real-time Value */
550 /* -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- */
551 #define AT91C_RTTC_ALMS ( ( unsigned int ) 0x1 << 0 ) /* (RTTC) Real-time Alarm Status */
552 #define AT91C_RTTC_RTTINC ( ( unsigned int ) 0x1 << 1 ) /* (RTTC) Real-time Timer Increment */
554 /* ***************************************************************************** */
555 /* SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface */
556 /* ***************************************************************************** */
557 typedef struct _AT91S_PITC
559 AT91_REG PITC_PIMR; /* Period Interval Mode Register */
560 AT91_REG PITC_PISR; /* Period Interval Status Register */
561 AT91_REG PITC_PIVR; /* Period Interval Value Register */
562 AT91_REG PITC_PIIR; /* Period Interval Image Register */
563 } AT91S_PITC, * AT91PS_PITC;
565 /* -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- */
566 #define AT91C_PITC_PIV ( ( unsigned int ) 0xFFFFF << 0 ) /* (PITC) Periodic Interval Value */
567 #define AT91C_PITC_PITEN ( ( unsigned int ) 0x1 << 24 ) /* (PITC) Periodic Interval Timer Enabled */
568 #define AT91C_PITC_PITIEN ( ( unsigned int ) 0x1 << 25 ) /* (PITC) Periodic Interval Timer Interrupt Enable */
569 /* -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- */
570 #define AT91C_PITC_PITS ( ( unsigned int ) 0x1 << 0 ) /* (PITC) Periodic Interval Timer Status */
571 /* -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- */
572 #define AT91C_PITC_CPIV ( ( unsigned int ) 0xFFFFF << 0 ) /* (PITC) Current Periodic Interval Value */
573 #define AT91C_PITC_PICNT ( ( unsigned int ) 0xFFF << 20 ) /* (PITC) Periodic Interval Counter */
574 /* -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- */
576 /* ***************************************************************************** */
577 /* SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface */
578 /* ***************************************************************************** */
579 typedef struct _AT91S_WDTC
581 AT91_REG WDTC_WDCR; /* Watchdog Control Register */
582 AT91_REG WDTC_WDMR; /* Watchdog Mode Register */
583 AT91_REG WDTC_WDSR; /* Watchdog Status Register */
584 } AT91S_WDTC, * AT91PS_WDTC;
586 /* -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- */
587 #define AT91C_WDTC_WDRSTT ( ( unsigned int ) 0x1 << 0 ) /* (WDTC) Watchdog Restart */
588 #define AT91C_WDTC_KEY ( ( unsigned int ) 0xFF << 24 ) /* (WDTC) Watchdog KEY Password */
589 /* -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- */
590 #define AT91C_WDTC_WDV ( ( unsigned int ) 0xFFF << 0 ) /* (WDTC) Watchdog Timer Restart */
591 #define AT91C_WDTC_WDFIEN ( ( unsigned int ) 0x1 << 12 ) /* (WDTC) Watchdog Fault Interrupt Enable */
592 #define AT91C_WDTC_WDRSTEN ( ( unsigned int ) 0x1 << 13 ) /* (WDTC) Watchdog Reset Enable */
593 #define AT91C_WDTC_WDRPROC ( ( unsigned int ) 0x1 << 14 ) /* (WDTC) Watchdog Timer Restart */
594 #define AT91C_WDTC_WDDIS ( ( unsigned int ) 0x1 << 15 ) /* (WDTC) Watchdog Disable */
595 #define AT91C_WDTC_WDD ( ( unsigned int ) 0xFFF << 16 ) /* (WDTC) Watchdog Delta Value */
596 #define AT91C_WDTC_WDDBGHLT ( ( unsigned int ) 0x1 << 28 ) /* (WDTC) Watchdog Debug Halt */
597 #define AT91C_WDTC_WDIDLEHLT ( ( unsigned int ) 0x1 << 29 ) /* (WDTC) Watchdog Idle Halt */
598 /* -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- */
599 #define AT91C_WDTC_WDUNF ( ( unsigned int ) 0x1 << 0 ) /* (WDTC) Watchdog Underflow */
600 #define AT91C_WDTC_WDERR ( ( unsigned int ) 0x1 << 1 ) /* (WDTC) Watchdog Error */
602 /* ***************************************************************************** */
603 /* SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface */
604 /* ***************************************************************************** */
605 typedef struct _AT91S_VREG
607 AT91_REG VREG_MR; /* Voltage Regulator Mode Register */
608 } AT91S_VREG, * AT91PS_VREG;
610 /* -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- */
611 #define AT91C_VREG_PSTDBY ( ( unsigned int ) 0x1 << 0 ) /* (VREG) Voltage Regulator Power Standby Mode */
613 /* ***************************************************************************** */
614 /* SOFTWARE API DEFINITION FOR Memory Controller Interface */
615 /* ***************************************************************************** */
616 typedef struct _AT91S_MC
618 AT91_REG MC_RCR; /* MC Remap Control Register */
619 AT91_REG MC_ASR; /* MC Abort Status Register */
620 AT91_REG MC_AASR; /* MC Abort Address Status Register */
621 AT91_REG Reserved0[ 21 ]; /* */
622 AT91_REG MC_FMR; /* MC Flash Mode Register */
623 AT91_REG MC_FCR; /* MC Flash Command Register */
624 AT91_REG MC_FSR; /* MC Flash Status Register */
625 } AT91S_MC, * AT91PS_MC;
627 /* -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- */
628 #define AT91C_MC_RCB ( ( unsigned int ) 0x1 << 0 ) /* (MC) Remap Command Bit */
629 /* -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- */
630 #define AT91C_MC_UNDADD ( ( unsigned int ) 0x1 << 0 ) /* (MC) Undefined Address Abort Status */
631 #define AT91C_MC_MISADD ( ( unsigned int ) 0x1 << 1 ) /* (MC) Misaligned Address Abort Status */
632 #define AT91C_MC_ABTSZ ( ( unsigned int ) 0x3 << 8 ) /* (MC) Abort Size Status */
633 #define AT91C_MC_ABTSZ_BYTE ( ( unsigned int ) 0x0 << 8 ) /* (MC) Byte */
634 #define AT91C_MC_ABTSZ_HWORD ( ( unsigned int ) 0x1 << 8 ) /* (MC) Half-word */
635 #define AT91C_MC_ABTSZ_WORD ( ( unsigned int ) 0x2 << 8 ) /* (MC) Word */
636 #define AT91C_MC_ABTTYP ( ( unsigned int ) 0x3 << 10 ) /* (MC) Abort Type Status */
637 #define AT91C_MC_ABTTYP_DATAR ( ( unsigned int ) 0x0 << 10 ) /* (MC) Data Read */
638 #define AT91C_MC_ABTTYP_DATAW ( ( unsigned int ) 0x1 << 10 ) /* (MC) Data Write */
639 #define AT91C_MC_ABTTYP_FETCH ( ( unsigned int ) 0x2 << 10 ) /* (MC) Code Fetch */
640 #define AT91C_MC_MST0 ( ( unsigned int ) 0x1 << 16 ) /* (MC) Master 0 Abort Source */
641 #define AT91C_MC_MST1 ( ( unsigned int ) 0x1 << 17 ) /* (MC) Master 1 Abort Source */
642 #define AT91C_MC_SVMST0 ( ( unsigned int ) 0x1 << 24 ) /* (MC) Saved Master 0 Abort Source */
643 #define AT91C_MC_SVMST1 ( ( unsigned int ) 0x1 << 25 ) /* (MC) Saved Master 1 Abort Source */
644 /* -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- */
645 #define AT91C_MC_FRDY ( ( unsigned int ) 0x1 << 0 ) /* (MC) Flash Ready */
646 #define AT91C_MC_LOCKE ( ( unsigned int ) 0x1 << 2 ) /* (MC) Lock Error */
647 #define AT91C_MC_PROGE ( ( unsigned int ) 0x1 << 3 ) /* (MC) Programming Error */
648 #define AT91C_MC_NEBP ( ( unsigned int ) 0x1 << 7 ) /* (MC) No Erase Before Programming */
649 #define AT91C_MC_FWS ( ( unsigned int ) 0x3 << 8 ) /* (MC) Flash Wait State */
650 #define AT91C_MC_FWS_0FWS ( ( unsigned int ) 0x0 << 8 ) /* (MC) 1 cycle for Read, 2 for Write operations */
651 #define AT91C_MC_FWS_1FWS ( ( unsigned int ) 0x1 << 8 ) /* (MC) 2 cycles for Read, 3 for Write operations */
652 #define AT91C_MC_FWS_2FWS ( ( unsigned int ) 0x2 << 8 ) /* (MC) 3 cycles for Read, 4 for Write operations */
653 #define AT91C_MC_FWS_3FWS ( ( unsigned int ) 0x3 << 8 ) /* (MC) 4 cycles for Read, 4 for Write operations */
654 #define AT91C_MC_FMCN ( ( unsigned int ) 0xFF << 16 ) /* (MC) Flash Microsecond Cycle Number */
655 /* -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- */
656 #define AT91C_MC_FCMD ( ( unsigned int ) 0xF << 0 ) /* (MC) Flash Command */
657 #define AT91C_MC_FCMD_START_PROG ( ( unsigned int ) 0x1 ) /* (MC) Starts the programming of th epage specified by PAGEN. */
658 #define AT91C_MC_FCMD_LOCK ( ( unsigned int ) 0x2 ) /* (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. */
659 #define AT91C_MC_FCMD_PROG_AND_LOCK ( ( unsigned int ) 0x3 ) /* (MC) The lock sequence automatically happens after the programming sequence is completed. */
660 #define AT91C_MC_FCMD_UNLOCK ( ( unsigned int ) 0x4 ) /* (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. */
661 #define AT91C_MC_FCMD_ERASE_ALL ( ( unsigned int ) 0x8 ) /* (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. */
662 #define AT91C_MC_FCMD_SET_GP_NVM ( ( unsigned int ) 0xB ) /* (MC) Set General Purpose NVM bits. */
663 #define AT91C_MC_FCMD_CLR_GP_NVM ( ( unsigned int ) 0xD ) /* (MC) Clear General Purpose NVM bits. */
664 #define AT91C_MC_FCMD_SET_SECURITY ( ( unsigned int ) 0xF ) /* (MC) Set Security Bit. */
665 #define AT91C_MC_PAGEN ( ( unsigned int ) 0x3FF << 8 ) /* (MC) Page Number */
666 #define AT91C_MC_KEY ( ( unsigned int ) 0xFF << 24 ) /* (MC) Writing Protect Key */
667 /* -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- */
668 #define AT91C_MC_SECURITY ( ( unsigned int ) 0x1 << 4 ) /* (MC) Security Bit Status */
669 #define AT91C_MC_GPNVM0 ( ( unsigned int ) 0x1 << 8 ) /* (MC) Sector 0 Lock Status */
670 #define AT91C_MC_GPNVM1 ( ( unsigned int ) 0x1 << 9 ) /* (MC) Sector 1 Lock Status */
671 #define AT91C_MC_GPNVM2 ( ( unsigned int ) 0x1 << 10 ) /* (MC) Sector 2 Lock Status */
672 #define AT91C_MC_GPNVM3 ( ( unsigned int ) 0x1 << 11 ) /* (MC) Sector 3 Lock Status */
673 #define AT91C_MC_GPNVM4 ( ( unsigned int ) 0x1 << 12 ) /* (MC) Sector 4 Lock Status */
674 #define AT91C_MC_GPNVM5 ( ( unsigned int ) 0x1 << 13 ) /* (MC) Sector 5 Lock Status */
675 #define AT91C_MC_GPNVM6 ( ( unsigned int ) 0x1 << 14 ) /* (MC) Sector 6 Lock Status */
676 #define AT91C_MC_GPNVM7 ( ( unsigned int ) 0x1 << 15 ) /* (MC) Sector 7 Lock Status */
677 #define AT91C_MC_LOCKS0 ( ( unsigned int ) 0x1 << 16 ) /* (MC) Sector 0 Lock Status */
678 #define AT91C_MC_LOCKS1 ( ( unsigned int ) 0x1 << 17 ) /* (MC) Sector 1 Lock Status */
679 #define AT91C_MC_LOCKS2 ( ( unsigned int ) 0x1 << 18 ) /* (MC) Sector 2 Lock Status */
680 #define AT91C_MC_LOCKS3 ( ( unsigned int ) 0x1 << 19 ) /* (MC) Sector 3 Lock Status */
681 #define AT91C_MC_LOCKS4 ( ( unsigned int ) 0x1 << 20 ) /* (MC) Sector 4 Lock Status */
682 #define AT91C_MC_LOCKS5 ( ( unsigned int ) 0x1 << 21 ) /* (MC) Sector 5 Lock Status */
683 #define AT91C_MC_LOCKS6 ( ( unsigned int ) 0x1 << 22 ) /* (MC) Sector 6 Lock Status */
684 #define AT91C_MC_LOCKS7 ( ( unsigned int ) 0x1 << 23 ) /* (MC) Sector 7 Lock Status */
685 #define AT91C_MC_LOCKS8 ( ( unsigned int ) 0x1 << 24 ) /* (MC) Sector 8 Lock Status */
686 #define AT91C_MC_LOCKS9 ( ( unsigned int ) 0x1 << 25 ) /* (MC) Sector 9 Lock Status */
687 #define AT91C_MC_LOCKS10 ( ( unsigned int ) 0x1 << 26 ) /* (MC) Sector 10 Lock Status */
688 #define AT91C_MC_LOCKS11 ( ( unsigned int ) 0x1 << 27 ) /* (MC) Sector 11 Lock Status */
689 #define AT91C_MC_LOCKS12 ( ( unsigned int ) 0x1 << 28 ) /* (MC) Sector 12 Lock Status */
690 #define AT91C_MC_LOCKS13 ( ( unsigned int ) 0x1 << 29 ) /* (MC) Sector 13 Lock Status */
691 #define AT91C_MC_LOCKS14 ( ( unsigned int ) 0x1 << 30 ) /* (MC) Sector 14 Lock Status */
692 #define AT91C_MC_LOCKS15 ( ( unsigned int ) 0x1 << 31 ) /* (MC) Sector 15 Lock Status */
694 /* ***************************************************************************** */
695 /* SOFTWARE API DEFINITION FOR Serial Parallel Interface */
696 /* ***************************************************************************** */
697 typedef struct _AT91S_SPI
699 AT91_REG SPI_CR; /* Control Register */
700 AT91_REG SPI_MR; /* Mode Register */
701 AT91_REG SPI_RDR; /* Receive Data Register */
702 AT91_REG SPI_TDR; /* Transmit Data Register */
703 AT91_REG SPI_SR; /* Status Register */
704 AT91_REG SPI_IER; /* Interrupt Enable Register */
705 AT91_REG SPI_IDR; /* Interrupt Disable Register */
706 AT91_REG SPI_IMR; /* Interrupt Mask Register */
707 AT91_REG Reserved0[ 4 ]; /* */
708 AT91_REG SPI_CSR[ 4 ]; /* Chip Select Register */
709 AT91_REG Reserved1[ 48 ]; /* */
710 AT91_REG SPI_RPR; /* Receive Pointer Register */
711 AT91_REG SPI_RCR; /* Receive Counter Register */
712 AT91_REG SPI_TPR; /* Transmit Pointer Register */
713 AT91_REG SPI_TCR; /* Transmit Counter Register */
714 AT91_REG SPI_RNPR; /* Receive Next Pointer Register */
715 AT91_REG SPI_RNCR; /* Receive Next Counter Register */
716 AT91_REG SPI_TNPR; /* Transmit Next Pointer Register */
717 AT91_REG SPI_TNCR; /* Transmit Next Counter Register */
718 AT91_REG SPI_PTCR; /* PDC Transfer Control Register */
719 AT91_REG SPI_PTSR; /* PDC Transfer Status Register */
720 } AT91S_SPI, * AT91PS_SPI;
722 /* -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- */
723 #define AT91C_SPI_SPIEN ( ( unsigned int ) 0x1 << 0 ) /* (SPI) SPI Enable */
724 #define AT91C_SPI_SPIDIS ( ( unsigned int ) 0x1 << 1 ) /* (SPI) SPI Disable */
725 #define AT91C_SPI_SWRST ( ( unsigned int ) 0x1 << 7 ) /* (SPI) SPI Software reset */
726 #define AT91C_SPI_LASTXFER ( ( unsigned int ) 0x1 << 24 ) /* (SPI) SPI Last Transfer */
727 /* -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- */
728 #define AT91C_SPI_MSTR ( ( unsigned int ) 0x1 << 0 ) /* (SPI) Master/Slave Mode */
729 #define AT91C_SPI_PS ( ( unsigned int ) 0x1 << 1 ) /* (SPI) Peripheral Select */
730 #define AT91C_SPI_PS_FIXED ( ( unsigned int ) 0x0 << 1 ) /* (SPI) Fixed Peripheral Select */
731 #define AT91C_SPI_PS_VARIABLE ( ( unsigned int ) 0x1 << 1 ) /* (SPI) Variable Peripheral Select */
732 #define AT91C_SPI_PCSDEC ( ( unsigned int ) 0x1 << 2 ) /* (SPI) Chip Select Decode */
733 #define AT91C_SPI_FDIV ( ( unsigned int ) 0x1 << 3 ) /* (SPI) Clock Selection */
734 #define AT91C_SPI_MODFDIS ( ( unsigned int ) 0x1 << 4 ) /* (SPI) Mode Fault Detection */
735 #define AT91C_SPI_LLB ( ( unsigned int ) 0x1 << 7 ) /* (SPI) Clock Selection */
736 #define AT91C_SPI_PCS ( ( unsigned int ) 0xF << 16 ) /* (SPI) Peripheral Chip Select */
737 #define AT91C_SPI_DLYBCS ( ( unsigned int ) 0xFF << 24 ) /* (SPI) Delay Between Chip Selects */
738 /* -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- */
739 #define AT91C_SPI_RD ( ( unsigned int ) 0xFFFF << 0 ) /* (SPI) Receive Data */
740 #define AT91C_SPI_RPCS ( ( unsigned int ) 0xF << 16 ) /* (SPI) Peripheral Chip Select Status */
741 /* -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- */
742 #define AT91C_SPI_TD ( ( unsigned int ) 0xFFFF << 0 ) /* (SPI) Transmit Data */
743 #define AT91C_SPI_TPCS ( ( unsigned int ) 0xF << 16 ) /* (SPI) Peripheral Chip Select Status */
744 /* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */
745 #define AT91C_SPI_RDRF ( ( unsigned int ) 0x1 << 0 ) /* (SPI) Receive Data Register Full */
746 #define AT91C_SPI_TDRE ( ( unsigned int ) 0x1 << 1 ) /* (SPI) Transmit Data Register Empty */
747 #define AT91C_SPI_MODF ( ( unsigned int ) 0x1 << 2 ) /* (SPI) Mode Fault Error */
748 #define AT91C_SPI_OVRES ( ( unsigned int ) 0x1 << 3 ) /* (SPI) Overrun Error Status */
749 #define AT91C_SPI_ENDRX ( ( unsigned int ) 0x1 << 4 ) /* (SPI) End of Receiver Transfer */
750 #define AT91C_SPI_ENDTX ( ( unsigned int ) 0x1 << 5 ) /* (SPI) End of Receiver Transfer */
751 #define AT91C_SPI_RXBUFF ( ( unsigned int ) 0x1 << 6 ) /* (SPI) RXBUFF Interrupt */
752 #define AT91C_SPI_TXBUFE ( ( unsigned int ) 0x1 << 7 ) /* (SPI) TXBUFE Interrupt */
753 #define AT91C_SPI_NSSR ( ( unsigned int ) 0x1 << 8 ) /* (SPI) NSSR Interrupt */
754 #define AT91C_SPI_TXEMPTY ( ( unsigned int ) 0x1 << 9 ) /* (SPI) TXEMPTY Interrupt */
755 #define AT91C_SPI_SPIENS ( ( unsigned int ) 0x1 << 16 ) /* (SPI) Enable Status */
756 /* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */
757 /* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */
758 /* -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- */
759 /* -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- */
760 #define AT91C_SPI_CPOL ( ( unsigned int ) 0x1 << 0 ) /* (SPI) Clock Polarity */
761 #define AT91C_SPI_NCPHA ( ( unsigned int ) 0x1 << 1 ) /* (SPI) Clock Phase */
762 #define AT91C_SPI_CSAAT ( ( unsigned int ) 0x1 << 3 ) /* (SPI) Chip Select Active After Transfer */
763 #define AT91C_SPI_BITS ( ( unsigned int ) 0xF << 4 ) /* (SPI) Bits Per Transfer */
764 #define AT91C_SPI_BITS_8 ( ( unsigned int ) 0x0 << 4 ) /* (SPI) 8 Bits Per transfer */
765 #define AT91C_SPI_BITS_9 ( ( unsigned int ) 0x1 << 4 ) /* (SPI) 9 Bits Per transfer */
766 #define AT91C_SPI_BITS_10 ( ( unsigned int ) 0x2 << 4 ) /* (SPI) 10 Bits Per transfer */
767 #define AT91C_SPI_BITS_11 ( ( unsigned int ) 0x3 << 4 ) /* (SPI) 11 Bits Per transfer */
768 #define AT91C_SPI_BITS_12 ( ( unsigned int ) 0x4 << 4 ) /* (SPI) 12 Bits Per transfer */
769 #define AT91C_SPI_BITS_13 ( ( unsigned int ) 0x5 << 4 ) /* (SPI) 13 Bits Per transfer */
770 #define AT91C_SPI_BITS_14 ( ( unsigned int ) 0x6 << 4 ) /* (SPI) 14 Bits Per transfer */
771 #define AT91C_SPI_BITS_15 ( ( unsigned int ) 0x7 << 4 ) /* (SPI) 15 Bits Per transfer */
772 #define AT91C_SPI_BITS_16 ( ( unsigned int ) 0x8 << 4 ) /* (SPI) 16 Bits Per transfer */
773 #define AT91C_SPI_SCBR ( ( unsigned int ) 0xFF << 8 ) /* (SPI) Serial Clock Baud Rate */
774 #define AT91C_SPI_DLYBS ( ( unsigned int ) 0xFF << 16 ) /* (SPI) Delay Before SPCK */
775 #define AT91C_SPI_DLYBCT ( ( unsigned int ) 0xFF << 24 ) /* (SPI) Delay Between Consecutive Transfers */
777 /* ***************************************************************************** */
778 /* SOFTWARE API DEFINITION FOR Usart */
779 /* ***************************************************************************** */
780 typedef struct _AT91S_USART
782 AT91_REG US_CR; /* Control Register */
783 AT91_REG US_MR; /* Mode Register */
784 AT91_REG US_IER; /* Interrupt Enable Register */
785 AT91_REG US_IDR; /* Interrupt Disable Register */
786 AT91_REG US_IMR; /* Interrupt Mask Register */
787 AT91_REG US_CSR; /* Channel Status Register */
788 AT91_REG US_RHR; /* Receiver Holding Register */
789 AT91_REG US_THR; /* Transmitter Holding Register */
790 AT91_REG US_BRGR; /* Baud Rate Generator Register */
791 AT91_REG US_RTOR; /* Receiver Time-out Register */
792 AT91_REG US_TTGR; /* Transmitter Time-guard Register */
793 AT91_REG Reserved0[ 5 ]; /* */
794 AT91_REG US_FIDI; /* FI_DI_Ratio Register */
795 AT91_REG US_NER; /* Nb Errors Register */
796 AT91_REG Reserved1[ 1 ]; /* */
797 AT91_REG US_IF; /* IRDA_FILTER Register */
798 AT91_REG Reserved2[ 44 ]; /* */
799 AT91_REG US_RPR; /* Receive Pointer Register */
800 AT91_REG US_RCR; /* Receive Counter Register */
801 AT91_REG US_TPR; /* Transmit Pointer Register */
802 AT91_REG US_TCR; /* Transmit Counter Register */
803 AT91_REG US_RNPR; /* Receive Next Pointer Register */
804 AT91_REG US_RNCR; /* Receive Next Counter Register */
805 AT91_REG US_TNPR; /* Transmit Next Pointer Register */
806 AT91_REG US_TNCR; /* Transmit Next Counter Register */
807 AT91_REG US_PTCR; /* PDC Transfer Control Register */
808 AT91_REG US_PTSR; /* PDC Transfer Status Register */
809 } AT91S_USART, * AT91PS_USART;
811 /* -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- */
812 #define AT91C_US_STTBRK ( ( unsigned int ) 0x1 << 9 ) /* (USART) Start Break */
813 #define AT91C_US_STPBRK ( ( unsigned int ) 0x1 << 10 ) /* (USART) Stop Break */
814 #define AT91C_US_STTTO ( ( unsigned int ) 0x1 << 11 ) /* (USART) Start Time-out */
815 #define AT91C_US_SENDA ( ( unsigned int ) 0x1 << 12 ) /* (USART) Send Address */
816 #define AT91C_US_RSTIT ( ( unsigned int ) 0x1 << 13 ) /* (USART) Reset Iterations */
817 #define AT91C_US_RSTNACK ( ( unsigned int ) 0x1 << 14 ) /* (USART) Reset Non Acknowledge */
818 #define AT91C_US_RETTO ( ( unsigned int ) 0x1 << 15 ) /* (USART) Rearm Time-out */
819 #define AT91C_US_DTREN ( ( unsigned int ) 0x1 << 16 ) /* (USART) Data Terminal ready Enable */
820 #define AT91C_US_DTRDIS ( ( unsigned int ) 0x1 << 17 ) /* (USART) Data Terminal ready Disable */
821 #define AT91C_US_RTSEN ( ( unsigned int ) 0x1 << 18 ) /* (USART) Request to Send enable */
822 #define AT91C_US_RTSDIS ( ( unsigned int ) 0x1 << 19 ) /* (USART) Request to Send Disable */
823 /* -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- */
824 #define AT91C_US_USMODE ( ( unsigned int ) 0xF << 0 ) /* (USART) Usart mode */
825 #define AT91C_US_USMODE_NORMAL ( ( unsigned int ) 0x0 ) /* (USART) Normal */
826 #define AT91C_US_USMODE_RS485 ( ( unsigned int ) 0x1 ) /* (USART) RS485 */
827 #define AT91C_US_USMODE_HWHSH ( ( unsigned int ) 0x2 ) /* (USART) Hardware Handshaking */
828 #define AT91C_US_USMODE_MODEM ( ( unsigned int ) 0x3 ) /* (USART) Modem */
829 #define AT91C_US_USMODE_ISO7816_0 ( ( unsigned int ) 0x4 ) /* (USART) ISO7816 protocol: T = 0 */
830 #define AT91C_US_USMODE_ISO7816_1 ( ( unsigned int ) 0x6 ) /* (USART) ISO7816 protocol: T = 1 */
831 #define AT91C_US_USMODE_IRDA ( ( unsigned int ) 0x8 ) /* (USART) IrDA */
832 #define AT91C_US_USMODE_SWHSH ( ( unsigned int ) 0xC ) /* (USART) Software Handshaking */
833 #define AT91C_US_CLKS ( ( unsigned int ) 0x3 << 4 ) /* (USART) Clock Selection (Baud Rate generator Input Clock */
834 #define AT91C_US_CLKS_CLOCK ( ( unsigned int ) 0x0 << 4 ) /* (USART) Clock */
835 #define AT91C_US_CLKS_FDIV1 ( ( unsigned int ) 0x1 << 4 ) /* (USART) fdiv1 */
836 #define AT91C_US_CLKS_SLOW ( ( unsigned int ) 0x2 << 4 ) /* (USART) slow_clock (ARM) */
837 #define AT91C_US_CLKS_EXT ( ( unsigned int ) 0x3 << 4 ) /* (USART) External (SCK) */
838 #define AT91C_US_CHRL ( ( unsigned int ) 0x3 << 6 ) /* (USART) Clock Selection (Baud Rate generator Input Clock */
839 #define AT91C_US_CHRL_5_BITS ( ( unsigned int ) 0x0 << 6 ) /* (USART) Character Length: 5 bits */
840 #define AT91C_US_CHRL_6_BITS ( ( unsigned int ) 0x1 << 6 ) /* (USART) Character Length: 6 bits */
841 #define AT91C_US_CHRL_7_BITS ( ( unsigned int ) 0x2 << 6 ) /* (USART) Character Length: 7 bits */
842 #define AT91C_US_CHRL_8_BITS ( ( unsigned int ) 0x3 << 6 ) /* (USART) Character Length: 8 bits */
843 #define AT91C_US_SYNC ( ( unsigned int ) 0x1 << 8 ) /* (USART) Synchronous Mode Select */
844 #define AT91C_US_NBSTOP ( ( unsigned int ) 0x3 << 12 ) /* (USART) Number of Stop bits */
845 #define AT91C_US_NBSTOP_1_BIT ( ( unsigned int ) 0x0 << 12 ) /* (USART) 1 stop bit */
846 #define AT91C_US_NBSTOP_15_BIT ( ( unsigned int ) 0x1 << 12 ) /* (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits */
847 #define AT91C_US_NBSTOP_2_BIT ( ( unsigned int ) 0x2 << 12 ) /* (USART) 2 stop bits */
848 #define AT91C_US_MSBF ( ( unsigned int ) 0x1 << 16 ) /* (USART) Bit Order */
849 #define AT91C_US_MODE9 ( ( unsigned int ) 0x1 << 17 ) /* (USART) 9-bit Character length */
850 #define AT91C_US_CKLO ( ( unsigned int ) 0x1 << 18 ) /* (USART) Clock Output Select */
851 #define AT91C_US_OVER ( ( unsigned int ) 0x1 << 19 ) /* (USART) Over Sampling Mode */
852 #define AT91C_US_INACK ( ( unsigned int ) 0x1 << 20 ) /* (USART) Inhibit Non Acknowledge */
853 #define AT91C_US_DSNACK ( ( unsigned int ) 0x1 << 21 ) /* (USART) Disable Successive NACK */
854 #define AT91C_US_MAX_ITER ( ( unsigned int ) 0x1 << 24 ) /* (USART) Number of Repetitions */
855 #define AT91C_US_FILTER ( ( unsigned int ) 0x1 << 28 ) /* (USART) Receive Line Filter */
856 /* -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- */
857 #define AT91C_US_RXBRK ( ( unsigned int ) 0x1 << 2 ) /* (USART) Break Received/End of Break */
858 #define AT91C_US_TIMEOUT ( ( unsigned int ) 0x1 << 8 ) /* (USART) Receiver Time-out */
859 #define AT91C_US_ITERATION ( ( unsigned int ) 0x1 << 10 ) /* (USART) Max number of Repetitions Reached */
860 #define AT91C_US_NACK ( ( unsigned int ) 0x1 << 13 ) /* (USART) Non Acknowledge */
861 #define AT91C_US_RIIC ( ( unsigned int ) 0x1 << 16 ) /* (USART) Ring INdicator Input Change Flag */
862 #define AT91C_US_DSRIC ( ( unsigned int ) 0x1 << 17 ) /* (USART) Data Set Ready Input Change Flag */
863 #define AT91C_US_DCDIC ( ( unsigned int ) 0x1 << 18 ) /* (USART) Data Carrier Flag */
864 #define AT91C_US_CTSIC ( ( unsigned int ) 0x1 << 19 ) /* (USART) Clear To Send Input Change Flag */
865 /* -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- */
866 /* -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- */
867 /* -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- */
868 #define AT91C_US_RI ( ( unsigned int ) 0x1 << 20 ) /* (USART) Image of RI Input */
869 #define AT91C_US_DSR ( ( unsigned int ) 0x1 << 21 ) /* (USART) Image of DSR Input */
870 #define AT91C_US_DCD ( ( unsigned int ) 0x1 << 22 ) /* (USART) Image of DCD Input */
871 #define AT91C_US_CTS ( ( unsigned int ) 0x1 << 23 ) /* (USART) Image of CTS Input */
873 /* ***************************************************************************** */
874 /* SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface */
875 /* ***************************************************************************** */
876 typedef struct _AT91S_SSC
878 AT91_REG SSC_CR; /* Control Register */
879 AT91_REG SSC_CMR; /* Clock Mode Register */
880 AT91_REG Reserved0[ 2 ]; /* */
881 AT91_REG SSC_RCMR; /* Receive Clock ModeRegister */
882 AT91_REG SSC_RFMR; /* Receive Frame Mode Register */
883 AT91_REG SSC_TCMR; /* Transmit Clock Mode Register */
884 AT91_REG SSC_TFMR; /* Transmit Frame Mode Register */
885 AT91_REG SSC_RHR; /* Receive Holding Register */
886 AT91_REG SSC_THR; /* Transmit Holding Register */
887 AT91_REG Reserved1[ 2 ]; /* */
888 AT91_REG SSC_RSHR; /* Receive Sync Holding Register */
889 AT91_REG SSC_TSHR; /* Transmit Sync Holding Register */
890 AT91_REG Reserved2[ 2 ]; /* */
891 AT91_REG SSC_SR; /* Status Register */
892 AT91_REG SSC_IER; /* Interrupt Enable Register */
893 AT91_REG SSC_IDR; /* Interrupt Disable Register */
894 AT91_REG SSC_IMR; /* Interrupt Mask Register */
895 AT91_REG Reserved3[ 44 ]; /* */
896 AT91_REG SSC_RPR; /* Receive Pointer Register */
897 AT91_REG SSC_RCR; /* Receive Counter Register */
898 AT91_REG SSC_TPR; /* Transmit Pointer Register */
899 AT91_REG SSC_TCR; /* Transmit Counter Register */
900 AT91_REG SSC_RNPR; /* Receive Next Pointer Register */
901 AT91_REG SSC_RNCR; /* Receive Next Counter Register */
902 AT91_REG SSC_TNPR; /* Transmit Next Pointer Register */
903 AT91_REG SSC_TNCR; /* Transmit Next Counter Register */
904 AT91_REG SSC_PTCR; /* PDC Transfer Control Register */
905 AT91_REG SSC_PTSR; /* PDC Transfer Status Register */
906 } AT91S_SSC, * AT91PS_SSC;
908 /* -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- */
909 #define AT91C_SSC_RXEN ( ( unsigned int ) 0x1 << 0 ) /* (SSC) Receive Enable */
910 #define AT91C_SSC_RXDIS ( ( unsigned int ) 0x1 << 1 ) /* (SSC) Receive Disable */
911 #define AT91C_SSC_TXEN ( ( unsigned int ) 0x1 << 8 ) /* (SSC) Transmit Enable */
912 #define AT91C_SSC_TXDIS ( ( unsigned int ) 0x1 << 9 ) /* (SSC) Transmit Disable */
913 #define AT91C_SSC_SWRST ( ( unsigned int ) 0x1 << 15 ) /* (SSC) Software Reset */
914 /* -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- */
915 #define AT91C_SSC_CKS ( ( unsigned int ) 0x3 << 0 ) /* (SSC) Receive/Transmit Clock Selection */
916 #define AT91C_SSC_CKS_DIV ( ( unsigned int ) 0x0 ) /* (SSC) Divided Clock */
917 #define AT91C_SSC_CKS_TK ( ( unsigned int ) 0x1 ) /* (SSC) TK Clock signal */
918 #define AT91C_SSC_CKS_RK ( ( unsigned int ) 0x2 ) /* (SSC) RK pin */
919 #define AT91C_SSC_CKO ( ( unsigned int ) 0x7 << 2 ) /* (SSC) Receive/Transmit Clock Output Mode Selection */
920 #define AT91C_SSC_CKO_NONE ( ( unsigned int ) 0x0 << 2 ) /* (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only */
921 #define AT91C_SSC_CKO_CONTINUOUS ( ( unsigned int ) 0x1 << 2 ) /* (SSC) Continuous Receive/Transmit Clock RK pin: Output */
922 #define AT91C_SSC_CKO_DATA_TX ( ( unsigned int ) 0x2 << 2 ) /* (SSC) Receive/Transmit Clock only during data transfers RK pin: Output */
923 #define AT91C_SSC_CKI ( ( unsigned int ) 0x1 << 5 ) /* (SSC) Receive/Transmit Clock Inversion */
924 #define AT91C_SSC_START ( ( unsigned int ) 0xF << 8 ) /* (SSC) Receive/Transmit Start Selection */
925 #define AT91C_SSC_START_CONTINUOUS ( ( unsigned int ) 0x0 << 8 ) /* (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. */
926 #define AT91C_SSC_START_TX ( ( unsigned int ) 0x1 << 8 ) /* (SSC) Transmit/Receive start */
927 #define AT91C_SSC_START_LOW_RF ( ( unsigned int ) 0x2 << 8 ) /* (SSC) Detection of a low level on RF input */
928 #define AT91C_SSC_START_HIGH_RF ( ( unsigned int ) 0x3 << 8 ) /* (SSC) Detection of a high level on RF input */
929 #define AT91C_SSC_START_FALL_RF ( ( unsigned int ) 0x4 << 8 ) /* (SSC) Detection of a falling edge on RF input */
930 #define AT91C_SSC_START_RISE_RF ( ( unsigned int ) 0x5 << 8 ) /* (SSC) Detection of a rising edge on RF input */
931 #define AT91C_SSC_START_LEVEL_RF ( ( unsigned int ) 0x6 << 8 ) /* (SSC) Detection of any level change on RF input */
932 #define AT91C_SSC_START_EDGE_RF ( ( unsigned int ) 0x7 << 8 ) /* (SSC) Detection of any edge on RF input */
933 #define AT91C_SSC_START_0 ( ( unsigned int ) 0x8 << 8 ) /* (SSC) Compare 0 */
934 #define AT91C_SSC_STTDLY ( ( unsigned int ) 0xFF << 16 ) /* (SSC) Receive/Transmit Start Delay */
935 #define AT91C_SSC_PERIOD ( ( unsigned int ) 0xFF << 24 ) /* (SSC) Receive/Transmit Period Divider Selection */
936 /* -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- */
937 #define AT91C_SSC_DATLEN ( ( unsigned int ) 0x1F << 0 ) /* (SSC) Data Length */
938 #define AT91C_SSC_LOOP ( ( unsigned int ) 0x1 << 5 ) /* (SSC) Loop Mode */
939 #define AT91C_SSC_MSBF ( ( unsigned int ) 0x1 << 7 ) /* (SSC) Most Significant Bit First */
940 #define AT91C_SSC_DATNB ( ( unsigned int ) 0xF << 8 ) /* (SSC) Data Number per Frame */
941 #define AT91C_SSC_FSLEN ( ( unsigned int ) 0xF << 16 ) /* (SSC) Receive/Transmit Frame Sync length */
942 #define AT91C_SSC_FSOS ( ( unsigned int ) 0x7 << 20 ) /* (SSC) Receive/Transmit Frame Sync Output Selection */
943 #define AT91C_SSC_FSOS_NONE ( ( unsigned int ) 0x0 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only */
944 #define AT91C_SSC_FSOS_NEGATIVE ( ( unsigned int ) 0x1 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse */
945 #define AT91C_SSC_FSOS_POSITIVE ( ( unsigned int ) 0x2 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse */
946 #define AT91C_SSC_FSOS_LOW ( ( unsigned int ) 0x3 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer */
947 #define AT91C_SSC_FSOS_HIGH ( ( unsigned int ) 0x4 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer */
948 #define AT91C_SSC_FSOS_TOGGLE ( ( unsigned int ) 0x5 << 20 ) /* (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer */
949 #define AT91C_SSC_FSEDGE ( ( unsigned int ) 0x1 << 24 ) /* (SSC) Frame Sync Edge Detection */
950 /* -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- */
951 /* -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- */
952 #define AT91C_SSC_DATDEF ( ( unsigned int ) 0x1 << 5 ) /* (SSC) Data Default Value */
953 #define AT91C_SSC_FSDEN ( ( unsigned int ) 0x1 << 23 ) /* (SSC) Frame Sync Data Enable */
954 /* -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- */
955 #define AT91C_SSC_TXRDY ( ( unsigned int ) 0x1 << 0 ) /* (SSC) Transmit Ready */
956 #define AT91C_SSC_TXEMPTY ( ( unsigned int ) 0x1 << 1 ) /* (SSC) Transmit Empty */
957 #define AT91C_SSC_ENDTX ( ( unsigned int ) 0x1 << 2 ) /* (SSC) End Of Transmission */
958 #define AT91C_SSC_TXBUFE ( ( unsigned int ) 0x1 << 3 ) /* (SSC) Transmit Buffer Empty */
959 #define AT91C_SSC_RXRDY ( ( unsigned int ) 0x1 << 4 ) /* (SSC) Receive Ready */
960 #define AT91C_SSC_OVRUN ( ( unsigned int ) 0x1 << 5 ) /* (SSC) Receive Overrun */
961 #define AT91C_SSC_ENDRX ( ( unsigned int ) 0x1 << 6 ) /* (SSC) End of Reception */
962 #define AT91C_SSC_RXBUFF ( ( unsigned int ) 0x1 << 7 ) /* (SSC) Receive Buffer Full */
963 #define AT91C_SSC_TXSYN ( ( unsigned int ) 0x1 << 10 ) /* (SSC) Transmit Sync */
964 #define AT91C_SSC_RXSYN ( ( unsigned int ) 0x1 << 11 ) /* (SSC) Receive Sync */
965 #define AT91C_SSC_TXENA ( ( unsigned int ) 0x1 << 16 ) /* (SSC) Transmit Enable */
966 #define AT91C_SSC_RXENA ( ( unsigned int ) 0x1 << 17 ) /* (SSC) Receive Enable */
967 /* -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- */
968 /* -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- */
969 /* -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- */
971 /* ***************************************************************************** */
972 /* SOFTWARE API DEFINITION FOR Two-wire Interface */
973 /* ***************************************************************************** */
974 typedef struct _AT91S_TWI
976 AT91_REG TWI_CR; /* Control Register */
977 AT91_REG TWI_MMR; /* Master Mode Register */
978 AT91_REG Reserved0[ 1 ]; /* */
979 AT91_REG TWI_IADR; /* Internal Address Register */
980 AT91_REG TWI_CWGR; /* Clock Waveform Generator Register */
981 AT91_REG Reserved1[ 3 ]; /* */
982 AT91_REG TWI_SR; /* Status Register */
983 AT91_REG TWI_IER; /* Interrupt Enable Register */
984 AT91_REG TWI_IDR; /* Interrupt Disable Register */
985 AT91_REG TWI_IMR; /* Interrupt Mask Register */
986 AT91_REG TWI_RHR; /* Receive Holding Register */
987 AT91_REG TWI_THR; /* Transmit Holding Register */
988 } AT91S_TWI, * AT91PS_TWI;
990 /* -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- */
991 #define AT91C_TWI_START ( ( unsigned int ) 0x1 << 0 ) /* (TWI) Send a START Condition */
992 #define AT91C_TWI_STOP ( ( unsigned int ) 0x1 << 1 ) /* (TWI) Send a STOP Condition */
993 #define AT91C_TWI_MSEN ( ( unsigned int ) 0x1 << 2 ) /* (TWI) TWI Master Transfer Enabled */
994 #define AT91C_TWI_MSDIS ( ( unsigned int ) 0x1 << 3 ) /* (TWI) TWI Master Transfer Disabled */
995 #define AT91C_TWI_SWRST ( ( unsigned int ) 0x1 << 7 ) /* (TWI) Software Reset */
996 /* -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- */
997 #define AT91C_TWI_IADRSZ ( ( unsigned int ) 0x3 << 8 ) /* (TWI) Internal Device Address Size */
998 #define AT91C_TWI_IADRSZ_NO ( ( unsigned int ) 0x0 << 8 ) /* (TWI) No internal device address */
999 #define AT91C_TWI_IADRSZ_1_BYTE ( ( unsigned int ) 0x1 << 8 ) /* (TWI) One-byte internal device address */
1000 #define AT91C_TWI_IADRSZ_2_BYTE ( ( unsigned int ) 0x2 << 8 ) /* (TWI) Two-byte internal device address */
1001 #define AT91C_TWI_IADRSZ_3_BYTE ( ( unsigned int ) 0x3 << 8 ) /* (TWI) Three-byte internal device address */
1002 #define AT91C_TWI_MREAD ( ( unsigned int ) 0x1 << 12 ) /* (TWI) Master Read Direction */
1003 #define AT91C_TWI_DADR ( ( unsigned int ) 0x7F << 16 ) /* (TWI) Device Address */
1004 /* -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- */
1005 #define AT91C_TWI_CLDIV ( ( unsigned int ) 0xFF << 0 ) /* (TWI) Clock Low Divider */
1006 #define AT91C_TWI_CHDIV ( ( unsigned int ) 0xFF << 8 ) /* (TWI) Clock High Divider */
1007 #define AT91C_TWI_CKDIV ( ( unsigned int ) 0x7 << 16 ) /* (TWI) Clock Divider */
1008 /* -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- */
1009 #define AT91C_TWI_TXCOMP ( ( unsigned int ) 0x1 << 0 ) /* (TWI) Transmission Completed */
1010 #define AT91C_TWI_RXRDY ( ( unsigned int ) 0x1 << 1 ) /* (TWI) Receive holding register ReaDY */
1011 #define AT91C_TWI_TXRDY ( ( unsigned int ) 0x1 << 2 ) /* (TWI) Transmit holding register ReaDY */
1012 #define AT91C_TWI_OVRE ( ( unsigned int ) 0x1 << 6 ) /* (TWI) Overrun Error */
1013 #define AT91C_TWI_UNRE ( ( unsigned int ) 0x1 << 7 ) /* (TWI) Underrun Error */
1014 #define AT91C_TWI_NACK ( ( unsigned int ) 0x1 << 8 ) /* (TWI) Not Acknowledged */
1015 /* -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- */
1016 /* -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- */
1017 /* -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- */
1019 /* ***************************************************************************** */
1020 /* SOFTWARE API DEFINITION FOR PWMC Channel Interface */
1021 /* ***************************************************************************** */
1022 typedef struct _AT91S_PWMC_CH
1024 AT91_REG PWMC_CMR; /* Channel Mode Register */
1025 AT91_REG PWMC_CDTYR; /* Channel Duty Cycle Register */
1026 AT91_REG PWMC_CPRDR; /* Channel Period Register */
1027 AT91_REG PWMC_CCNTR; /* Channel Counter Register */
1028 AT91_REG PWMC_CUPDR; /* Channel Update Register */
1029 AT91_REG PWMC_Reserved[ 3 ]; /* Reserved */
1030 } AT91S_PWMC_CH, * AT91PS_PWMC_CH;
1032 /* -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- */
1033 #define AT91C_PWMC_CPRE ( ( unsigned int ) 0xF << 0 ) /* (PWMC_CH) Channel Pre-scaler : PWMC_CLKx */
1034 #define AT91C_PWMC_CPRE_MCK ( ( unsigned int ) 0x0 ) /* (PWMC_CH) */
1035 #define AT91C_PWMC_CPRE_MCKA ( ( unsigned int ) 0xB ) /* (PWMC_CH) */
1036 #define AT91C_PWMC_CPRE_MCKB ( ( unsigned int ) 0xC ) /* (PWMC_CH) */
1037 #define AT91C_PWMC_CALG ( ( unsigned int ) 0x1 << 8 ) /* (PWMC_CH) Channel Alignment */
1038 #define AT91C_PWMC_CPOL ( ( unsigned int ) 0x1 << 9 ) /* (PWMC_CH) Channel Polarity */
1039 #define AT91C_PWMC_CPD ( ( unsigned int ) 0x1 << 10 ) /* (PWMC_CH) Channel Update Period */
1040 /* -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- */
1041 #define AT91C_PWMC_CDTY ( ( unsigned int ) 0x0 << 0 ) /* (PWMC_CH) Channel Duty Cycle */
1042 /* -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- */
1043 #define AT91C_PWMC_CPRD ( ( unsigned int ) 0x0 << 0 ) /* (PWMC_CH) Channel Period */
1044 /* -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- */
1045 #define AT91C_PWMC_CCNT ( ( unsigned int ) 0x0 << 0 ) /* (PWMC_CH) Channel Counter */
1046 /* -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- */
1047 #define AT91C_PWMC_CUPD ( ( unsigned int ) 0x0 << 0 ) /* (PWMC_CH) Channel Update */
1049 /* ***************************************************************************** */
1050 /* SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface */
1051 /* ***************************************************************************** */
1052 typedef struct _AT91S_PWMC
1054 AT91_REG PWMC_MR; /* PWMC Mode Register */
1055 AT91_REG PWMC_ENA; /* PWMC Enable Register */
1056 AT91_REG PWMC_DIS; /* PWMC Disable Register */
1057 AT91_REG PWMC_SR; /* PWMC Status Register */
1058 AT91_REG PWMC_IER; /* PWMC Interrupt Enable Register */
1059 AT91_REG PWMC_IDR; /* PWMC Interrupt Disable Register */
1060 AT91_REG PWMC_IMR; /* PWMC Interrupt Mask Register */
1061 AT91_REG PWMC_ISR; /* PWMC Interrupt Status Register */
1062 AT91_REG Reserved0[ 55 ]; /* */
1063 AT91_REG PWMC_VR; /* PWMC Version Register */
1064 AT91_REG Reserved1[ 64 ]; /* */
1065 AT91S_PWMC_CH PWMC_CH[ 4 ]; /* PWMC Channel */
1066 } AT91S_PWMC, * AT91PS_PWMC;
1068 /* -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- */
1069 #define AT91C_PWMC_DIVA ( ( unsigned int ) 0xFF << 0 ) /* (PWMC) CLKA divide factor. */
1070 #define AT91C_PWMC_PREA ( ( unsigned int ) 0xF << 8 ) /* (PWMC) Divider Input Clock Prescaler A */
1071 #define AT91C_PWMC_PREA_MCK ( ( unsigned int ) 0x0 << 8 ) /* (PWMC) */
1072 #define AT91C_PWMC_DIVB ( ( unsigned int ) 0xFF << 16 ) /* (PWMC) CLKB divide factor. */
1073 #define AT91C_PWMC_PREB ( ( unsigned int ) 0xF << 24 ) /* (PWMC) Divider Input Clock Prescaler B */
1074 #define AT91C_PWMC_PREB_MCK ( ( unsigned int ) 0x0 << 24 ) /* (PWMC) */
1075 /* -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- */
1076 #define AT91C_PWMC_CHID0 ( ( unsigned int ) 0x1 << 0 ) /* (PWMC) Channel ID 0 */
1077 #define AT91C_PWMC_CHID1 ( ( unsigned int ) 0x1 << 1 ) /* (PWMC) Channel ID 1 */
1078 #define AT91C_PWMC_CHID2 ( ( unsigned int ) 0x1 << 2 ) /* (PWMC) Channel ID 2 */
1079 #define AT91C_PWMC_CHID3 ( ( unsigned int ) 0x1 << 3 ) /* (PWMC) Channel ID 3 */
1080 /* -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- */
1081 /* -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- */
1082 /* -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- */
1083 /* -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- */
1084 /* -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- */
1085 /* -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- */
1087 /* ***************************************************************************** */
1088 /* SOFTWARE API DEFINITION FOR USB Device Interface */
1089 /* ***************************************************************************** */
1090 typedef struct _AT91S_UDP
1092 AT91_REG UDP_NUM; /* Frame Number Register */
1093 AT91_REG UDP_GLBSTATE; /* Global State Register */
1094 AT91_REG UDP_FADDR; /* Function Address Register */
1095 AT91_REG Reserved0[ 1 ]; /* */
1096 AT91_REG UDP_IER; /* Interrupt Enable Register */
1097 AT91_REG UDP_IDR; /* Interrupt Disable Register */
1098 AT91_REG UDP_IMR; /* Interrupt Mask Register */
1099 AT91_REG UDP_ISR; /* Interrupt Status Register */
1100 AT91_REG UDP_ICR; /* Interrupt Clear Register */
1101 AT91_REG Reserved1[ 1 ]; /* */
1102 AT91_REG UDP_RSTEP; /* Reset Endpoint Register */
1103 AT91_REG Reserved2[ 1 ]; /* */
1104 AT91_REG UDP_CSR[ 6 ]; /* Endpoint Control and Status Register */
1105 AT91_REG Reserved3[ 2 ]; /* */
1106 AT91_REG UDP_FDR[ 6 ]; /* Endpoint FIFO Data Register */
1107 AT91_REG Reserved4[ 3 ]; /* */
1108 AT91_REG UDP_TXVC; /* Transceiver Control Register */
1109 } AT91S_UDP, * AT91PS_UDP;
1111 /* -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- */
1112 #define AT91C_UDP_FRM_NUM ( ( unsigned int ) 0x7FF << 0 ) /* (UDP) Frame Number as Defined in the Packet Field Formats */
1113 #define AT91C_UDP_FRM_ERR ( ( unsigned int ) 0x1 << 16 ) /* (UDP) Frame Error */
1114 #define AT91C_UDP_FRM_OK ( ( unsigned int ) 0x1 << 17 ) /* (UDP) Frame OK */
1115 /* -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- */
1116 #define AT91C_UDP_FADDEN ( ( unsigned int ) 0x1 << 0 ) /* (UDP) Function Address Enable */
1117 #define AT91C_UDP_CONFG ( ( unsigned int ) 0x1 << 1 ) /* (UDP) Configured */
1118 #define AT91C_UDP_ESR ( ( unsigned int ) 0x1 << 2 ) /* (UDP) Enable Send Resume */
1119 #define AT91C_UDP_RSMINPR ( ( unsigned int ) 0x1 << 3 ) /* (UDP) A Resume Has Been Sent to the Host */
1120 #define AT91C_UDP_RMWUPE ( ( unsigned int ) 0x1 << 4 ) /* (UDP) Remote Wake Up Enable */
1121 /* -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- */
1122 #define AT91C_UDP_FADD ( ( unsigned int ) 0xFF << 0 ) /* (UDP) Function Address Value */
1123 #define AT91C_UDP_FEN ( ( unsigned int ) 0x1 << 8 ) /* (UDP) Function Enable */
1124 /* -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- */
1125 #define AT91C_UDP_EPINT0 ( ( unsigned int ) 0x1 << 0 ) /* (UDP) Endpoint 0 Interrupt */
1126 #define AT91C_UDP_EPINT1 ( ( unsigned int ) 0x1 << 1 ) /* (UDP) Endpoint 0 Interrupt */
1127 #define AT91C_UDP_EPINT2 ( ( unsigned int ) 0x1 << 2 ) /* (UDP) Endpoint 2 Interrupt */
1128 #define AT91C_UDP_EPINT3 ( ( unsigned int ) 0x1 << 3 ) /* (UDP) Endpoint 3 Interrupt */
1129 #define AT91C_UDP_EPINT4 ( ( unsigned int ) 0x1 << 4 ) /* (UDP) Endpoint 4 Interrupt */
1130 #define AT91C_UDP_EPINT5 ( ( unsigned int ) 0x1 << 5 ) /* (UDP) Endpoint 5 Interrupt */
1131 #define AT91C_UDP_RXSUSP ( ( unsigned int ) 0x1 << 8 ) /* (UDP) USB Suspend Interrupt */
1132 #define AT91C_UDP_RXRSM ( ( unsigned int ) 0x1 << 9 ) /* (UDP) USB Resume Interrupt */
1133 #define AT91C_UDP_EXTRSM ( ( unsigned int ) 0x1 << 10 ) /* (UDP) USB External Resume Interrupt */
1134 #define AT91C_UDP_SOFINT ( ( unsigned int ) 0x1 << 11 ) /* (UDP) USB Start Of frame Interrupt */
1135 #define AT91C_UDP_WAKEUP ( ( unsigned int ) 0x1 << 13 ) /* (UDP) USB Resume Interrupt */
1136 /* -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- */
1137 /* -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- */
1138 /* -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- */
1139 #define AT91C_UDP_ENDBUSRES ( ( unsigned int ) 0x1 << 12 ) /* (UDP) USB End Of Bus Reset Interrupt */
1140 /* -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- */
1141 /* -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- */
1142 #define AT91C_UDP_EP0 ( ( unsigned int ) 0x1 << 0 ) /* (UDP) Reset Endpoint 0 */
1143 #define AT91C_UDP_EP1 ( ( unsigned int ) 0x1 << 1 ) /* (UDP) Reset Endpoint 1 */
1144 #define AT91C_UDP_EP2 ( ( unsigned int ) 0x1 << 2 ) /* (UDP) Reset Endpoint 2 */
1145 #define AT91C_UDP_EP3 ( ( unsigned int ) 0x1 << 3 ) /* (UDP) Reset Endpoint 3 */
1146 #define AT91C_UDP_EP4 ( ( unsigned int ) 0x1 << 4 ) /* (UDP) Reset Endpoint 4 */
1147 #define AT91C_UDP_EP5 ( ( unsigned int ) 0x1 << 5 ) /* (UDP) Reset Endpoint 5 */
1148 /* -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- */
1149 #define AT91C_UDP_TXCOMP ( ( unsigned int ) 0x1 << 0 ) /* (UDP) Generates an IN packet with data previously written in the DPR */
1150 #define AT91C_UDP_RX_DATA_BK0 ( ( unsigned int ) 0x1 << 1 ) /* (UDP) Receive Data Bank 0 */
1151 #define AT91C_UDP_RXSETUP ( ( unsigned int ) 0x1 << 2 ) /* (UDP) Sends STALL to the Host (Control endpoints) */
1152 #define AT91C_UDP_ISOERROR ( ( unsigned int ) 0x1 << 3 ) /* (UDP) Isochronous error (Isochronous endpoints) */
1153 #define AT91C_UDP_TXPKTRDY ( ( unsigned int ) 0x1 << 4 ) /* (UDP) Transmit Packet Ready */
1154 #define AT91C_UDP_FORCESTALL ( ( unsigned int ) 0x1 << 5 ) /* (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). */
1155 #define AT91C_UDP_RX_DATA_BK1 ( ( unsigned int ) 0x1 << 6 ) /* (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). */
1156 #define AT91C_UDP_DIR ( ( unsigned int ) 0x1 << 7 ) /* (UDP) Transfer Direction */
1157 #define AT91C_UDP_EPTYPE ( ( unsigned int ) 0x7 << 8 ) /* (UDP) Endpoint type */
1158 #define AT91C_UDP_EPTYPE_CTRL ( ( unsigned int ) 0x0 << 8 ) /* (UDP) Control */
1159 #define AT91C_UDP_EPTYPE_ISO_OUT ( ( unsigned int ) 0x1 << 8 ) /* (UDP) Isochronous OUT */
1160 #define AT91C_UDP_EPTYPE_BULK_OUT ( ( unsigned int ) 0x2 << 8 ) /* (UDP) Bulk OUT */
1161 #define AT91C_UDP_EPTYPE_INT_OUT ( ( unsigned int ) 0x3 << 8 ) /* (UDP) Interrupt OUT */
1162 #define AT91C_UDP_EPTYPE_ISO_IN ( ( unsigned int ) 0x5 << 8 ) /* (UDP) Isochronous IN */
1163 #define AT91C_UDP_EPTYPE_BULK_IN ( ( unsigned int ) 0x6 << 8 ) /* (UDP) Bulk IN */
1164 #define AT91C_UDP_EPTYPE_INT_IN ( ( unsigned int ) 0x7 << 8 ) /* (UDP) Interrupt IN */
1165 #define AT91C_UDP_DTGLE ( ( unsigned int ) 0x1 << 11 ) /* (UDP) Data Toggle */
1166 #define AT91C_UDP_EPEDS ( ( unsigned int ) 0x1 << 15 ) /* (UDP) Endpoint Enable Disable */
1167 #define AT91C_UDP_RXBYTECNT ( ( unsigned int ) 0x7FF << 16 ) /* (UDP) Number Of Bytes Available in the FIFO */
1168 /* -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- */
1169 #define AT91C_UDP_TXVDIS ( ( unsigned int ) 0x1 << 8 ) /* (UDP) */
1170 #define AT91C_UDP_PUON ( ( unsigned int ) 0x1 << 9 ) /* (UDP) Pull-up ON */
1172 /* ***************************************************************************** */
1173 /* SOFTWARE API DEFINITION FOR Timer Counter Channel Interface */
1174 /* ***************************************************************************** */
1175 typedef struct _AT91S_TC
1177 AT91_REG TC_CCR; /* Channel Control Register */
1178 AT91_REG TC_CMR; /* Channel Mode Register (Capture Mode / Waveform Mode) */
1179 AT91_REG Reserved0[ 2 ]; /* */
1180 AT91_REG TC_CV; /* Counter Value */
1181 AT91_REG TC_RA; /* Register A */
1182 AT91_REG TC_RB; /* Register B */
1183 AT91_REG TC_RC; /* Register C */
1184 AT91_REG TC_SR; /* Status Register */
1185 AT91_REG TC_IER; /* Interrupt Enable Register */
1186 AT91_REG TC_IDR; /* Interrupt Disable Register */
1187 AT91_REG TC_IMR; /* Interrupt Mask Register */
1188 } AT91S_TC, * AT91PS_TC;
1190 /* -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- */
1191 #define AT91C_TC_CLKEN ( ( unsigned int ) 0x1 << 0 ) /* (TC) Counter Clock Enable Command */
1192 #define AT91C_TC_CLKDIS ( ( unsigned int ) 0x1 << 1 ) /* (TC) Counter Clock Disable Command */
1193 #define AT91C_TC_SWTRG ( ( unsigned int ) 0x1 << 2 ) /* (TC) Software Trigger Command */
1194 /* -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- */
1195 #define AT91C_TC_CLKS ( ( unsigned int ) 0x7 << 0 ) /* (TC) Clock Selection */
1196 #define AT91C_TC_CLKS_TIMER_DIV1_CLOCK ( ( unsigned int ) 0x0 ) /* (TC) Clock selected: TIMER_DIV1_CLOCK */
1197 #define AT91C_TC_CLKS_TIMER_DIV2_CLOCK ( ( unsigned int ) 0x1 ) /* (TC) Clock selected: TIMER_DIV2_CLOCK */
1198 #define AT91C_TC_CLKS_TIMER_DIV3_CLOCK ( ( unsigned int ) 0x2 ) /* (TC) Clock selected: TIMER_DIV3_CLOCK */
1199 #define AT91C_TC_CLKS_TIMER_DIV4_CLOCK ( ( unsigned int ) 0x3 ) /* (TC) Clock selected: TIMER_DIV4_CLOCK */
1200 #define AT91C_TC_CLKS_TIMER_DIV5_CLOCK ( ( unsigned int ) 0x4 ) /* (TC) Clock selected: TIMER_DIV5_CLOCK */
1201 #define AT91C_TC_CLKS_XC0 ( ( unsigned int ) 0x5 ) /* (TC) Clock selected: XC0 */
1202 #define AT91C_TC_CLKS_XC1 ( ( unsigned int ) 0x6 ) /* (TC) Clock selected: XC1 */
1203 #define AT91C_TC_CLKS_XC2 ( ( unsigned int ) 0x7 ) /* (TC) Clock selected: XC2 */
1204 #define AT91C_TC_CLKI ( ( unsigned int ) 0x1 << 3 ) /* (TC) Clock Invert */
1205 #define AT91C_TC_BURST ( ( unsigned int ) 0x3 << 4 ) /* (TC) Burst Signal Selection */
1206 #define AT91C_TC_BURST_NONE ( ( unsigned int ) 0x0 << 4 ) /* (TC) The clock is not gated by an external signal */
1207 #define AT91C_TC_BURST_XC0 ( ( unsigned int ) 0x1 << 4 ) /* (TC) XC0 is ANDed with the selected clock */
1208 #define AT91C_TC_BURST_XC1 ( ( unsigned int ) 0x2 << 4 ) /* (TC) XC1 is ANDed with the selected clock */
1209 #define AT91C_TC_BURST_XC2 ( ( unsigned int ) 0x3 << 4 ) /* (TC) XC2 is ANDed with the selected clock */
1210 #define AT91C_TC_CPCSTOP ( ( unsigned int ) 0x1 << 6 ) /* (TC) Counter Clock Stopped with RC Compare */
1211 #define AT91C_TC_LDBSTOP ( ( unsigned int ) 0x1 << 6 ) /* (TC) Counter Clock Stopped with RB Loading */
1212 #define AT91C_TC_CPCDIS ( ( unsigned int ) 0x1 << 7 ) /* (TC) Counter Clock Disable with RC Compare */
1213 #define AT91C_TC_LDBDIS ( ( unsigned int ) 0x1 << 7 ) /* (TC) Counter Clock Disabled with RB Loading */
1214 #define AT91C_TC_ETRGEDG ( ( unsigned int ) 0x3 << 8 ) /* (TC) External Trigger Edge Selection */
1215 #define AT91C_TC_ETRGEDG_NONE ( ( unsigned int ) 0x0 << 8 ) /* (TC) Edge: None */
1216 #define AT91C_TC_ETRGEDG_RISING ( ( unsigned int ) 0x1 << 8 ) /* (TC) Edge: rising edge */
1217 #define AT91C_TC_ETRGEDG_FALLING ( ( unsigned int ) 0x2 << 8 ) /* (TC) Edge: falling edge */
1218 #define AT91C_TC_ETRGEDG_BOTH ( ( unsigned int ) 0x3 << 8 ) /* (TC) Edge: each edge */
1219 #define AT91C_TC_EEVTEDG ( ( unsigned int ) 0x3 << 8 ) /* (TC) External Event Edge Selection */
1220 #define AT91C_TC_EEVTEDG_NONE ( ( unsigned int ) 0x0 << 8 ) /* (TC) Edge: None */
1221 #define AT91C_TC_EEVTEDG_RISING ( ( unsigned int ) 0x1 << 8 ) /* (TC) Edge: rising edge */
1222 #define AT91C_TC_EEVTEDG_FALLING ( ( unsigned int ) 0x2 << 8 ) /* (TC) Edge: falling edge */
1223 #define AT91C_TC_EEVTEDG_BOTH ( ( unsigned int ) 0x3 << 8 ) /* (TC) Edge: each edge */
1224 #define AT91C_TC_EEVT ( ( unsigned int ) 0x3 << 10 ) /* (TC) External Event Selection */
1225 #define AT91C_TC_EEVT_TIOB ( ( unsigned int ) 0x0 << 10 ) /* (TC) Signal selected as external event: TIOB TIOB direction: input */
1226 #define AT91C_TC_EEVT_XC0 ( ( unsigned int ) 0x1 << 10 ) /* (TC) Signal selected as external event: XC0 TIOB direction: output */
1227 #define AT91C_TC_EEVT_XC1 ( ( unsigned int ) 0x2 << 10 ) /* (TC) Signal selected as external event: XC1 TIOB direction: output */
1228 #define AT91C_TC_EEVT_XC2 ( ( unsigned int ) 0x3 << 10 ) /* (TC) Signal selected as external event: XC2 TIOB direction: output */
1229 #define AT91C_TC_ABETRG ( ( unsigned int ) 0x1 << 10 ) /* (TC) TIOA or TIOB External Trigger Selection */
1230 #define AT91C_TC_ENETRG ( ( unsigned int ) 0x1 << 12 ) /* (TC) External Event Trigger enable */
1231 #define AT91C_TC_WAVESEL ( ( unsigned int ) 0x3 << 13 ) /* (TC) Waveform Selection */
1232 #define AT91C_TC_WAVESEL_UP ( ( unsigned int ) 0x0 << 13 ) /* (TC) UP mode without atomatic trigger on RC Compare */
1233 #define AT91C_TC_WAVESEL_UPDOWN ( ( unsigned int ) 0x1 << 13 ) /* (TC) UPDOWN mode without automatic trigger on RC Compare */
1234 #define AT91C_TC_WAVESEL_UP_AUTO ( ( unsigned int ) 0x2 << 13 ) /* (TC) UP mode with automatic trigger on RC Compare */
1235 #define AT91C_TC_WAVESEL_UPDOWN_AUTO ( ( unsigned int ) 0x3 << 13 ) /* (TC) UPDOWN mode with automatic trigger on RC Compare */
1236 #define AT91C_TC_CPCTRG ( ( unsigned int ) 0x1 << 14 ) /* (TC) RC Compare Trigger Enable */
1237 #define AT91C_TC_WAVE ( ( unsigned int ) 0x1 << 15 ) /* (TC) */
1238 #define AT91C_TC_ACPA ( ( unsigned int ) 0x3 << 16 ) /* (TC) RA Compare Effect on TIOA */
1239 #define AT91C_TC_ACPA_NONE ( ( unsigned int ) 0x0 << 16 ) /* (TC) Effect: none */
1240 #define AT91C_TC_ACPA_SET ( ( unsigned int ) 0x1 << 16 ) /* (TC) Effect: set */
1241 #define AT91C_TC_ACPA_CLEAR ( ( unsigned int ) 0x2 << 16 ) /* (TC) Effect: clear */
1242 #define AT91C_TC_ACPA_TOGGLE ( ( unsigned int ) 0x3 << 16 ) /* (TC) Effect: toggle */
1243 #define AT91C_TC_LDRA ( ( unsigned int ) 0x3 << 16 ) /* (TC) RA Loading Selection */
1244 #define AT91C_TC_LDRA_NONE ( ( unsigned int ) 0x0 << 16 ) /* (TC) Edge: None */
1245 #define AT91C_TC_LDRA_RISING ( ( unsigned int ) 0x1 << 16 ) /* (TC) Edge: rising edge of TIOA */
1246 #define AT91C_TC_LDRA_FALLING ( ( unsigned int ) 0x2 << 16 ) /* (TC) Edge: falling edge of TIOA */
1247 #define AT91C_TC_LDRA_BOTH ( ( unsigned int ) 0x3 << 16 ) /* (TC) Edge: each edge of TIOA */
1248 #define AT91C_TC_ACPC ( ( unsigned int ) 0x3 << 18 ) /* (TC) RC Compare Effect on TIOA */
1249 #define AT91C_TC_ACPC_NONE ( ( unsigned int ) 0x0 << 18 ) /* (TC) Effect: none */
1250 #define AT91C_TC_ACPC_SET ( ( unsigned int ) 0x1 << 18 ) /* (TC) Effect: set */
1251 #define AT91C_TC_ACPC_CLEAR ( ( unsigned int ) 0x2 << 18 ) /* (TC) Effect: clear */
1252 #define AT91C_TC_ACPC_TOGGLE ( ( unsigned int ) 0x3 << 18 ) /* (TC) Effect: toggle */
1253 #define AT91C_TC_LDRB ( ( unsigned int ) 0x3 << 18 ) /* (TC) RB Loading Selection */
1254 #define AT91C_TC_LDRB_NONE ( ( unsigned int ) 0x0 << 18 ) /* (TC) Edge: None */
1255 #define AT91C_TC_LDRB_RISING ( ( unsigned int ) 0x1 << 18 ) /* (TC) Edge: rising edge of TIOA */
1256 #define AT91C_TC_LDRB_FALLING ( ( unsigned int ) 0x2 << 18 ) /* (TC) Edge: falling edge of TIOA */
1257 #define AT91C_TC_LDRB_BOTH ( ( unsigned int ) 0x3 << 18 ) /* (TC) Edge: each edge of TIOA */
1258 #define AT91C_TC_AEEVT ( ( unsigned int ) 0x3 << 20 ) /* (TC) External Event Effect on TIOA */
1259 #define AT91C_TC_AEEVT_NONE ( ( unsigned int ) 0x0 << 20 ) /* (TC) Effect: none */
1260 #define AT91C_TC_AEEVT_SET ( ( unsigned int ) 0x1 << 20 ) /* (TC) Effect: set */
1261 #define AT91C_TC_AEEVT_CLEAR ( ( unsigned int ) 0x2 << 20 ) /* (TC) Effect: clear */
1262 #define AT91C_TC_AEEVT_TOGGLE ( ( unsigned int ) 0x3 << 20 ) /* (TC) Effect: toggle */
1263 #define AT91C_TC_ASWTRG ( ( unsigned int ) 0x3 << 22 ) /* (TC) Software Trigger Effect on TIOA */
1264 #define AT91C_TC_ASWTRG_NONE ( ( unsigned int ) 0x0 << 22 ) /* (TC) Effect: none */
1265 #define AT91C_TC_ASWTRG_SET ( ( unsigned int ) 0x1 << 22 ) /* (TC) Effect: set */
1266 #define AT91C_TC_ASWTRG_CLEAR ( ( unsigned int ) 0x2 << 22 ) /* (TC) Effect: clear */
1267 #define AT91C_TC_ASWTRG_TOGGLE ( ( unsigned int ) 0x3 << 22 ) /* (TC) Effect: toggle */
1268 #define AT91C_TC_BCPB ( ( unsigned int ) 0x3 << 24 ) /* (TC) RB Compare Effect on TIOB */
1269 #define AT91C_TC_BCPB_NONE ( ( unsigned int ) 0x0 << 24 ) /* (TC) Effect: none */
1270 #define AT91C_TC_BCPB_SET ( ( unsigned int ) 0x1 << 24 ) /* (TC) Effect: set */
1271 #define AT91C_TC_BCPB_CLEAR ( ( unsigned int ) 0x2 << 24 ) /* (TC) Effect: clear */
1272 #define AT91C_TC_BCPB_TOGGLE ( ( unsigned int ) 0x3 << 24 ) /* (TC) Effect: toggle */
1273 #define AT91C_TC_BCPC ( ( unsigned int ) 0x3 << 26 ) /* (TC) RC Compare Effect on TIOB */
1274 #define AT91C_TC_BCPC_NONE ( ( unsigned int ) 0x0 << 26 ) /* (TC) Effect: none */
1275 #define AT91C_TC_BCPC_SET ( ( unsigned int ) 0x1 << 26 ) /* (TC) Effect: set */
1276 #define AT91C_TC_BCPC_CLEAR ( ( unsigned int ) 0x2 << 26 ) /* (TC) Effect: clear */
1277 #define AT91C_TC_BCPC_TOGGLE ( ( unsigned int ) 0x3 << 26 ) /* (TC) Effect: toggle */
1278 #define AT91C_TC_BEEVT ( ( unsigned int ) 0x3 << 28 ) /* (TC) External Event Effect on TIOB */
1279 #define AT91C_TC_BEEVT_NONE ( ( unsigned int ) 0x0 << 28 ) /* (TC) Effect: none */
1280 #define AT91C_TC_BEEVT_SET ( ( unsigned int ) 0x1 << 28 ) /* (TC) Effect: set */
1281 #define AT91C_TC_BEEVT_CLEAR ( ( unsigned int ) 0x2 << 28 ) /* (TC) Effect: clear */
1282 #define AT91C_TC_BEEVT_TOGGLE ( ( unsigned int ) 0x3 << 28 ) /* (TC) Effect: toggle */
1283 #define AT91C_TC_BSWTRG ( ( unsigned int ) 0x3 << 30 ) /* (TC) Software Trigger Effect on TIOB */
1284 #define AT91C_TC_BSWTRG_NONE ( ( unsigned int ) 0x0 << 30 ) /* (TC) Effect: none */
1285 #define AT91C_TC_BSWTRG_SET ( ( unsigned int ) 0x1 << 30 ) /* (TC) Effect: set */
1286 #define AT91C_TC_BSWTRG_CLEAR ( ( unsigned int ) 0x2 << 30 ) /* (TC) Effect: clear */
1287 #define AT91C_TC_BSWTRG_TOGGLE ( ( unsigned int ) 0x3 << 30 ) /* (TC) Effect: toggle */
1288 /* -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- */
1289 #define AT91C_TC_COVFS ( ( unsigned int ) 0x1 << 0 ) /* (TC) Counter Overflow */
1290 #define AT91C_TC_LOVRS ( ( unsigned int ) 0x1 << 1 ) /* (TC) Load Overrun */
1291 #define AT91C_TC_CPAS ( ( unsigned int ) 0x1 << 2 ) /* (TC) RA Compare */
1292 #define AT91C_TC_CPBS ( ( unsigned int ) 0x1 << 3 ) /* (TC) RB Compare */
1293 #define AT91C_TC_CPCS ( ( unsigned int ) 0x1 << 4 ) /* (TC) RC Compare */
1294 #define AT91C_TC_LDRAS ( ( unsigned int ) 0x1 << 5 ) /* (TC) RA Loading */
1295 #define AT91C_TC_LDRBS ( ( unsigned int ) 0x1 << 6 ) /* (TC) RB Loading */
1296 #define AT91C_TC_ETRGS ( ( unsigned int ) 0x1 << 7 ) /* (TC) External Trigger */
1297 #define AT91C_TC_CLKSTA ( ( unsigned int ) 0x1 << 16 ) /* (TC) Clock Enabling */
1298 #define AT91C_TC_MTIOA ( ( unsigned int ) 0x1 << 17 ) /* (TC) TIOA Mirror */
1299 #define AT91C_TC_MTIOB ( ( unsigned int ) 0x1 << 18 ) /* (TC) TIOA Mirror */
1300 /* -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- */
1301 /* -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- */
1302 /* -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- */
1304 /* ***************************************************************************** */
1305 /* SOFTWARE API DEFINITION FOR Timer Counter Interface */
1306 /* ***************************************************************************** */
1307 typedef struct _AT91S_TCB
1309 AT91S_TC TCB_TC0; /* TC Channel 0 */
1310 AT91_REG Reserved0[ 4 ]; /* */
1311 AT91S_TC TCB_TC1; /* TC Channel 1 */
1312 AT91_REG Reserved1[ 4 ]; /* */
1313 AT91S_TC TCB_TC2; /* TC Channel 2 */
1314 AT91_REG Reserved2[ 4 ]; /* */
1315 AT91_REG TCB_BCR; /* TC Block Control Register */
1316 AT91_REG TCB_BMR; /* TC Block Mode Register */
1317 } AT91S_TCB, * AT91PS_TCB;
1319 /* -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- */
1320 #define AT91C_TCB_SYNC ( ( unsigned int ) 0x1 << 0 ) /* (TCB) Synchro Command */
1321 /* -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- */
1322 #define AT91C_TCB_TC0XC0S ( ( unsigned int ) 0x3 << 0 ) /* (TCB) External Clock Signal 0 Selection */
1323 #define AT91C_TCB_TC0XC0S_TCLK0 ( ( unsigned int ) 0x0 ) /* (TCB) TCLK0 connected to XC0 */
1324 #define AT91C_TCB_TC0XC0S_NONE ( ( unsigned int ) 0x1 ) /* (TCB) None signal connected to XC0 */
1325 #define AT91C_TCB_TC0XC0S_TIOA1 ( ( unsigned int ) 0x2 ) /* (TCB) TIOA1 connected to XC0 */
1326 #define AT91C_TCB_TC0XC0S_TIOA2 ( ( unsigned int ) 0x3 ) /* (TCB) TIOA2 connected to XC0 */
1327 #define AT91C_TCB_TC1XC1S ( ( unsigned int ) 0x3 << 2 ) /* (TCB) External Clock Signal 1 Selection */
1328 #define AT91C_TCB_TC1XC1S_TCLK1 ( ( unsigned int ) 0x0 << 2 ) /* (TCB) TCLK1 connected to XC1 */
1329 #define AT91C_TCB_TC1XC1S_NONE ( ( unsigned int ) 0x1 << 2 ) /* (TCB) None signal connected to XC1 */
1330 #define AT91C_TCB_TC1XC1S_TIOA0 ( ( unsigned int ) 0x2 << 2 ) /* (TCB) TIOA0 connected to XC1 */
1331 #define AT91C_TCB_TC1XC1S_TIOA2 ( ( unsigned int ) 0x3 << 2 ) /* (TCB) TIOA2 connected to XC1 */
1332 #define AT91C_TCB_TC2XC2S ( ( unsigned int ) 0x3 << 4 ) /* (TCB) External Clock Signal 2 Selection */
1333 #define AT91C_TCB_TC2XC2S_TCLK2 ( ( unsigned int ) 0x0 << 4 ) /* (TCB) TCLK2 connected to XC2 */
1334 #define AT91C_TCB_TC2XC2S_NONE ( ( unsigned int ) 0x1 << 4 ) /* (TCB) None signal connected to XC2 */
1335 #define AT91C_TCB_TC2XC2S_TIOA0 ( ( unsigned int ) 0x2 << 4 ) /* (TCB) TIOA0 connected to XC2 */
1336 #define AT91C_TCB_TC2XC2S_TIOA1 ( ( unsigned int ) 0x3 << 4 ) /* (TCB) TIOA2 connected to XC2 */
1338 /* ***************************************************************************** */
1339 /* SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface */
1340 /* ***************************************************************************** */
1341 typedef struct _AT91S_CAN_MB
1343 AT91_REG CAN_MB_MMR; /* MailBox Mode Register */
1344 AT91_REG CAN_MB_MAM; /* MailBox Acceptance Mask Register */
1345 AT91_REG CAN_MB_MID; /* MailBox ID Register */
1346 AT91_REG CAN_MB_MFID; /* MailBox Family ID Register */
1347 AT91_REG CAN_MB_MSR; /* MailBox Status Register */
1348 AT91_REG CAN_MB_MDL; /* MailBox Data Low Register */
1349 AT91_REG CAN_MB_MDH; /* MailBox Data High Register */
1350 AT91_REG CAN_MB_MCR; /* MailBox Control Register */
1351 } AT91S_CAN_MB, * AT91PS_CAN_MB;
1353 /* -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- */
1354 #define AT91C_CAN_MTIMEMARK ( ( unsigned int ) 0xFFFF << 0 ) /* (CAN_MB) Mailbox Timemark */
1355 #define AT91C_CAN_PRIOR ( ( unsigned int ) 0xF << 16 ) /* (CAN_MB) Mailbox Priority */
1356 #define AT91C_CAN_MOT ( ( unsigned int ) 0x7 << 24 ) /* (CAN_MB) Mailbox Object Type */
1357 #define AT91C_CAN_MOT_DIS ( ( unsigned int ) 0x0 << 24 ) /* (CAN_MB) */
1358 #define AT91C_CAN_MOT_RX ( ( unsigned int ) 0x1 << 24 ) /* (CAN_MB) */
1359 #define AT91C_CAN_MOT_RXOVERWRITE ( ( unsigned int ) 0x2 << 24 ) /* (CAN_MB) */
1360 #define AT91C_CAN_MOT_TX ( ( unsigned int ) 0x3 << 24 ) /* (CAN_MB) */
1361 #define AT91C_CAN_MOT_CONSUMER ( ( unsigned int ) 0x4 << 24 ) /* (CAN_MB) */
1362 #define AT91C_CAN_MOT_PRODUCER ( ( unsigned int ) 0x5 << 24 ) /* (CAN_MB) */
1363 /* -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- */
1364 #define AT91C_CAN_MIDvB ( ( unsigned int ) 0x3FFFF << 0 ) /* (CAN_MB) Complementary bits for identifier in extended mode */
1365 #define AT91C_CAN_MIDvA ( ( unsigned int ) 0x7FF << 18 ) /* (CAN_MB) Identifier for standard frame mode */
1366 #define AT91C_CAN_MIDE ( ( unsigned int ) 0x1 << 29 ) /* (CAN_MB) Identifier Version */
1367 /* -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- */
1368 /* -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- */
1369 /* -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- */
1370 #define AT91C_CAN_MTIMESTAMP ( ( unsigned int ) 0xFFFF << 0 ) /* (CAN_MB) Timer Value */
1371 #define AT91C_CAN_MDLC ( ( unsigned int ) 0xF << 16 ) /* (CAN_MB) Mailbox Data Length Code */
1372 #define AT91C_CAN_MRTR ( ( unsigned int ) 0x1 << 20 ) /* (CAN_MB) Mailbox Remote Transmission Request */
1373 #define AT91C_CAN_MABT ( ( unsigned int ) 0x1 << 22 ) /* (CAN_MB) Mailbox Message Abort */
1374 #define AT91C_CAN_MRDY ( ( unsigned int ) 0x1 << 23 ) /* (CAN_MB) Mailbox Ready */
1375 #define AT91C_CAN_MMI ( ( unsigned int ) 0x1 << 24 ) /* (CAN_MB) Mailbox Message Ignored */
1376 /* -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- */
1377 /* -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- */
1378 /* -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- */
1379 #define AT91C_CAN_MACR ( ( unsigned int ) 0x1 << 22 ) /* (CAN_MB) Abort Request for Mailbox */
1380 #define AT91C_CAN_MTCR ( ( unsigned int ) 0x1 << 23 ) /* (CAN_MB) Mailbox Transfer Command */
1382 /* ***************************************************************************** */
1383 /* SOFTWARE API DEFINITION FOR Control Area Network Interface */
1384 /* ***************************************************************************** */
1385 typedef struct _AT91S_CAN
1387 AT91_REG CAN_MR; /* Mode Register */
1388 AT91_REG CAN_IER; /* Interrupt Enable Register */
1389 AT91_REG CAN_IDR; /* Interrupt Disable Register */
1390 AT91_REG CAN_IMR; /* Interrupt Mask Register */
1391 AT91_REG CAN_SR; /* Status Register */
1392 AT91_REG CAN_BR; /* Baudrate Register */
1393 AT91_REG CAN_TIM; /* Timer Register */
1394 AT91_REG CAN_TIMESTP; /* Time Stamp Register */
1395 AT91_REG CAN_ECR; /* Error Counter Register */
1396 AT91_REG CAN_TCR; /* Transfer Command Register */
1397 AT91_REG CAN_ACR; /* Abort Command Register */
1398 AT91_REG Reserved0[ 52 ]; /* */
1399 AT91_REG CAN_VR; /* Version Register */
1400 AT91_REG Reserved1[ 64 ]; /* */
1401 AT91S_CAN_MB CAN_MB0; /* CAN Mailbox 0 */
1402 AT91S_CAN_MB CAN_MB1; /* CAN Mailbox 1 */
1403 AT91S_CAN_MB CAN_MB2; /* CAN Mailbox 2 */
1404 AT91S_CAN_MB CAN_MB3; /* CAN Mailbox 3 */
1405 AT91S_CAN_MB CAN_MB4; /* CAN Mailbox 4 */
1406 AT91S_CAN_MB CAN_MB5; /* CAN Mailbox 5 */
1407 AT91S_CAN_MB CAN_MB6; /* CAN Mailbox 6 */
1408 AT91S_CAN_MB CAN_MB7; /* CAN Mailbox 7 */
1409 AT91S_CAN_MB CAN_MB8; /* CAN Mailbox 8 */
1410 AT91S_CAN_MB CAN_MB9; /* CAN Mailbox 9 */
1411 AT91S_CAN_MB CAN_MB10; /* CAN Mailbox 10 */
1412 AT91S_CAN_MB CAN_MB11; /* CAN Mailbox 11 */
1413 AT91S_CAN_MB CAN_MB12; /* CAN Mailbox 12 */
1414 AT91S_CAN_MB CAN_MB13; /* CAN Mailbox 13 */
1415 AT91S_CAN_MB CAN_MB14; /* CAN Mailbox 14 */
1416 AT91S_CAN_MB CAN_MB15; /* CAN Mailbox 15 */
1417 } AT91S_CAN, * AT91PS_CAN;
1419 /* -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- */
1420 #define AT91C_CAN_CANEN ( ( unsigned int ) 0x1 << 0 ) /* (CAN) CAN Controller Enable */
1421 #define AT91C_CAN_LPM ( ( unsigned int ) 0x1 << 1 ) /* (CAN) Disable/Enable Low Power Mode */
1422 #define AT91C_CAN_ABM ( ( unsigned int ) 0x1 << 2 ) /* (CAN) Disable/Enable Autobaud/Listen Mode */
1423 #define AT91C_CAN_OVL ( ( unsigned int ) 0x1 << 3 ) /* (CAN) Disable/Enable Overload Frame */
1424 #define AT91C_CAN_TEOF ( ( unsigned int ) 0x1 << 4 ) /* (CAN) Time Stamp messages at each end of Frame */
1425 #define AT91C_CAN_TTM ( ( unsigned int ) 0x1 << 5 ) /* (CAN) Disable/Enable Time Trigger Mode */
1426 #define AT91C_CAN_TIMFRZ ( ( unsigned int ) 0x1 << 6 ) /* (CAN) Enable Timer Freeze */
1427 #define AT91C_CAN_DRPT ( ( unsigned int ) 0x1 << 7 ) /* (CAN) Disable Repeat */
1428 /* -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- */
1429 #define AT91C_CAN_MB0 ( ( unsigned int ) 0x1 << 0 ) /* (CAN) Mailbox 0 Flag */
1430 #define AT91C_CAN_MB1 ( ( unsigned int ) 0x1 << 1 ) /* (CAN) Mailbox 1 Flag */
1431 #define AT91C_CAN_MB2 ( ( unsigned int ) 0x1 << 2 ) /* (CAN) Mailbox 2 Flag */
1432 #define AT91C_CAN_MB3 ( ( unsigned int ) 0x1 << 3 ) /* (CAN) Mailbox 3 Flag */
1433 #define AT91C_CAN_MB4 ( ( unsigned int ) 0x1 << 4 ) /* (CAN) Mailbox 4 Flag */
1434 #define AT91C_CAN_MB5 ( ( unsigned int ) 0x1 << 5 ) /* (CAN) Mailbox 5 Flag */
1435 #define AT91C_CAN_MB6 ( ( unsigned int ) 0x1 << 6 ) /* (CAN) Mailbox 6 Flag */
1436 #define AT91C_CAN_MB7 ( ( unsigned int ) 0x1 << 7 ) /* (CAN) Mailbox 7 Flag */
1437 #define AT91C_CAN_MB8 ( ( unsigned int ) 0x1 << 8 ) /* (CAN) Mailbox 8 Flag */
1438 #define AT91C_CAN_MB9 ( ( unsigned int ) 0x1 << 9 ) /* (CAN) Mailbox 9 Flag */
1439 #define AT91C_CAN_MB10 ( ( unsigned int ) 0x1 << 10 ) /* (CAN) Mailbox 10 Flag */
1440 #define AT91C_CAN_MB11 ( ( unsigned int ) 0x1 << 11 ) /* (CAN) Mailbox 11 Flag */
1441 #define AT91C_CAN_MB12 ( ( unsigned int ) 0x1 << 12 ) /* (CAN) Mailbox 12 Flag */
1442 #define AT91C_CAN_MB13 ( ( unsigned int ) 0x1 << 13 ) /* (CAN) Mailbox 13 Flag */
1443 #define AT91C_CAN_MB14 ( ( unsigned int ) 0x1 << 14 ) /* (CAN) Mailbox 14 Flag */
1444 #define AT91C_CAN_MB15 ( ( unsigned int ) 0x1 << 15 ) /* (CAN) Mailbox 15 Flag */
1445 #define AT91C_CAN_ERRA ( ( unsigned int ) 0x1 << 16 ) /* (CAN) Error Active Mode Flag */
1446 #define AT91C_CAN_WARN ( ( unsigned int ) 0x1 << 17 ) /* (CAN) Warning Limit Flag */
1447 #define AT91C_CAN_ERRP ( ( unsigned int ) 0x1 << 18 ) /* (CAN) Error Passive Mode Flag */
1448 #define AT91C_CAN_BOFF ( ( unsigned int ) 0x1 << 19 ) /* (CAN) Bus Off Mode Flag */
1449 #define AT91C_CAN_SLEEP ( ( unsigned int ) 0x1 << 20 ) /* (CAN) Sleep Flag */
1450 #define AT91C_CAN_WAKEUP ( ( unsigned int ) 0x1 << 21 ) /* (CAN) Wakeup Flag */
1451 #define AT91C_CAN_TOVF ( ( unsigned int ) 0x1 << 22 ) /* (CAN) Timer Overflow Flag */
1452 #define AT91C_CAN_TSTP ( ( unsigned int ) 0x1 << 23 ) /* (CAN) Timestamp Flag */
1453 #define AT91C_CAN_CERR ( ( unsigned int ) 0x1 << 24 ) /* (CAN) CRC Error */
1454 #define AT91C_CAN_SERR ( ( unsigned int ) 0x1 << 25 ) /* (CAN) Stuffing Error */
1455 #define AT91C_CAN_AERR ( ( unsigned int ) 0x1 << 26 ) /* (CAN) Acknowledgment Error */
1456 #define AT91C_CAN_FERR ( ( unsigned int ) 0x1 << 27 ) /* (CAN) Form Error */
1457 #define AT91C_CAN_BERR ( ( unsigned int ) 0x1 << 28 ) /* (CAN) Bit Error */
1458 /* -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- */
1459 /* -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- */
1460 /* -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- */
1461 #define AT91C_CAN_RBSY ( ( unsigned int ) 0x1 << 29 ) /* (CAN) Receiver Busy */
1462 #define AT91C_CAN_TBSY ( ( unsigned int ) 0x1 << 30 ) /* (CAN) Transmitter Busy */
1463 #define AT91C_CAN_OVLY ( ( unsigned int ) 0x1 << 31 ) /* (CAN) Overload Busy */
1464 /* -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- */
1465 #define AT91C_CAN_PHASE2 ( ( unsigned int ) 0x7 << 0 ) /* (CAN) Phase 2 segment */
1466 #define AT91C_CAN_PHASE1 ( ( unsigned int ) 0x7 << 4 ) /* (CAN) Phase 1 segment */
1467 #define AT91C_CAN_PROPAG ( ( unsigned int ) 0x7 << 8 ) /* (CAN) Programmation time segment */
1468 #define AT91C_CAN_SYNC ( ( unsigned int ) 0x3 << 12 ) /* (CAN) Re-synchronization jump width segment */
1469 #define AT91C_CAN_BRP ( ( unsigned int ) 0x7F << 16 ) /* (CAN) Baudrate Prescaler */
1470 #define AT91C_CAN_SMP ( ( unsigned int ) 0x1 << 24 ) /* (CAN) Sampling mode */
1471 /* -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- */
1472 #define AT91C_CAN_TIMER ( ( unsigned int ) 0xFFFF << 0 ) /* (CAN) Timer field */
1473 /* -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- */
1474 /* -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- */
1475 #define AT91C_CAN_REC ( ( unsigned int ) 0xFF << 0 ) /* (CAN) Receive Error Counter */
1476 #define AT91C_CAN_TEC ( ( unsigned int ) 0xFF << 16 ) /* (CAN) Transmit Error Counter */
1477 /* -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- */
1478 #define AT91C_CAN_TIMRST ( ( unsigned int ) 0x1 << 31 ) /* (CAN) Timer Reset Field */
1479 /* -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- */
1481 /* ***************************************************************************** */
1482 /* SOFTWARE API DEFINITION FOR Ethernet MAC 10/100 */
1483 /* ***************************************************************************** */
1484 typedef struct _AT91S_EMAC
1486 AT91_REG EMAC_NCR; /* Network Control Register */
1487 AT91_REG EMAC_NCFGR; /* Network Configuration Register */
1488 AT91_REG EMAC_NSR; /* Network Status Register */
1489 AT91_REG Reserved0[ 2 ]; /* */
1490 AT91_REG EMAC_TSR; /* Transmit Status Register */
1491 AT91_REG EMAC_RBQP; /* Receive Buffer Queue Pointer */
1492 AT91_REG EMAC_TBQP; /* Transmit Buffer Queue Pointer */
1493 AT91_REG EMAC_RSR; /* Receive Status Register */
1494 AT91_REG EMAC_ISR; /* Interrupt Status Register */
1495 AT91_REG EMAC_IER; /* Interrupt Enable Register */
1496 AT91_REG EMAC_IDR; /* Interrupt Disable Register */
1497 AT91_REG EMAC_IMR; /* Interrupt Mask Register */
1498 AT91_REG EMAC_MAN; /* PHY Maintenance Register */
1499 AT91_REG EMAC_PTR; /* Pause Time Register */
1500 AT91_REG EMAC_PFR; /* Pause Frames received Register */
1501 AT91_REG EMAC_FTO; /* Frames Transmitted OK Register */
1502 AT91_REG EMAC_SCF; /* Single Collision Frame Register */
1503 AT91_REG EMAC_MCF; /* Multiple Collision Frame Register */
1504 AT91_REG EMAC_FRO; /* Frames Received OK Register */
1505 AT91_REG EMAC_FCSE; /* Frame Check Sequence Error Register */
1506 AT91_REG EMAC_ALE; /* Alignment Error Register */
1507 AT91_REG EMAC_DTF; /* Deferred Transmission Frame Register */
1508 AT91_REG EMAC_LCOL; /* Late Collision Register */
1509 AT91_REG EMAC_ECOL; /* Excessive Collision Register */
1510 AT91_REG EMAC_TUND; /* Transmit Underrun Error Register */
1511 AT91_REG EMAC_CSE; /* Carrier Sense Error Register */
1512 AT91_REG EMAC_RRE; /* Receive Resource Error Register */
1513 AT91_REG EMAC_ROV; /* Receive Overrun Errors Register */
1514 AT91_REG EMAC_RSE; /* Receive Symbol Errors Register */
1515 AT91_REG EMAC_ELE; /* Excessive Length Errors Register */
1516 AT91_REG EMAC_RJA; /* Receive Jabbers Register */
1517 AT91_REG EMAC_USF; /* Undersize Frames Register */
1518 AT91_REG EMAC_STE; /* SQE Test Error Register */
1519 AT91_REG EMAC_RLE; /* Receive Length Field Mismatch Register */
1520 AT91_REG EMAC_TPF; /* Transmitted Pause Frames Register */
1521 AT91_REG EMAC_HRB; /* Hash Address Bottom[31:0] */
1522 AT91_REG EMAC_HRT; /* Hash Address Top[63:32] */
1523 AT91_REG EMAC_SA1L; /* Specific Address 1 Bottom, First 4 bytes */
1524 AT91_REG EMAC_SA1H; /* Specific Address 1 Top, Last 2 bytes */
1525 AT91_REG EMAC_SA2L; /* Specific Address 2 Bottom, First 4 bytes */
1526 AT91_REG EMAC_SA2H; /* Specific Address 2 Top, Last 2 bytes */
1527 AT91_REG EMAC_SA3L; /* Specific Address 3 Bottom, First 4 bytes */
1528 AT91_REG EMAC_SA3H; /* Specific Address 3 Top, Last 2 bytes */
1529 AT91_REG EMAC_SA4L; /* Specific Address 4 Bottom, First 4 bytes */
1530 AT91_REG EMAC_SA4H; /* Specific Address 4 Top, Last 2 bytes */
1531 AT91_REG EMAC_TID; /* Type ID Checking Register */
1532 AT91_REG EMAC_TPQ; /* Transmit Pause Quantum Register */
1533 AT91_REG EMAC_USRIO; /* USER Input/Output Register */
1534 AT91_REG EMAC_WOL; /* Wake On LAN Register */
1535 AT91_REG Reserved1[ 13 ]; /* */
1536 AT91_REG EMAC_REV; /* Revision Register */
1537 } AT91S_EMAC, * AT91PS_EMAC;
1539 /* -------- EMAC_NCR : (EMAC Offset: 0x0) -------- */
1540 #define AT91C_EMAC_LB ( ( unsigned int ) 0x1 << 0 ) /* (EMAC) Loopback. Optional. When set, loopback signal is at high level. */
1541 #define AT91C_EMAC_LLB ( ( unsigned int ) 0x1 << 1 ) /* (EMAC) Loopback local. */
1542 #define AT91C_EMAC_RE ( ( unsigned int ) 0x1 << 2 ) /* (EMAC) Receive enable. */
1543 #define AT91C_EMAC_TE ( ( unsigned int ) 0x1 << 3 ) /* (EMAC) Transmit enable. */
1544 #define AT91C_EMAC_MPE ( ( unsigned int ) 0x1 << 4 ) /* (EMAC) Management port enable. */
1545 #define AT91C_EMAC_CLRSTAT ( ( unsigned int ) 0x1 << 5 ) /* (EMAC) Clear statistics registers. */
1546 #define AT91C_EMAC_INCSTAT ( ( unsigned int ) 0x1 << 6 ) /* (EMAC) Increment statistics registers. */
1547 #define AT91C_EMAC_WESTAT ( ( unsigned int ) 0x1 << 7 ) /* (EMAC) Write enable for statistics registers. */
1548 #define AT91C_EMAC_BP ( ( unsigned int ) 0x1 << 8 ) /* (EMAC) Back pressure. */
1549 #define AT91C_EMAC_TSTART ( ( unsigned int ) 0x1 << 9 ) /* (EMAC) Start Transmission. */
1550 #define AT91C_EMAC_THALT ( ( unsigned int ) 0x1 << 10 ) /* (EMAC) Transmission Halt. */
1551 #define AT91C_EMAC_TPFR ( ( unsigned int ) 0x1 << 11 ) /* (EMAC) Transmit pause frame */
1552 #define AT91C_EMAC_TZQ ( ( unsigned int ) 0x1 << 12 ) /* (EMAC) Transmit zero quantum pause frame */
1553 /* -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- */
1554 #define AT91C_EMAC_SPD ( ( unsigned int ) 0x1 << 0 ) /* (EMAC) Speed. */
1555 #define AT91C_EMAC_FD ( ( unsigned int ) 0x1 << 1 ) /* (EMAC) Full duplex. */
1556 #define AT91C_EMAC_JFRAME ( ( unsigned int ) 0x1 << 3 ) /* (EMAC) Jumbo Frames. */
1557 #define AT91C_EMAC_CAF ( ( unsigned int ) 0x1 << 4 ) /* (EMAC) Copy all frames. */
1558 #define AT91C_EMAC_NBC ( ( unsigned int ) 0x1 << 5 ) /* (EMAC) No broadcast. */
1559 #define AT91C_EMAC_MTI ( ( unsigned int ) 0x1 << 6 ) /* (EMAC) Multicast hash event enable */
1560 #define AT91C_EMAC_UNI ( ( unsigned int ) 0x1 << 7 ) /* (EMAC) Unicast hash enable. */
1561 #define AT91C_EMAC_BIG ( ( unsigned int ) 0x1 << 8 ) /* (EMAC) Receive 1522 bytes. */
1562 #define AT91C_EMAC_EAE ( ( unsigned int ) 0x1 << 9 ) /* (EMAC) External address match enable. */
1563 #define AT91C_EMAC_CLK ( ( unsigned int ) 0x3 << 10 ) /* (EMAC) */
1564 #define AT91C_EMAC_CLK_HCLK_8 ( ( unsigned int ) 0x0 << 10 ) /* (EMAC) HCLK divided by 8 */
1565 #define AT91C_EMAC_CLK_HCLK_16 ( ( unsigned int ) 0x1 << 10 ) /* (EMAC) HCLK divided by 16 */
1566 #define AT91C_EMAC_CLK_HCLK_32 ( ( unsigned int ) 0x2 << 10 ) /* (EMAC) HCLK divided by 32 */
1567 #define AT91C_EMAC_CLK_HCLK_64 ( ( unsigned int ) 0x3 << 10 ) /* (EMAC) HCLK divided by 64 */
1568 #define AT91C_EMAC_RTY ( ( unsigned int ) 0x1 << 12 ) /* (EMAC) */
1569 #define AT91C_EMAC_PAE ( ( unsigned int ) 0x1 << 13 ) /* (EMAC) */
1570 #define AT91C_EMAC_RBOF ( ( unsigned int ) 0x3 << 14 ) /* (EMAC) */
1571 #define AT91C_EMAC_RBOF_OFFSET_0 ( ( unsigned int ) 0x0 << 14 ) /* (EMAC) no offset from start of receive buffer */
1572 #define AT91C_EMAC_RBOF_OFFSET_1 ( ( unsigned int ) 0x1 << 14 ) /* (EMAC) one byte offset from start of receive buffer */
1573 #define AT91C_EMAC_RBOF_OFFSET_2 ( ( unsigned int ) 0x2 << 14 ) /* (EMAC) two bytes offset from start of receive buffer */
1574 #define AT91C_EMAC_RBOF_OFFSET_3 ( ( unsigned int ) 0x3 << 14 ) /* (EMAC) three bytes offset from start of receive buffer */
1575 #define AT91C_EMAC_RLCE ( ( unsigned int ) 0x1 << 16 ) /* (EMAC) Receive Length field Checking Enable */
1576 #define AT91C_EMAC_DRFCS ( ( unsigned int ) 0x1 << 17 ) /* (EMAC) Discard Receive FCS */
1577 #define AT91C_EMAC_EFRHD ( ( unsigned int ) 0x1 << 18 ) /* (EMAC) */
1578 #define AT91C_EMAC_IRXFCS ( ( unsigned int ) 0x1 << 19 ) /* (EMAC) Ignore RX FCS */
1579 /* -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- */
1580 #define AT91C_EMAC_LINKR ( ( unsigned int ) 0x1 << 0 ) /* (EMAC) */
1581 #define AT91C_EMAC_MDIO ( ( unsigned int ) 0x1 << 1 ) /* (EMAC) */
1582 #define AT91C_EMAC_IDLE ( ( unsigned int ) 0x1 << 2 ) /* (EMAC) */
1583 /* -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- */
1584 #define AT91C_EMAC_UBR ( ( unsigned int ) 0x1 << 0 ) /* (EMAC) */
1585 #define AT91C_EMAC_COL ( ( unsigned int ) 0x1 << 1 ) /* (EMAC) */
1586 #define AT91C_EMAC_RLES ( ( unsigned int ) 0x1 << 2 ) /* (EMAC) */
1587 #define AT91C_EMAC_TGO ( ( unsigned int ) 0x1 << 3 ) /* (EMAC) Transmit Go */
1588 #define AT91C_EMAC_BEX ( ( unsigned int ) 0x1 << 4 ) /* (EMAC) Buffers exhausted mid frame */
1589 #define AT91C_EMAC_COMP ( ( unsigned int ) 0x1 << 5 ) /* (EMAC) */
1590 #define AT91C_EMAC_UND ( ( unsigned int ) 0x1 << 6 ) /* (EMAC) */
1591 /* -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- */
1592 #define AT91C_EMAC_BNA ( ( unsigned int ) 0x1 << 0 ) /* (EMAC) */
1593 #define AT91C_EMAC_REC ( ( unsigned int ) 0x1 << 1 ) /* (EMAC) */
1594 #define AT91C_EMAC_OVR ( ( unsigned int ) 0x1 << 2 ) /* (EMAC) */
1595 /* -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- */
1596 #define AT91C_EMAC_MFD ( ( unsigned int ) 0x1 << 0 ) /* (EMAC) */
1597 #define AT91C_EMAC_RCOMP ( ( unsigned int ) 0x1 << 1 ) /* (EMAC) */
1598 #define AT91C_EMAC_RXUBR ( ( unsigned int ) 0x1 << 2 ) /* (EMAC) */
1599 #define AT91C_EMAC_TXUBR ( ( unsigned int ) 0x1 << 3 ) /* (EMAC) */
1600 #define AT91C_EMAC_TUNDR ( ( unsigned int ) 0x1 << 4 ) /* (EMAC) */
1601 #define AT91C_EMAC_RLEX ( ( unsigned int ) 0x1 << 5 ) /* (EMAC) */
1602 #define AT91C_EMAC_TXERR ( ( unsigned int ) 0x1 << 6 ) /* (EMAC) */
1603 #define AT91C_EMAC_TCOMP ( ( unsigned int ) 0x1 << 7 ) /* (EMAC) */
1604 #define AT91C_EMAC_LINK ( ( unsigned int ) 0x1 << 9 ) /* (EMAC) */
1605 #define AT91C_EMAC_ROVR ( ( unsigned int ) 0x1 << 10 ) /* (EMAC) */
1606 #define AT91C_EMAC_HRESP ( ( unsigned int ) 0x1 << 11 ) /* (EMAC) */
1607 #define AT91C_EMAC_PFRE ( ( unsigned int ) 0x1 << 12 ) /* (EMAC) */
1608 #define AT91C_EMAC_PTZ ( ( unsigned int ) 0x1 << 13 ) /* (EMAC) */
1609 /* -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- */
1610 /* -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- */
1611 /* -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- */
1612 /* -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- */
1613 #define AT91C_EMAC_DATA ( ( unsigned int ) 0xFFFF << 0 ) /* (EMAC) */
1614 #define AT91C_EMAC_CODE ( ( unsigned int ) 0x3 << 16 ) /* (EMAC) */
1615 #define AT91C_EMAC_REGA ( ( unsigned int ) 0x1F << 18 ) /* (EMAC) */
1616 #define AT91C_EMAC_PHYA ( ( unsigned int ) 0x1F << 23 ) /* (EMAC) */
1617 #define AT91C_EMAC_RW ( ( unsigned int ) 0x3 << 28 ) /* (EMAC) */
1618 #define AT91C_EMAC_SOF ( ( unsigned int ) 0x3 << 30 ) /* (EMAC) */
1619 /* -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- */
1620 #define AT91C_EMAC_RMII ( ( unsigned int ) 0x1 << 0 ) /* (EMAC) Reduce MII */
1621 /* -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- */
1622 #define AT91C_EMAC_IP ( ( unsigned int ) 0xFFFF << 0 ) /* (EMAC) ARP request IP address */
1623 #define AT91C_EMAC_MAG ( ( unsigned int ) 0x1 << 16 ) /* (EMAC) Magic packet event enable */
1624 #define AT91C_EMAC_ARP ( ( unsigned int ) 0x1 << 17 ) /* (EMAC) ARP request event enable */
1625 #define AT91C_EMAC_SA1 ( ( unsigned int ) 0x1 << 18 ) /* (EMAC) Specific address register 1 event enable */
1626 /* -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- */
1627 #define AT91C_EMAC_REVREF ( ( unsigned int ) 0xFFFF << 0 ) /* (EMAC) */
1628 #define AT91C_EMAC_PARTREF ( ( unsigned int ) 0xFFFF << 16 ) /* (EMAC) */
1630 /* ***************************************************************************** */
1631 /* SOFTWARE API DEFINITION FOR Analog to Digital Convertor */
1632 /* ***************************************************************************** */
1633 typedef struct _AT91S_ADC
1635 AT91_REG ADC_CR; /* ADC Control Register */
1636 AT91_REG ADC_MR; /* ADC Mode Register */
1637 AT91_REG Reserved0[ 2 ]; /* */
1638 AT91_REG ADC_CHER; /* ADC Channel Enable Register */
1639 AT91_REG ADC_CHDR; /* ADC Channel Disable Register */
1640 AT91_REG ADC_CHSR; /* ADC Channel Status Register */
1641 AT91_REG ADC_SR; /* ADC Status Register */
1642 AT91_REG ADC_LCDR; /* ADC Last Converted Data Register */
1643 AT91_REG ADC_IER; /* ADC Interrupt Enable Register */
1644 AT91_REG ADC_IDR; /* ADC Interrupt Disable Register */
1645 AT91_REG ADC_IMR; /* ADC Interrupt Mask Register */
1646 AT91_REG ADC_CDR0; /* ADC Channel Data Register 0 */
1647 AT91_REG ADC_CDR1; /* ADC Channel Data Register 1 */
1648 AT91_REG ADC_CDR2; /* ADC Channel Data Register 2 */
1649 AT91_REG ADC_CDR3; /* ADC Channel Data Register 3 */
1650 AT91_REG ADC_CDR4; /* ADC Channel Data Register 4 */
1651 AT91_REG ADC_CDR5; /* ADC Channel Data Register 5 */
1652 AT91_REG ADC_CDR6; /* ADC Channel Data Register 6 */
1653 AT91_REG ADC_CDR7; /* ADC Channel Data Register 7 */
1654 AT91_REG Reserved1[ 44 ]; /* */
1655 AT91_REG ADC_RPR; /* Receive Pointer Register */
1656 AT91_REG ADC_RCR; /* Receive Counter Register */
1657 AT91_REG ADC_TPR; /* Transmit Pointer Register */
1658 AT91_REG ADC_TCR; /* Transmit Counter Register */
1659 AT91_REG ADC_RNPR; /* Receive Next Pointer Register */
1660 AT91_REG ADC_RNCR; /* Receive Next Counter Register */
1661 AT91_REG ADC_TNPR; /* Transmit Next Pointer Register */
1662 AT91_REG ADC_TNCR; /* Transmit Next Counter Register */
1663 AT91_REG ADC_PTCR; /* PDC Transfer Control Register */
1664 AT91_REG ADC_PTSR; /* PDC Transfer Status Register */
1665 } AT91S_ADC, * AT91PS_ADC;
1667 /* -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- */
1668 #define AT91C_ADC_SWRST ( ( unsigned int ) 0x1 << 0 ) /* (ADC) Software Reset */
1669 #define AT91C_ADC_START ( ( unsigned int ) 0x1 << 1 ) /* (ADC) Start Conversion */
1670 /* -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- */
1671 #define AT91C_ADC_TRGEN ( ( unsigned int ) 0x1 << 0 ) /* (ADC) Trigger Enable */
1672 #define AT91C_ADC_TRGEN_DIS ( ( unsigned int ) 0x0 ) /* (ADC) Hardware triggers are disabled. Starting a conversion is only possible by software */
1673 #define AT91C_ADC_TRGEN_EN ( ( unsigned int ) 0x1 ) /* (ADC) Hardware trigger selected by TRGSEL field is enabled. */
1674 #define AT91C_ADC_TRGSEL ( ( unsigned int ) 0x7 << 1 ) /* (ADC) Trigger Selection */
1675 #define AT91C_ADC_TRGSEL_TIOA0 ( ( unsigned int ) 0x0 << 1 ) /* (ADC) Selected TRGSEL = TIAO0 */
1676 #define AT91C_ADC_TRGSEL_TIOA1 ( ( unsigned int ) 0x1 << 1 ) /* (ADC) Selected TRGSEL = TIAO1 */
1677 #define AT91C_ADC_TRGSEL_TIOA2 ( ( unsigned int ) 0x2 << 1 ) /* (ADC) Selected TRGSEL = TIAO2 */
1678 #define AT91C_ADC_TRGSEL_TIOA3 ( ( unsigned int ) 0x3 << 1 ) /* (ADC) Selected TRGSEL = TIAO3 */
1679 #define AT91C_ADC_TRGSEL_TIOA4 ( ( unsigned int ) 0x4 << 1 ) /* (ADC) Selected TRGSEL = TIAO4 */
1680 #define AT91C_ADC_TRGSEL_TIOA5 ( ( unsigned int ) 0x5 << 1 ) /* (ADC) Selected TRGSEL = TIAO5 */
1681 #define AT91C_ADC_TRGSEL_EXT ( ( unsigned int ) 0x6 << 1 ) /* (ADC) Selected TRGSEL = External Trigger */
1682 #define AT91C_ADC_LOWRES ( ( unsigned int ) 0x1 << 4 ) /* (ADC) Resolution. */
1683 #define AT91C_ADC_LOWRES_10_BIT ( ( unsigned int ) 0x0 << 4 ) /* (ADC) 10-bit resolution */
1684 #define AT91C_ADC_LOWRES_8_BIT ( ( unsigned int ) 0x1 << 4 ) /* (ADC) 8-bit resolution */
1685 #define AT91C_ADC_SLEEP ( ( unsigned int ) 0x1 << 5 ) /* (ADC) Sleep Mode */
1686 #define AT91C_ADC_SLEEP_NORMAL_MODE ( ( unsigned int ) 0x0 << 5 ) /* (ADC) Normal Mode */
1687 #define AT91C_ADC_SLEEP_MODE ( ( unsigned int ) 0x1 << 5 ) /* (ADC) Sleep Mode */
1688 #define AT91C_ADC_PRESCAL ( ( unsigned int ) 0x3F << 8 ) /* (ADC) Prescaler rate selection */
1689 #define AT91C_ADC_STARTUP ( ( unsigned int ) 0x1F << 16 ) /* (ADC) Startup Time */
1690 #define AT91C_ADC_SHTIM ( ( unsigned int ) 0xF << 24 ) /* (ADC) Sample & Hold Time */
1691 /* -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- */
1692 #define AT91C_ADC_CH0 ( ( unsigned int ) 0x1 << 0 ) /* (ADC) Channel 0 */
1693 #define AT91C_ADC_CH1 ( ( unsigned int ) 0x1 << 1 ) /* (ADC) Channel 1 */
1694 #define AT91C_ADC_CH2 ( ( unsigned int ) 0x1 << 2 ) /* (ADC) Channel 2 */
1695 #define AT91C_ADC_CH3 ( ( unsigned int ) 0x1 << 3 ) /* (ADC) Channel 3 */
1696 #define AT91C_ADC_CH4 ( ( unsigned int ) 0x1 << 4 ) /* (ADC) Channel 4 */
1697 #define AT91C_ADC_CH5 ( ( unsigned int ) 0x1 << 5 ) /* (ADC) Channel 5 */
1698 #define AT91C_ADC_CH6 ( ( unsigned int ) 0x1 << 6 ) /* (ADC) Channel 6 */
1699 #define AT91C_ADC_CH7 ( ( unsigned int ) 0x1 << 7 ) /* (ADC) Channel 7 */
1700 /* -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- */
1701 /* -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- */
1702 /* -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- */
1703 #define AT91C_ADC_EOC0 ( ( unsigned int ) 0x1 << 0 ) /* (ADC) End of Conversion */
1704 #define AT91C_ADC_EOC1 ( ( unsigned int ) 0x1 << 1 ) /* (ADC) End of Conversion */
1705 #define AT91C_ADC_EOC2 ( ( unsigned int ) 0x1 << 2 ) /* (ADC) End of Conversion */
1706 #define AT91C_ADC_EOC3 ( ( unsigned int ) 0x1 << 3 ) /* (ADC) End of Conversion */
1707 #define AT91C_ADC_EOC4 ( ( unsigned int ) 0x1 << 4 ) /* (ADC) End of Conversion */
1708 #define AT91C_ADC_EOC5 ( ( unsigned int ) 0x1 << 5 ) /* (ADC) End of Conversion */
1709 #define AT91C_ADC_EOC6 ( ( unsigned int ) 0x1 << 6 ) /* (ADC) End of Conversion */
1710 #define AT91C_ADC_EOC7 ( ( unsigned int ) 0x1 << 7 ) /* (ADC) End of Conversion */
1711 #define AT91C_ADC_OVRE0 ( ( unsigned int ) 0x1 << 8 ) /* (ADC) Overrun Error */
1712 #define AT91C_ADC_OVRE1 ( ( unsigned int ) 0x1 << 9 ) /* (ADC) Overrun Error */
1713 #define AT91C_ADC_OVRE2 ( ( unsigned int ) 0x1 << 10 ) /* (ADC) Overrun Error */
1714 #define AT91C_ADC_OVRE3 ( ( unsigned int ) 0x1 << 11 ) /* (ADC) Overrun Error */
1715 #define AT91C_ADC_OVRE4 ( ( unsigned int ) 0x1 << 12 ) /* (ADC) Overrun Error */
1716 #define AT91C_ADC_OVRE5 ( ( unsigned int ) 0x1 << 13 ) /* (ADC) Overrun Error */
1717 #define AT91C_ADC_OVRE6 ( ( unsigned int ) 0x1 << 14 ) /* (ADC) Overrun Error */
1718 #define AT91C_ADC_OVRE7 ( ( unsigned int ) 0x1 << 15 ) /* (ADC) Overrun Error */
1719 #define AT91C_ADC_DRDY ( ( unsigned int ) 0x1 << 16 ) /* (ADC) Data Ready */
1720 #define AT91C_ADC_GOVRE ( ( unsigned int ) 0x1 << 17 ) /* (ADC) General Overrun */
1721 #define AT91C_ADC_ENDRX ( ( unsigned int ) 0x1 << 18 ) /* (ADC) End of Receiver Transfer */
1722 #define AT91C_ADC_RXBUFF ( ( unsigned int ) 0x1 << 19 ) /* (ADC) RXBUFF Interrupt */
1723 /* -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- */
1724 #define AT91C_ADC_LDATA ( ( unsigned int ) 0x3FF << 0 ) /* (ADC) Last Data Converted */
1725 /* -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- */
1726 /* -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- */
1727 /* -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- */
1728 /* -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- */
1729 #define AT91C_ADC_DATA ( ( unsigned int ) 0x3FF << 0 ) /* (ADC) Converted Data */
1730 /* -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- */
1731 /* -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- */
1732 /* -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- */
1733 /* -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- */
1734 /* -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- */
1735 /* -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- */
1736 /* -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- */
1738 /* ***************************************************************************** */
1739 /* SOFTWARE API DEFINITION FOR Advanced Encryption Standard */
1740 /* ***************************************************************************** */
1741 typedef struct _AT91S_AES
1743 AT91_REG AES_CR; /* Control Register */
1744 AT91_REG AES_MR; /* Mode Register */
1745 AT91_REG Reserved0[ 2 ]; /* */
1746 AT91_REG AES_IER; /* Interrupt Enable Register */
1747 AT91_REG AES_IDR; /* Interrupt Disable Register */
1748 AT91_REG AES_IMR; /* Interrupt Mask Register */
1749 AT91_REG AES_ISR; /* Interrupt Status Register */
1750 AT91_REG AES_KEYWxR[ 4 ]; /* Key Word x Register */
1751 AT91_REG Reserved1[ 4 ]; /* */
1752 AT91_REG AES_IDATAxR[ 4 ]; /* Input Data x Register */
1753 AT91_REG AES_ODATAxR[ 4 ]; /* Output Data x Register */
1754 AT91_REG AES_IVxR[ 4 ]; /* Initialization Vector x Register */
1755 AT91_REG Reserved2[ 35 ]; /* */
1756 AT91_REG AES_VR; /* AES Version Register */
1757 AT91_REG AES_RPR; /* Receive Pointer Register */
1758 AT91_REG AES_RCR; /* Receive Counter Register */
1759 AT91_REG AES_TPR; /* Transmit Pointer Register */
1760 AT91_REG AES_TCR; /* Transmit Counter Register */
1761 AT91_REG AES_RNPR; /* Receive Next Pointer Register */
1762 AT91_REG AES_RNCR; /* Receive Next Counter Register */
1763 AT91_REG AES_TNPR; /* Transmit Next Pointer Register */
1764 AT91_REG AES_TNCR; /* Transmit Next Counter Register */
1765 AT91_REG AES_PTCR; /* PDC Transfer Control Register */
1766 AT91_REG AES_PTSR; /* PDC Transfer Status Register */
1767 } AT91S_AES, * AT91PS_AES;
1769 /* -------- AES_CR : (AES Offset: 0x0) Control Register -------- */
1770 #define AT91C_AES_START ( ( unsigned int ) 0x1 << 0 ) /* (AES) Starts Processing */
1771 #define AT91C_AES_SWRST ( ( unsigned int ) 0x1 << 8 ) /* (AES) Software Reset */
1772 #define AT91C_AES_LOADSEED ( ( unsigned int ) 0x1 << 16 ) /* (AES) Random Number Generator Seed Loading */
1773 /* -------- AES_MR : (AES Offset: 0x4) Mode Register -------- */
1774 #define AT91C_AES_CIPHER ( ( unsigned int ) 0x1 << 0 ) /* (AES) Processing Mode */
1775 #define AT91C_AES_PROCDLY ( ( unsigned int ) 0xF << 4 ) /* (AES) Processing Delay */
1776 #define AT91C_AES_SMOD ( ( unsigned int ) 0x3 << 8 ) /* (AES) Start Mode */
1777 #define AT91C_AES_SMOD_MANUAL ( ( unsigned int ) 0x0 << 8 ) /* (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption. */
1778 #define AT91C_AES_SMOD_AUTO ( ( unsigned int ) 0x1 << 8 ) /* (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet). */
1779 #define AT91C_AES_SMOD_PDC ( ( unsigned int ) 0x2 << 8 ) /* (AES) PDC Mode (cf datasheet). */
1780 #define AT91C_AES_OPMOD ( ( unsigned int ) 0x7 << 12 ) /* (AES) Operation Mode */
1781 #define AT91C_AES_OPMOD_ECB ( ( unsigned int ) 0x0 << 12 ) /* (AES) ECB Electronic CodeBook mode. */
1782 #define AT91C_AES_OPMOD_CBC ( ( unsigned int ) 0x1 << 12 ) /* (AES) CBC Cipher Block Chaining mode. */
1783 #define AT91C_AES_OPMOD_OFB ( ( unsigned int ) 0x2 << 12 ) /* (AES) OFB Output Feedback mode. */
1784 #define AT91C_AES_OPMOD_CFB ( ( unsigned int ) 0x3 << 12 ) /* (AES) CFB Cipher Feedback mode. */
1785 #define AT91C_AES_OPMOD_CTR ( ( unsigned int ) 0x4 << 12 ) /* (AES) CTR Counter mode. */
1786 #define AT91C_AES_LOD ( ( unsigned int ) 0x1 << 15 ) /* (AES) Last Output Data Mode */
1787 #define AT91C_AES_CFBS ( ( unsigned int ) 0x7 << 16 ) /* (AES) Cipher Feedback Data Size */
1788 #define AT91C_AES_CFBS_128_BIT ( ( unsigned int ) 0x0 << 16 ) /* (AES) 128-bit. */
1789 #define AT91C_AES_CFBS_64_BIT ( ( unsigned int ) 0x1 << 16 ) /* (AES) 64-bit. */
1790 #define AT91C_AES_CFBS_32_BIT ( ( unsigned int ) 0x2 << 16 ) /* (AES) 32-bit. */
1791 #define AT91C_AES_CFBS_16_BIT ( ( unsigned int ) 0x3 << 16 ) /* (AES) 16-bit. */
1792 #define AT91C_AES_CFBS_8_BIT ( ( unsigned int ) 0x4 << 16 ) /* (AES) 8-bit. */
1793 #define AT91C_AES_CKEY ( ( unsigned int ) 0xF << 20 ) /* (AES) Countermeasure Key */
1794 #define AT91C_AES_CTYPE ( ( unsigned int ) 0x1F << 24 ) /* (AES) Countermeasure Type */
1795 #define AT91C_AES_CTYPE_TYPE1_EN ( ( unsigned int ) 0x1 << 24 ) /* (AES) Countermeasure type 1 is enabled. */
1796 #define AT91C_AES_CTYPE_TYPE2_EN ( ( unsigned int ) 0x2 << 24 ) /* (AES) Countermeasure type 2 is enabled. */
1797 #define AT91C_AES_CTYPE_TYPE3_EN ( ( unsigned int ) 0x4 << 24 ) /* (AES) Countermeasure type 3 is enabled. */
1798 #define AT91C_AES_CTYPE_TYPE4_EN ( ( unsigned int ) 0x8 << 24 ) /* (AES) Countermeasure type 4 is enabled. */
1799 #define AT91C_AES_CTYPE_TYPE5_EN ( ( unsigned int ) 0x10 << 24 ) /* (AES) Countermeasure type 5 is enabled. */
1800 /* -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- */
1801 #define AT91C_AES_DATRDY ( ( unsigned int ) 0x1 << 0 ) /* (AES) DATRDY */
1802 #define AT91C_AES_ENDRX ( ( unsigned int ) 0x1 << 1 ) /* (AES) PDC Read Buffer End */
1803 #define AT91C_AES_ENDTX ( ( unsigned int ) 0x1 << 2 ) /* (AES) PDC Write Buffer End */
1804 #define AT91C_AES_RXBUFF ( ( unsigned int ) 0x1 << 3 ) /* (AES) PDC Read Buffer Full */
1805 #define AT91C_AES_TXBUFE ( ( unsigned int ) 0x1 << 4 ) /* (AES) PDC Write Buffer Empty */
1806 #define AT91C_AES_URAD ( ( unsigned int ) 0x1 << 8 ) /* (AES) Unspecified Register Access Detection */
1807 /* -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- */
1808 /* -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- */
1809 /* -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- */
1810 #define AT91C_AES_URAT ( ( unsigned int ) 0x7 << 12 ) /* (AES) Unspecified Register Access Type Status */
1811 #define AT91C_AES_URAT_IN_DAT_WRITE_DATPROC ( ( unsigned int ) 0x0 << 12 ) /* (AES) Input data register written during the data processing in PDC mode. */
1812 #define AT91C_AES_URAT_OUT_DAT_READ_DATPROC ( ( unsigned int ) 0x1 << 12 ) /* (AES) Output data register read during the data processing. */
1813 #define AT91C_AES_URAT_MODEREG_WRITE_DATPROC ( ( unsigned int ) 0x2 << 12 ) /* (AES) Mode register written during the data processing. */
1814 #define AT91C_AES_URAT_OUT_DAT_READ_SUBKEY ( ( unsigned int ) 0x3 << 12 ) /* (AES) Output data register read during the sub-keys generation. */
1815 #define AT91C_AES_URAT_MODEREG_WRITE_SUBKEY ( ( unsigned int ) 0x4 << 12 ) /* (AES) Mode register written during the sub-keys generation. */
1816 #define AT91C_AES_URAT_WO_REG_READ ( ( unsigned int ) 0x5 << 12 ) /* (AES) Write-only register read access. */
1818 /* ***************************************************************************** */
1819 /* SOFTWARE API DEFINITION FOR Triple Data Encryption Standard */
1820 /* ***************************************************************************** */
1821 typedef struct _AT91S_TDES
1823 AT91_REG TDES_CR; /* Control Register */
1824 AT91_REG TDES_MR; /* Mode Register */
1825 AT91_REG Reserved0[ 2 ]; /* */
1826 AT91_REG TDES_IER; /* Interrupt Enable Register */
1827 AT91_REG TDES_IDR; /* Interrupt Disable Register */
1828 AT91_REG TDES_IMR; /* Interrupt Mask Register */
1829 AT91_REG TDES_ISR; /* Interrupt Status Register */
1830 AT91_REG TDES_KEY1WxR[ 2 ]; /* Key 1 Word x Register */
1831 AT91_REG TDES_KEY2WxR[ 2 ]; /* Key 2 Word x Register */
1832 AT91_REG TDES_KEY3WxR[ 2 ]; /* Key 3 Word x Register */
1833 AT91_REG Reserved1[ 2 ]; /* */
1834 AT91_REG TDES_IDATAxR[ 2 ]; /* Input Data x Register */
1835 AT91_REG Reserved2[ 2 ]; /* */
1836 AT91_REG TDES_ODATAxR[ 2 ]; /* Output Data x Register */
1837 AT91_REG Reserved3[ 2 ]; /* */
1838 AT91_REG TDES_IVxR[ 2 ]; /* Initialization Vector x Register */
1839 AT91_REG Reserved4[ 37 ]; /* */
1840 AT91_REG TDES_VR; /* TDES Version Register */
1841 AT91_REG TDES_RPR; /* Receive Pointer Register */
1842 AT91_REG TDES_RCR; /* Receive Counter Register */
1843 AT91_REG TDES_TPR; /* Transmit Pointer Register */
1844 AT91_REG TDES_TCR; /* Transmit Counter Register */
1845 AT91_REG TDES_RNPR; /* Receive Next Pointer Register */
1846 AT91_REG TDES_RNCR; /* Receive Next Counter Register */
1847 AT91_REG TDES_TNPR; /* Transmit Next Pointer Register */
1848 AT91_REG TDES_TNCR; /* Transmit Next Counter Register */
1849 AT91_REG TDES_PTCR; /* PDC Transfer Control Register */
1850 AT91_REG TDES_PTSR; /* PDC Transfer Status Register */
1851 } AT91S_TDES, * AT91PS_TDES;
1853 /* -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- */
1854 #define AT91C_TDES_START ( ( unsigned int ) 0x1 << 0 ) /* (TDES) Starts Processing */
1855 #define AT91C_TDES_SWRST ( ( unsigned int ) 0x1 << 8 ) /* (TDES) Software Reset */
1856 /* -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- */
1857 #define AT91C_TDES_CIPHER ( ( unsigned int ) 0x1 << 0 ) /* (TDES) Processing Mode */
1858 #define AT91C_TDES_TDESMOD ( ( unsigned int ) 0x1 << 1 ) /* (TDES) Single or Triple DES Mode */
1859 #define AT91C_TDES_KEYMOD ( ( unsigned int ) 0x1 << 4 ) /* (TDES) Key Mode */
1860 #define AT91C_TDES_SMOD ( ( unsigned int ) 0x3 << 8 ) /* (TDES) Start Mode */
1861 #define AT91C_TDES_SMOD_MANUAL ( ( unsigned int ) 0x0 << 8 ) /* (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption. */
1862 #define AT91C_TDES_SMOD_AUTO ( ( unsigned int ) 0x1 << 8 ) /* (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet). */
1863 #define AT91C_TDES_SMOD_PDC ( ( unsigned int ) 0x2 << 8 ) /* (TDES) PDC Mode (cf datasheet). */
1864 #define AT91C_TDES_OPMOD ( ( unsigned int ) 0x3 << 12 ) /* (TDES) Operation Mode */
1865 #define AT91C_TDES_OPMOD_ECB ( ( unsigned int ) 0x0 << 12 ) /* (TDES) ECB Electronic CodeBook mode. */
1866 #define AT91C_TDES_OPMOD_CBC ( ( unsigned int ) 0x1 << 12 ) /* (TDES) CBC Cipher Block Chaining mode. */
1867 #define AT91C_TDES_OPMOD_OFB ( ( unsigned int ) 0x2 << 12 ) /* (TDES) OFB Output Feedback mode. */
1868 #define AT91C_TDES_OPMOD_CFB ( ( unsigned int ) 0x3 << 12 ) /* (TDES) CFB Cipher Feedback mode. */
1869 #define AT91C_TDES_LOD ( ( unsigned int ) 0x1 << 15 ) /* (TDES) Last Output Data Mode */
1870 #define AT91C_TDES_CFBS ( ( unsigned int ) 0x3 << 16 ) /* (TDES) Cipher Feedback Data Size */
1871 #define AT91C_TDES_CFBS_64_BIT ( ( unsigned int ) 0x0 << 16 ) /* (TDES) 64-bit. */
1872 #define AT91C_TDES_CFBS_32_BIT ( ( unsigned int ) 0x1 << 16 ) /* (TDES) 32-bit. */
1873 #define AT91C_TDES_CFBS_16_BIT ( ( unsigned int ) 0x2 << 16 ) /* (TDES) 16-bit. */
1874 #define AT91C_TDES_CFBS_8_BIT ( ( unsigned int ) 0x3 << 16 ) /* (TDES) 8-bit. */
1875 /* -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- */
1876 #define AT91C_TDES_DATRDY ( ( unsigned int ) 0x1 << 0 ) /* (TDES) DATRDY */
1877 #define AT91C_TDES_ENDRX ( ( unsigned int ) 0x1 << 1 ) /* (TDES) PDC Read Buffer End */
1878 #define AT91C_TDES_ENDTX ( ( unsigned int ) 0x1 << 2 ) /* (TDES) PDC Write Buffer End */
1879 #define AT91C_TDES_RXBUFF ( ( unsigned int ) 0x1 << 3 ) /* (TDES) PDC Read Buffer Full */
1880 #define AT91C_TDES_TXBUFE ( ( unsigned int ) 0x1 << 4 ) /* (TDES) PDC Write Buffer Empty */
1881 #define AT91C_TDES_URAD ( ( unsigned int ) 0x1 << 8 ) /* (TDES) Unspecified Register Access Detection */
1882 /* -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- */
1883 /* -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- */
1884 /* -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- */
1885 #define AT91C_TDES_URAT ( ( unsigned int ) 0x3 << 12 ) /* (TDES) Unspecified Register Access Type Status */
1886 #define AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC ( ( unsigned int ) 0x0 << 12 ) /* (TDES) Input data register written during the data processing in PDC mode. */
1887 #define AT91C_TDES_URAT_OUT_DAT_READ_DATPROC ( ( unsigned int ) 0x1 << 12 ) /* (TDES) Output data register read during the data processing. */
1888 #define AT91C_TDES_URAT_MODEREG_WRITE_DATPROC ( ( unsigned int ) 0x2 << 12 ) /* (TDES) Mode register written during the data processing. */
1889 #define AT91C_TDES_URAT_WO_REG_READ ( ( unsigned int ) 0x3 << 12 ) /* (TDES) Write-only register read access. */
1891 /* ***************************************************************************** */
1892 /* REGISTER ADDRESS DEFINITION FOR AT91SAM7X256 */
1893 /* ***************************************************************************** */
1894 /* ========== Register definition for SYS peripheral ========== */
1895 /* ========== Register definition for AIC peripheral ========== */
1896 #define AT91C_AIC_IVR ( ( AT91_REG * ) 0xFFFFF100 ) /* (AIC) IRQ Vector Register */
1897 #define AT91C_AIC_SMR ( ( AT91_REG * ) 0xFFFFF000 ) /* (AIC) Source Mode Register */
1898 #define AT91C_AIC_FVR ( ( AT91_REG * ) 0xFFFFF104 ) /* (AIC) FIQ Vector Register */
1899 #define AT91C_AIC_DCR ( ( AT91_REG * ) 0xFFFFF138 ) /* (AIC) Debug Control Register (Protect) */
1900 #define AT91C_AIC_EOICR ( ( AT91_REG * ) 0xFFFFF130 ) /* (AIC) End of Interrupt Command Register */
1901 #define AT91C_AIC_SVR ( ( AT91_REG * ) 0xFFFFF080 ) /* (AIC) Source Vector Register */
1902 #define AT91C_AIC_FFSR ( ( AT91_REG * ) 0xFFFFF148 ) /* (AIC) Fast Forcing Status Register */
1903 #define AT91C_AIC_ICCR ( ( AT91_REG * ) 0xFFFFF128 ) /* (AIC) Interrupt Clear Command Register */
1904 #define AT91C_AIC_ISR ( ( AT91_REG * ) 0xFFFFF108 ) /* (AIC) Interrupt Status Register */
1905 #define AT91C_AIC_IMR ( ( AT91_REG * ) 0xFFFFF110 ) /* (AIC) Interrupt Mask Register */
1906 #define AT91C_AIC_IPR ( ( AT91_REG * ) 0xFFFFF10C ) /* (AIC) Interrupt Pending Register */
1907 #define AT91C_AIC_FFER ( ( AT91_REG * ) 0xFFFFF140 ) /* (AIC) Fast Forcing Enable Register */
1908 #define AT91C_AIC_IECR ( ( AT91_REG * ) 0xFFFFF120 ) /* (AIC) Interrupt Enable Command Register */
1909 #define AT91C_AIC_ISCR ( ( AT91_REG * ) 0xFFFFF12C ) /* (AIC) Interrupt Set Command Register */
1910 #define AT91C_AIC_FFDR ( ( AT91_REG * ) 0xFFFFF144 ) /* (AIC) Fast Forcing Disable Register */
1911 #define AT91C_AIC_CISR ( ( AT91_REG * ) 0xFFFFF114 ) /* (AIC) Core Interrupt Status Register */
1912 #define AT91C_AIC_IDCR ( ( AT91_REG * ) 0xFFFFF124 ) /* (AIC) Interrupt Disable Command Register */
1913 #define AT91C_AIC_SPU ( ( AT91_REG * ) 0xFFFFF134 ) /* (AIC) Spurious Vector Register */
1914 /* ========== Register definition for PDC_DBGU peripheral ========== */
1915 #define AT91C_DBGU_TCR ( ( AT91_REG * ) 0xFFFFF30C ) /* (PDC_DBGU) Transmit Counter Register */
1916 #define AT91C_DBGU_RNPR ( ( AT91_REG * ) 0xFFFFF310 ) /* (PDC_DBGU) Receive Next Pointer Register */
1917 #define AT91C_DBGU_TNPR ( ( AT91_REG * ) 0xFFFFF318 ) /* (PDC_DBGU) Transmit Next Pointer Register */
1918 #define AT91C_DBGU_TPR ( ( AT91_REG * ) 0xFFFFF308 ) /* (PDC_DBGU) Transmit Pointer Register */
1919 #define AT91C_DBGU_RPR ( ( AT91_REG * ) 0xFFFFF300 ) /* (PDC_DBGU) Receive Pointer Register */
1920 #define AT91C_DBGU_RCR ( ( AT91_REG * ) 0xFFFFF304 ) /* (PDC_DBGU) Receive Counter Register */
1921 #define AT91C_DBGU_RNCR ( ( AT91_REG * ) 0xFFFFF314 ) /* (PDC_DBGU) Receive Next Counter Register */
1922 #define AT91C_DBGU_PTCR ( ( AT91_REG * ) 0xFFFFF320 ) /* (PDC_DBGU) PDC Transfer Control Register */
1923 #define AT91C_DBGU_PTSR ( ( AT91_REG * ) 0xFFFFF324 ) /* (PDC_DBGU) PDC Transfer Status Register */
1924 #define AT91C_DBGU_TNCR ( ( AT91_REG * ) 0xFFFFF31C ) /* (PDC_DBGU) Transmit Next Counter Register */
1925 /* ========== Register definition for DBGU peripheral ========== */
1926 #define AT91C_DBGU_EXID ( ( AT91_REG * ) 0xFFFFF244 ) /* (DBGU) Chip ID Extension Register */
1927 #define AT91C_DBGU_BRGR ( ( AT91_REG * ) 0xFFFFF220 ) /* (DBGU) Baud Rate Generator Register */
1928 #define AT91C_DBGU_IDR ( ( AT91_REG * ) 0xFFFFF20C ) /* (DBGU) Interrupt Disable Register */
1929 #define AT91C_DBGU_CSR ( ( AT91_REG * ) 0xFFFFF214 ) /* (DBGU) Channel Status Register */
1930 #define AT91C_DBGU_CIDR ( ( AT91_REG * ) 0xFFFFF240 ) /* (DBGU) Chip ID Register */
1931 #define AT91C_DBGU_MR ( ( AT91_REG * ) 0xFFFFF204 ) /* (DBGU) Mode Register */
1932 #define AT91C_DBGU_IMR ( ( AT91_REG * ) 0xFFFFF210 ) /* (DBGU) Interrupt Mask Register */
1933 #define AT91C_DBGU_CR ( ( AT91_REG * ) 0xFFFFF200 ) /* (DBGU) Control Register */
1934 #define AT91C_DBGU_FNTR ( ( AT91_REG * ) 0xFFFFF248 ) /* (DBGU) Force NTRST Register */
1935 #define AT91C_DBGU_THR ( ( AT91_REG * ) 0xFFFFF21C ) /* (DBGU) Transmitter Holding Register */
1936 #define AT91C_DBGU_RHR ( ( AT91_REG * ) 0xFFFFF218 ) /* (DBGU) Receiver Holding Register */
1937 #define AT91C_DBGU_IER ( ( AT91_REG * ) 0xFFFFF208 ) /* (DBGU) Interrupt Enable Register */
1938 /* ========== Register definition for PIOA peripheral ========== */
1939 #define AT91C_PIOA_ODR ( ( AT91_REG * ) 0xFFFFF414 ) /* (PIOA) Output Disable Registerr */
1940 #define AT91C_PIOA_SODR ( ( AT91_REG * ) 0xFFFFF430 ) /* (PIOA) Set Output Data Register */
1941 #define AT91C_PIOA_ISR ( ( AT91_REG * ) 0xFFFFF44C ) /* (PIOA) Interrupt Status Register */
1942 #define AT91C_PIOA_ABSR ( ( AT91_REG * ) 0xFFFFF478 ) /* (PIOA) AB Select Status Register */
1943 #define AT91C_PIOA_IER ( ( AT91_REG * ) 0xFFFFF440 ) /* (PIOA) Interrupt Enable Register */
1944 #define AT91C_PIOA_PPUDR ( ( AT91_REG * ) 0xFFFFF460 ) /* (PIOA) Pull-up Disable Register */
1945 #define AT91C_PIOA_IMR ( ( AT91_REG * ) 0xFFFFF448 ) /* (PIOA) Interrupt Mask Register */
1946 #define AT91C_PIOA_PER ( ( AT91_REG * ) 0xFFFFF400 ) /* (PIOA) PIO Enable Register */
1947 #define AT91C_PIOA_IFDR ( ( AT91_REG * ) 0xFFFFF424 ) /* (PIOA) Input Filter Disable Register */
1948 #define AT91C_PIOA_OWDR ( ( AT91_REG * ) 0xFFFFF4A4 ) /* (PIOA) Output Write Disable Register */
1949 #define AT91C_PIOA_MDSR ( ( AT91_REG * ) 0xFFFFF458 ) /* (PIOA) Multi-driver Status Register */
1950 #define AT91C_PIOA_IDR ( ( AT91_REG * ) 0xFFFFF444 ) /* (PIOA) Interrupt Disable Register */
1951 #define AT91C_PIOA_ODSR ( ( AT91_REG * ) 0xFFFFF438 ) /* (PIOA) Output Data Status Register */
1952 #define AT91C_PIOA_PPUSR ( ( AT91_REG * ) 0xFFFFF468 ) /* (PIOA) Pull-up Status Register */
1953 #define AT91C_PIOA_OWSR ( ( AT91_REG * ) 0xFFFFF4A8 ) /* (PIOA) Output Write Status Register */
1954 #define AT91C_PIOA_BSR ( ( AT91_REG * ) 0xFFFFF474 ) /* (PIOA) Select B Register */
1955 #define AT91C_PIOA_OWER ( ( AT91_REG * ) 0xFFFFF4A0 ) /* (PIOA) Output Write Enable Register */
1956 #define AT91C_PIOA_IFER ( ( AT91_REG * ) 0xFFFFF420 ) /* (PIOA) Input Filter Enable Register */
1957 #define AT91C_PIOA_PDSR ( ( AT91_REG * ) 0xFFFFF43C ) /* (PIOA) Pin Data Status Register */
1958 #define AT91C_PIOA_PPUER ( ( AT91_REG * ) 0xFFFFF464 ) /* (PIOA) Pull-up Enable Register */
1959 #define AT91C_PIOA_OSR ( ( AT91_REG * ) 0xFFFFF418 ) /* (PIOA) Output Status Register */
1960 #define AT91C_PIOA_ASR ( ( AT91_REG * ) 0xFFFFF470 ) /* (PIOA) Select A Register */
1961 #define AT91C_PIOA_MDDR ( ( AT91_REG * ) 0xFFFFF454 ) /* (PIOA) Multi-driver Disable Register */
1962 #define AT91C_PIOA_CODR ( ( AT91_REG * ) 0xFFFFF434 ) /* (PIOA) Clear Output Data Register */
1963 #define AT91C_PIOA_MDER ( ( AT91_REG * ) 0xFFFFF450 ) /* (PIOA) Multi-driver Enable Register */
1964 #define AT91C_PIOA_PDR ( ( AT91_REG * ) 0xFFFFF404 ) /* (PIOA) PIO Disable Register */
1965 #define AT91C_PIOA_IFSR ( ( AT91_REG * ) 0xFFFFF428 ) /* (PIOA) Input Filter Status Register */
1966 #define AT91C_PIOA_OER ( ( AT91_REG * ) 0xFFFFF410 ) /* (PIOA) Output Enable Register */
1967 #define AT91C_PIOA_PSR ( ( AT91_REG * ) 0xFFFFF408 ) /* (PIOA) PIO Status Register */
1968 /* ========== Register definition for PIOB peripheral ========== */
1969 #define AT91C_PIOB_OWDR ( ( AT91_REG * ) 0xFFFFF6A4 ) /* (PIOB) Output Write Disable Register */
1970 #define AT91C_PIOB_MDER ( ( AT91_REG * ) 0xFFFFF650 ) /* (PIOB) Multi-driver Enable Register */
1971 #define AT91C_PIOB_PPUSR ( ( AT91_REG * ) 0xFFFFF668 ) /* (PIOB) Pull-up Status Register */
1972 #define AT91C_PIOB_IMR ( ( AT91_REG * ) 0xFFFFF648 ) /* (PIOB) Interrupt Mask Register */
1973 #define AT91C_PIOB_ASR ( ( AT91_REG * ) 0xFFFFF670 ) /* (PIOB) Select A Register */
1974 #define AT91C_PIOB_PPUDR ( ( AT91_REG * ) 0xFFFFF660 ) /* (PIOB) Pull-up Disable Register */
1975 #define AT91C_PIOB_PSR ( ( AT91_REG * ) 0xFFFFF608 ) /* (PIOB) PIO Status Register */
1976 #define AT91C_PIOB_IER ( ( AT91_REG * ) 0xFFFFF640 ) /* (PIOB) Interrupt Enable Register */
1977 #define AT91C_PIOB_CODR ( ( AT91_REG * ) 0xFFFFF634 ) /* (PIOB) Clear Output Data Register */
1978 #define AT91C_PIOB_OWER ( ( AT91_REG * ) 0xFFFFF6A0 ) /* (PIOB) Output Write Enable Register */
1979 #define AT91C_PIOB_ABSR ( ( AT91_REG * ) 0xFFFFF678 ) /* (PIOB) AB Select Status Register */
1980 #define AT91C_PIOB_IFDR ( ( AT91_REG * ) 0xFFFFF624 ) /* (PIOB) Input Filter Disable Register */
1981 #define AT91C_PIOB_PDSR ( ( AT91_REG * ) 0xFFFFF63C ) /* (PIOB) Pin Data Status Register */
1982 #define AT91C_PIOB_IDR ( ( AT91_REG * ) 0xFFFFF644 ) /* (PIOB) Interrupt Disable Register */
1983 #define AT91C_PIOB_OWSR ( ( AT91_REG * ) 0xFFFFF6A8 ) /* (PIOB) Output Write Status Register */
1984 #define AT91C_PIOB_PDR ( ( AT91_REG * ) 0xFFFFF604 ) /* (PIOB) PIO Disable Register */
1985 #define AT91C_PIOB_ODR ( ( AT91_REG * ) 0xFFFFF614 ) /* (PIOB) Output Disable Registerr */
1986 #define AT91C_PIOB_IFSR ( ( AT91_REG * ) 0xFFFFF628 ) /* (PIOB) Input Filter Status Register */
1987 #define AT91C_PIOB_PPUER ( ( AT91_REG * ) 0xFFFFF664 ) /* (PIOB) Pull-up Enable Register */
1988 #define AT91C_PIOB_SODR ( ( AT91_REG * ) 0xFFFFF630 ) /* (PIOB) Set Output Data Register */
1989 #define AT91C_PIOB_ISR ( ( AT91_REG * ) 0xFFFFF64C ) /* (PIOB) Interrupt Status Register */
1990 #define AT91C_PIOB_ODSR ( ( AT91_REG * ) 0xFFFFF638 ) /* (PIOB) Output Data Status Register */
1991 #define AT91C_PIOB_OSR ( ( AT91_REG * ) 0xFFFFF618 ) /* (PIOB) Output Status Register */
1992 #define AT91C_PIOB_MDSR ( ( AT91_REG * ) 0xFFFFF658 ) /* (PIOB) Multi-driver Status Register */
1993 #define AT91C_PIOB_IFER ( ( AT91_REG * ) 0xFFFFF620 ) /* (PIOB) Input Filter Enable Register */
1994 #define AT91C_PIOB_BSR ( ( AT91_REG * ) 0xFFFFF674 ) /* (PIOB) Select B Register */
1995 #define AT91C_PIOB_MDDR ( ( AT91_REG * ) 0xFFFFF654 ) /* (PIOB) Multi-driver Disable Register */
1996 #define AT91C_PIOB_OER ( ( AT91_REG * ) 0xFFFFF610 ) /* (PIOB) Output Enable Register */
1997 #define AT91C_PIOB_PER ( ( AT91_REG * ) 0xFFFFF600 ) /* (PIOB) PIO Enable Register */
1998 /* ========== Register definition for CKGR peripheral ========== */
1999 #define AT91C_CKGR_MOR ( ( AT91_REG * ) 0xFFFFFC20 ) /* (CKGR) Main Oscillator Register */
2000 #define AT91C_CKGR_PLLR ( ( AT91_REG * ) 0xFFFFFC2C ) /* (CKGR) PLL Register */
2001 #define AT91C_CKGR_MCFR ( ( AT91_REG * ) 0xFFFFFC24 ) /* (CKGR) Main Clock Frequency Register */
2002 /* ========== Register definition for PMC peripheral ========== */
2003 #define AT91C_PMC_IDR ( ( AT91_REG * ) 0xFFFFFC64 ) /* (PMC) Interrupt Disable Register */
2004 #define AT91C_PMC_MOR ( ( AT91_REG * ) 0xFFFFFC20 ) /* (PMC) Main Oscillator Register */
2005 #define AT91C_PMC_PLLR ( ( AT91_REG * ) 0xFFFFFC2C ) /* (PMC) PLL Register */
2006 #define AT91C_PMC_PCER ( ( AT91_REG * ) 0xFFFFFC10 ) /* (PMC) Peripheral Clock Enable Register */
2007 #define AT91C_PMC_PCKR ( ( AT91_REG * ) 0xFFFFFC40 ) /* (PMC) Programmable Clock Register */
2008 #define AT91C_PMC_MCKR ( ( AT91_REG * ) 0xFFFFFC30 ) /* (PMC) Master Clock Register */
2009 #define AT91C_PMC_SCDR ( ( AT91_REG * ) 0xFFFFFC04 ) /* (PMC) System Clock Disable Register */
2010 #define AT91C_PMC_PCDR ( ( AT91_REG * ) 0xFFFFFC14 ) /* (PMC) Peripheral Clock Disable Register */
2011 #define AT91C_PMC_SCSR ( ( AT91_REG * ) 0xFFFFFC08 ) /* (PMC) System Clock Status Register */
2012 #define AT91C_PMC_PCSR ( ( AT91_REG * ) 0xFFFFFC18 ) /* (PMC) Peripheral Clock Status Register */
2013 #define AT91C_PMC_MCFR ( ( AT91_REG * ) 0xFFFFFC24 ) /* (PMC) Main Clock Frequency Register */
2014 #define AT91C_PMC_SCER ( ( AT91_REG * ) 0xFFFFFC00 ) /* (PMC) System Clock Enable Register */
2015 #define AT91C_PMC_IMR ( ( AT91_REG * ) 0xFFFFFC6C ) /* (PMC) Interrupt Mask Register */
2016 #define AT91C_PMC_IER ( ( AT91_REG * ) 0xFFFFFC60 ) /* (PMC) Interrupt Enable Register */
2017 #define AT91C_PMC_SR ( ( AT91_REG * ) 0xFFFFFC68 ) /* (PMC) Status Register */
2018 /* ========== Register definition for RSTC peripheral ========== */
2019 #define AT91C_RSTC_RCR ( ( AT91_REG * ) 0xFFFFFD00 ) /* (RSTC) Reset Control Register */
2020 #define AT91C_RSTC_RMR ( ( AT91_REG * ) 0xFFFFFD08 ) /* (RSTC) Reset Mode Register */
2021 #define AT91C_RSTC_RSR ( ( AT91_REG * ) 0xFFFFFD04 ) /* (RSTC) Reset Status Register */
2022 /* ========== Register definition for RTTC peripheral ========== */
2023 #define AT91C_RTTC_RTSR ( ( AT91_REG * ) 0xFFFFFD2C ) /* (RTTC) Real-time Status Register */
2024 #define AT91C_RTTC_RTMR ( ( AT91_REG * ) 0xFFFFFD20 ) /* (RTTC) Real-time Mode Register */
2025 #define AT91C_RTTC_RTVR ( ( AT91_REG * ) 0xFFFFFD28 ) /* (RTTC) Real-time Value Register */
2026 #define AT91C_RTTC_RTAR ( ( AT91_REG * ) 0xFFFFFD24 ) /* (RTTC) Real-time Alarm Register */
2027 /* ========== Register definition for PITC peripheral ========== */
2028 #define AT91C_PITC_PIVR ( ( AT91_REG * ) 0xFFFFFD38 ) /* (PITC) Period Interval Value Register */
2029 #define AT91C_PITC_PISR ( ( AT91_REG * ) 0xFFFFFD34 ) /* (PITC) Period Interval Status Register */
2030 #define AT91C_PITC_PIIR ( ( AT91_REG * ) 0xFFFFFD3C ) /* (PITC) Period Interval Image Register */
2031 #define AT91C_PITC_PIMR ( ( AT91_REG * ) 0xFFFFFD30 ) /* (PITC) Period Interval Mode Register */
2032 /* ========== Register definition for WDTC peripheral ========== */
2033 #define AT91C_WDTC_WDCR ( ( AT91_REG * ) 0xFFFFFD40 ) /* (WDTC) Watchdog Control Register */
2034 #define AT91C_WDTC_WDSR ( ( AT91_REG * ) 0xFFFFFD48 ) /* (WDTC) Watchdog Status Register */
2035 #define AT91C_WDTC_WDMR ( ( AT91_REG * ) 0xFFFFFD44 ) /* (WDTC) Watchdog Mode Register */
2036 /* ========== Register definition for VREG peripheral ========== */
2037 #define AT91C_VREG_MR ( ( AT91_REG * ) 0xFFFFFD60 ) /* (VREG) Voltage Regulator Mode Register */
2038 /* ========== Register definition for MC peripheral ========== */
2039 #define AT91C_MC_ASR ( ( AT91_REG * ) 0xFFFFFF04 ) /* (MC) MC Abort Status Register */
2040 #define AT91C_MC_RCR ( ( AT91_REG * ) 0xFFFFFF00 ) /* (MC) MC Remap Control Register */
2041 #define AT91C_MC_FCR ( ( AT91_REG * ) 0xFFFFFF64 ) /* (MC) MC Flash Command Register */
2042 #define AT91C_MC_AASR ( ( AT91_REG * ) 0xFFFFFF08 ) /* (MC) MC Abort Address Status Register */
2043 #define AT91C_MC_FSR ( ( AT91_REG * ) 0xFFFFFF68 ) /* (MC) MC Flash Status Register */
2044 #define AT91C_MC_FMR ( ( AT91_REG * ) 0xFFFFFF60 ) /* (MC) MC Flash Mode Register */
2045 /* ========== Register definition for PDC_SPI1 peripheral ========== */
2046 #define AT91C_SPI1_PTCR ( ( AT91_REG * ) 0xFFFE4120 ) /* (PDC_SPI1) PDC Transfer Control Register */
2047 #define AT91C_SPI1_RPR ( ( AT91_REG * ) 0xFFFE4100 ) /* (PDC_SPI1) Receive Pointer Register */
2048 #define AT91C_SPI1_TNCR ( ( AT91_REG * ) 0xFFFE411C ) /* (PDC_SPI1) Transmit Next Counter Register */
2049 #define AT91C_SPI1_TPR ( ( AT91_REG * ) 0xFFFE4108 ) /* (PDC_SPI1) Transmit Pointer Register */
2050 #define AT91C_SPI1_TNPR ( ( AT91_REG * ) 0xFFFE4118 ) /* (PDC_SPI1) Transmit Next Pointer Register */
2051 #define AT91C_SPI1_TCR ( ( AT91_REG * ) 0xFFFE410C ) /* (PDC_SPI1) Transmit Counter Register */
2052 #define AT91C_SPI1_RCR ( ( AT91_REG * ) 0xFFFE4104 ) /* (PDC_SPI1) Receive Counter Register */
2053 #define AT91C_SPI1_RNPR ( ( AT91_REG * ) 0xFFFE4110 ) /* (PDC_SPI1) Receive Next Pointer Register */
2054 #define AT91C_SPI1_RNCR ( ( AT91_REG * ) 0xFFFE4114 ) /* (PDC_SPI1) Receive Next Counter Register */
2055 #define AT91C_SPI1_PTSR ( ( AT91_REG * ) 0xFFFE4124 ) /* (PDC_SPI1) PDC Transfer Status Register */
2056 /* ========== Register definition for SPI1 peripheral ========== */
2057 #define AT91C_SPI1_IMR ( ( AT91_REG * ) 0xFFFE401C ) /* (SPI1) Interrupt Mask Register */
2058 #define AT91C_SPI1_IER ( ( AT91_REG * ) 0xFFFE4014 ) /* (SPI1) Interrupt Enable Register */
2059 #define AT91C_SPI1_MR ( ( AT91_REG * ) 0xFFFE4004 ) /* (SPI1) Mode Register */
2060 #define AT91C_SPI1_RDR ( ( AT91_REG * ) 0xFFFE4008 ) /* (SPI1) Receive Data Register */
2061 #define AT91C_SPI1_IDR ( ( AT91_REG * ) 0xFFFE4018 ) /* (SPI1) Interrupt Disable Register */
2062 #define AT91C_SPI1_SR ( ( AT91_REG * ) 0xFFFE4010 ) /* (SPI1) Status Register */
2063 #define AT91C_SPI1_TDR ( ( AT91_REG * ) 0xFFFE400C ) /* (SPI1) Transmit Data Register */
2064 #define AT91C_SPI1_CR ( ( AT91_REG * ) 0xFFFE4000 ) /* (SPI1) Control Register */
2065 #define AT91C_SPI1_CSR ( ( AT91_REG * ) 0xFFFE4030 ) /* (SPI1) Chip Select Register */
2066 /* ========== Register definition for PDC_SPI0 peripheral ========== */
2067 #define AT91C_SPI0_PTCR ( ( AT91_REG * ) 0xFFFE0120 ) /* (PDC_SPI0) PDC Transfer Control Register */
2068 #define AT91C_SPI0_TPR ( ( AT91_REG * ) 0xFFFE0108 ) /* (PDC_SPI0) Transmit Pointer Register */
2069 #define AT91C_SPI0_TCR ( ( AT91_REG * ) 0xFFFE010C ) /* (PDC_SPI0) Transmit Counter Register */
2070 #define AT91C_SPI0_RCR ( ( AT91_REG * ) 0xFFFE0104 ) /* (PDC_SPI0) Receive Counter Register */
2071 #define AT91C_SPI0_PTSR ( ( AT91_REG * ) 0xFFFE0124 ) /* (PDC_SPI0) PDC Transfer Status Register */
2072 #define AT91C_SPI0_RNPR ( ( AT91_REG * ) 0xFFFE0110 ) /* (PDC_SPI0) Receive Next Pointer Register */
2073 #define AT91C_SPI0_RPR ( ( AT91_REG * ) 0xFFFE0100 ) /* (PDC_SPI0) Receive Pointer Register */
2074 #define AT91C_SPI0_TNCR ( ( AT91_REG * ) 0xFFFE011C ) /* (PDC_SPI0) Transmit Next Counter Register */
2075 #define AT91C_SPI0_RNCR ( ( AT91_REG * ) 0xFFFE0114 ) /* (PDC_SPI0) Receive Next Counter Register */
2076 #define AT91C_SPI0_TNPR ( ( AT91_REG * ) 0xFFFE0118 ) /* (PDC_SPI0) Transmit Next Pointer Register */
2077 /* ========== Register definition for SPI0 peripheral ========== */
2078 #define AT91C_SPI0_IER ( ( AT91_REG * ) 0xFFFE0014 ) /* (SPI0) Interrupt Enable Register */
2079 #define AT91C_SPI0_SR ( ( AT91_REG * ) 0xFFFE0010 ) /* (SPI0) Status Register */
2080 #define AT91C_SPI0_IDR ( ( AT91_REG * ) 0xFFFE0018 ) /* (SPI0) Interrupt Disable Register */
2081 #define AT91C_SPI0_CR ( ( AT91_REG * ) 0xFFFE0000 ) /* (SPI0) Control Register */
2082 #define AT91C_SPI0_MR ( ( AT91_REG * ) 0xFFFE0004 ) /* (SPI0) Mode Register */
2083 #define AT91C_SPI0_IMR ( ( AT91_REG * ) 0xFFFE001C ) /* (SPI0) Interrupt Mask Register */
2084 #define AT91C_SPI0_TDR ( ( AT91_REG * ) 0xFFFE000C ) /* (SPI0) Transmit Data Register */
2085 #define AT91C_SPI0_RDR ( ( AT91_REG * ) 0xFFFE0008 ) /* (SPI0) Receive Data Register */
2086 #define AT91C_SPI0_CSR ( ( AT91_REG * ) 0xFFFE0030 ) /* (SPI0) Chip Select Register */
2087 /* ========== Register definition for PDC_US1 peripheral ========== */
2088 #define AT91C_US1_RNCR ( ( AT91_REG * ) 0xFFFC4114 ) /* (PDC_US1) Receive Next Counter Register */
2089 #define AT91C_US1_PTCR ( ( AT91_REG * ) 0xFFFC4120 ) /* (PDC_US1) PDC Transfer Control Register */
2090 #define AT91C_US1_TCR ( ( AT91_REG * ) 0xFFFC410C ) /* (PDC_US1) Transmit Counter Register */
2091 #define AT91C_US1_PTSR ( ( AT91_REG * ) 0xFFFC4124 ) /* (PDC_US1) PDC Transfer Status Register */
2092 #define AT91C_US1_TNPR ( ( AT91_REG * ) 0xFFFC4118 ) /* (PDC_US1) Transmit Next Pointer Register */
2093 #define AT91C_US1_RCR ( ( AT91_REG * ) 0xFFFC4104 ) /* (PDC_US1) Receive Counter Register */
2094 #define AT91C_US1_RNPR ( ( AT91_REG * ) 0xFFFC4110 ) /* (PDC_US1) Receive Next Pointer Register */
2095 #define AT91C_US1_RPR ( ( AT91_REG * ) 0xFFFC4100 ) /* (PDC_US1) Receive Pointer Register */
2096 #define AT91C_US1_TNCR ( ( AT91_REG * ) 0xFFFC411C ) /* (PDC_US1) Transmit Next Counter Register */
2097 #define AT91C_US1_TPR ( ( AT91_REG * ) 0xFFFC4108 ) /* (PDC_US1) Transmit Pointer Register */
2098 /* ========== Register definition for US1 peripheral ========== */
2099 #define AT91C_US1_IF ( ( AT91_REG * ) 0xFFFC404C ) /* (US1) IRDA_FILTER Register */
2100 #define AT91C_US1_NER ( ( AT91_REG * ) 0xFFFC4044 ) /* (US1) Nb Errors Register */
2101 #define AT91C_US1_RTOR ( ( AT91_REG * ) 0xFFFC4024 ) /* (US1) Receiver Time-out Register */
2102 #define AT91C_US1_CSR ( ( AT91_REG * ) 0xFFFC4014 ) /* (US1) Channel Status Register */
2103 #define AT91C_US1_IDR ( ( AT91_REG * ) 0xFFFC400C ) /* (US1) Interrupt Disable Register */
2104 #define AT91C_US1_IER ( ( AT91_REG * ) 0xFFFC4008 ) /* (US1) Interrupt Enable Register */
2105 #define AT91C_US1_THR ( ( AT91_REG * ) 0xFFFC401C ) /* (US1) Transmitter Holding Register */
2106 #define AT91C_US1_TTGR ( ( AT91_REG * ) 0xFFFC4028 ) /* (US1) Transmitter Time-guard Register */
2107 #define AT91C_US1_RHR ( ( AT91_REG * ) 0xFFFC4018 ) /* (US1) Receiver Holding Register */
2108 #define AT91C_US1_BRGR ( ( AT91_REG * ) 0xFFFC4020 ) /* (US1) Baud Rate Generator Register */
2109 #define AT91C_US1_IMR ( ( AT91_REG * ) 0xFFFC4010 ) /* (US1) Interrupt Mask Register */
2110 #define AT91C_US1_FIDI ( ( AT91_REG * ) 0xFFFC4040 ) /* (US1) FI_DI_Ratio Register */
2111 #define AT91C_US1_CR ( ( AT91_REG * ) 0xFFFC4000 ) /* (US1) Control Register */
2112 #define AT91C_US1_MR ( ( AT91_REG * ) 0xFFFC4004 ) /* (US1) Mode Register */
2113 /* ========== Register definition for PDC_US0 peripheral ========== */
2114 #define AT91C_US0_TNPR ( ( AT91_REG * ) 0xFFFC0118 ) /* (PDC_US0) Transmit Next Pointer Register */
2115 #define AT91C_US0_RNPR ( ( AT91_REG * ) 0xFFFC0110 ) /* (PDC_US0) Receive Next Pointer Register */
2116 #define AT91C_US0_TCR ( ( AT91_REG * ) 0xFFFC010C ) /* (PDC_US0) Transmit Counter Register */
2117 #define AT91C_US0_PTCR ( ( AT91_REG * ) 0xFFFC0120 ) /* (PDC_US0) PDC Transfer Control Register */
2118 #define AT91C_US0_PTSR ( ( AT91_REG * ) 0xFFFC0124 ) /* (PDC_US0) PDC Transfer Status Register */
2119 #define AT91C_US0_TNCR ( ( AT91_REG * ) 0xFFFC011C ) /* (PDC_US0) Transmit Next Counter Register */
2120 #define AT91C_US0_TPR ( ( AT91_REG * ) 0xFFFC0108 ) /* (PDC_US0) Transmit Pointer Register */
2121 #define AT91C_US0_RCR ( ( AT91_REG * ) 0xFFFC0104 ) /* (PDC_US0) Receive Counter Register */
2122 #define AT91C_US0_RPR ( ( AT91_REG * ) 0xFFFC0100 ) /* (PDC_US0) Receive Pointer Register */
2123 #define AT91C_US0_RNCR ( ( AT91_REG * ) 0xFFFC0114 ) /* (PDC_US0) Receive Next Counter Register */
2124 /* ========== Register definition for US0 peripheral ========== */
2125 #define AT91C_US0_BRGR ( ( AT91_REG * ) 0xFFFC0020 ) /* (US0) Baud Rate Generator Register */
2126 #define AT91C_US0_NER ( ( AT91_REG * ) 0xFFFC0044 ) /* (US0) Nb Errors Register */
2127 #define AT91C_US0_CR ( ( AT91_REG * ) 0xFFFC0000 ) /* (US0) Control Register */
2128 #define AT91C_US0_IMR ( ( AT91_REG * ) 0xFFFC0010 ) /* (US0) Interrupt Mask Register */
2129 #define AT91C_US0_FIDI ( ( AT91_REG * ) 0xFFFC0040 ) /* (US0) FI_DI_Ratio Register */
2130 #define AT91C_US0_TTGR ( ( AT91_REG * ) 0xFFFC0028 ) /* (US0) Transmitter Time-guard Register */
2131 #define AT91C_US0_MR ( ( AT91_REG * ) 0xFFFC0004 ) /* (US0) Mode Register */
2132 #define AT91C_US0_RTOR ( ( AT91_REG * ) 0xFFFC0024 ) /* (US0) Receiver Time-out Register */
2133 #define AT91C_US0_CSR ( ( AT91_REG * ) 0xFFFC0014 ) /* (US0) Channel Status Register */
2134 #define AT91C_US0_RHR ( ( AT91_REG * ) 0xFFFC0018 ) /* (US0) Receiver Holding Register */
2135 #define AT91C_US0_IDR ( ( AT91_REG * ) 0xFFFC000C ) /* (US0) Interrupt Disable Register */
2136 #define AT91C_US0_THR ( ( AT91_REG * ) 0xFFFC001C ) /* (US0) Transmitter Holding Register */
2137 #define AT91C_US0_IF ( ( AT91_REG * ) 0xFFFC004C ) /* (US0) IRDA_FILTER Register */
2138 #define AT91C_US0_IER ( ( AT91_REG * ) 0xFFFC0008 ) /* (US0) Interrupt Enable Register */
2139 /* ========== Register definition for PDC_SSC peripheral ========== */
2140 #define AT91C_SSC_TNCR ( ( AT91_REG * ) 0xFFFD411C ) /* (PDC_SSC) Transmit Next Counter Register */
2141 #define AT91C_SSC_RPR ( ( AT91_REG * ) 0xFFFD4100 ) /* (PDC_SSC) Receive Pointer Register */
2142 #define AT91C_SSC_RNCR ( ( AT91_REG * ) 0xFFFD4114 ) /* (PDC_SSC) Receive Next Counter Register */
2143 #define AT91C_SSC_TPR ( ( AT91_REG * ) 0xFFFD4108 ) /* (PDC_SSC) Transmit Pointer Register */
2144 #define AT91C_SSC_PTCR ( ( AT91_REG * ) 0xFFFD4120 ) /* (PDC_SSC) PDC Transfer Control Register */
2145 #define AT91C_SSC_TCR ( ( AT91_REG * ) 0xFFFD410C ) /* (PDC_SSC) Transmit Counter Register */
2146 #define AT91C_SSC_RCR ( ( AT91_REG * ) 0xFFFD4104 ) /* (PDC_SSC) Receive Counter Register */
2147 #define AT91C_SSC_RNPR ( ( AT91_REG * ) 0xFFFD4110 ) /* (PDC_SSC) Receive Next Pointer Register */
2148 #define AT91C_SSC_TNPR ( ( AT91_REG * ) 0xFFFD4118 ) /* (PDC_SSC) Transmit Next Pointer Register */
2149 #define AT91C_SSC_PTSR ( ( AT91_REG * ) 0xFFFD4124 ) /* (PDC_SSC) PDC Transfer Status Register */
2150 /* ========== Register definition for SSC peripheral ========== */
2151 #define AT91C_SSC_RHR ( ( AT91_REG * ) 0xFFFD4020 ) /* (SSC) Receive Holding Register */
2152 #define AT91C_SSC_RSHR ( ( AT91_REG * ) 0xFFFD4030 ) /* (SSC) Receive Sync Holding Register */
2153 #define AT91C_SSC_TFMR ( ( AT91_REG * ) 0xFFFD401C ) /* (SSC) Transmit Frame Mode Register */
2154 #define AT91C_SSC_IDR ( ( AT91_REG * ) 0xFFFD4048 ) /* (SSC) Interrupt Disable Register */
2155 #define AT91C_SSC_THR ( ( AT91_REG * ) 0xFFFD4024 ) /* (SSC) Transmit Holding Register */
2156 #define AT91C_SSC_RCMR ( ( AT91_REG * ) 0xFFFD4010 ) /* (SSC) Receive Clock ModeRegister */
2157 #define AT91C_SSC_IER ( ( AT91_REG * ) 0xFFFD4044 ) /* (SSC) Interrupt Enable Register */
2158 #define AT91C_SSC_TSHR ( ( AT91_REG * ) 0xFFFD4034 ) /* (SSC) Transmit Sync Holding Register */
2159 #define AT91C_SSC_SR ( ( AT91_REG * ) 0xFFFD4040 ) /* (SSC) Status Register */
2160 #define AT91C_SSC_CMR ( ( AT91_REG * ) 0xFFFD4004 ) /* (SSC) Clock Mode Register */
2161 #define AT91C_SSC_TCMR ( ( AT91_REG * ) 0xFFFD4018 ) /* (SSC) Transmit Clock Mode Register */
2162 #define AT91C_SSC_CR ( ( AT91_REG * ) 0xFFFD4000 ) /* (SSC) Control Register */
2163 #define AT91C_SSC_IMR ( ( AT91_REG * ) 0xFFFD404C ) /* (SSC) Interrupt Mask Register */
2164 #define AT91C_SSC_RFMR ( ( AT91_REG * ) 0xFFFD4014 ) /* (SSC) Receive Frame Mode Register */
2165 /* ========== Register definition for TWI peripheral ========== */
2166 #define AT91C_TWI_IER ( ( AT91_REG * ) 0xFFFB8024 ) /* (TWI) Interrupt Enable Register */
2167 #define AT91C_TWI_CR ( ( AT91_REG * ) 0xFFFB8000 ) /* (TWI) Control Register */
2168 #define AT91C_TWI_SR ( ( AT91_REG * ) 0xFFFB8020 ) /* (TWI) Status Register */
2169 #define AT91C_TWI_IMR ( ( AT91_REG * ) 0xFFFB802C ) /* (TWI) Interrupt Mask Register */
2170 #define AT91C_TWI_THR ( ( AT91_REG * ) 0xFFFB8034 ) /* (TWI) Transmit Holding Register */
2171 #define AT91C_TWI_IDR ( ( AT91_REG * ) 0xFFFB8028 ) /* (TWI) Interrupt Disable Register */
2172 #define AT91C_TWI_IADR ( ( AT91_REG * ) 0xFFFB800C ) /* (TWI) Internal Address Register */
2173 #define AT91C_TWI_MMR ( ( AT91_REG * ) 0xFFFB8004 ) /* (TWI) Master Mode Register */
2174 #define AT91C_TWI_CWGR ( ( AT91_REG * ) 0xFFFB8010 ) /* (TWI) Clock Waveform Generator Register */
2175 #define AT91C_TWI_RHR ( ( AT91_REG * ) 0xFFFB8030 ) /* (TWI) Receive Holding Register */
2176 /* ========== Register definition for PWMC_CH3 peripheral ========== */
2177 #define AT91C_PWMC_CH3_CUPDR ( ( AT91_REG * ) 0xFFFCC270 ) /* (PWMC_CH3) Channel Update Register */
2178 #define AT91C_PWMC_CH3_Reserved ( ( AT91_REG * ) 0xFFFCC274 ) /* (PWMC_CH3) Reserved */
2179 #define AT91C_PWMC_CH3_CPRDR ( ( AT91_REG * ) 0xFFFCC268 ) /* (PWMC_CH3) Channel Period Register */
2180 #define AT91C_PWMC_CH3_CDTYR ( ( AT91_REG * ) 0xFFFCC264 ) /* (PWMC_CH3) Channel Duty Cycle Register */
2181 #define AT91C_PWMC_CH3_CCNTR ( ( AT91_REG * ) 0xFFFCC26C ) /* (PWMC_CH3) Channel Counter Register */
2182 #define AT91C_PWMC_CH3_CMR ( ( AT91_REG * ) 0xFFFCC260 ) /* (PWMC_CH3) Channel Mode Register */
2183 /* ========== Register definition for PWMC_CH2 peripheral ========== */
2184 #define AT91C_PWMC_CH2_Reserved ( ( AT91_REG * ) 0xFFFCC254 ) /* (PWMC_CH2) Reserved */
2185 #define AT91C_PWMC_CH2_CMR ( ( AT91_REG * ) 0xFFFCC240 ) /* (PWMC_CH2) Channel Mode Register */
2186 #define AT91C_PWMC_CH2_CCNTR ( ( AT91_REG * ) 0xFFFCC24C ) /* (PWMC_CH2) Channel Counter Register */
2187 #define AT91C_PWMC_CH2_CPRDR ( ( AT91_REG * ) 0xFFFCC248 ) /* (PWMC_CH2) Channel Period Register */
2188 #define AT91C_PWMC_CH2_CUPDR ( ( AT91_REG * ) 0xFFFCC250 ) /* (PWMC_CH2) Channel Update Register */
2189 #define AT91C_PWMC_CH2_CDTYR ( ( AT91_REG * ) 0xFFFCC244 ) /* (PWMC_CH2) Channel Duty Cycle Register */
2190 /* ========== Register definition for PWMC_CH1 peripheral ========== */
2191 #define AT91C_PWMC_CH1_Reserved ( ( AT91_REG * ) 0xFFFCC234 ) /* (PWMC_CH1) Reserved */
2192 #define AT91C_PWMC_CH1_CUPDR ( ( AT91_REG * ) 0xFFFCC230 ) /* (PWMC_CH1) Channel Update Register */
2193 #define AT91C_PWMC_CH1_CPRDR ( ( AT91_REG * ) 0xFFFCC228 ) /* (PWMC_CH1) Channel Period Register */
2194 #define AT91C_PWMC_CH1_CCNTR ( ( AT91_REG * ) 0xFFFCC22C ) /* (PWMC_CH1) Channel Counter Register */
2195 #define AT91C_PWMC_CH1_CDTYR ( ( AT91_REG * ) 0xFFFCC224 ) /* (PWMC_CH1) Channel Duty Cycle Register */
2196 #define AT91C_PWMC_CH1_CMR ( ( AT91_REG * ) 0xFFFCC220 ) /* (PWMC_CH1) Channel Mode Register */
2197 /* ========== Register definition for PWMC_CH0 peripheral ========== */
2198 #define AT91C_PWMC_CH0_Reserved ( ( AT91_REG * ) 0xFFFCC214 ) /* (PWMC_CH0) Reserved */
2199 #define AT91C_PWMC_CH0_CPRDR ( ( AT91_REG * ) 0xFFFCC208 ) /* (PWMC_CH0) Channel Period Register */
2200 #define AT91C_PWMC_CH0_CDTYR ( ( AT91_REG * ) 0xFFFCC204 ) /* (PWMC_CH0) Channel Duty Cycle Register */
2201 #define AT91C_PWMC_CH0_CMR ( ( AT91_REG * ) 0xFFFCC200 ) /* (PWMC_CH0) Channel Mode Register */
2202 #define AT91C_PWMC_CH0_CUPDR ( ( AT91_REG * ) 0xFFFCC210 ) /* (PWMC_CH0) Channel Update Register */
2203 #define AT91C_PWMC_CH0_CCNTR ( ( AT91_REG * ) 0xFFFCC20C ) /* (PWMC_CH0) Channel Counter Register */
2204 /* ========== Register definition for PWMC peripheral ========== */
2205 #define AT91C_PWMC_IDR ( ( AT91_REG * ) 0xFFFCC014 ) /* (PWMC) PWMC Interrupt Disable Register */
2206 #define AT91C_PWMC_DIS ( ( AT91_REG * ) 0xFFFCC008 ) /* (PWMC) PWMC Disable Register */
2207 #define AT91C_PWMC_IER ( ( AT91_REG * ) 0xFFFCC010 ) /* (PWMC) PWMC Interrupt Enable Register */
2208 #define AT91C_PWMC_VR ( ( AT91_REG * ) 0xFFFCC0FC ) /* (PWMC) PWMC Version Register */
2209 #define AT91C_PWMC_ISR ( ( AT91_REG * ) 0xFFFCC01C ) /* (PWMC) PWMC Interrupt Status Register */
2210 #define AT91C_PWMC_SR ( ( AT91_REG * ) 0xFFFCC00C ) /* (PWMC) PWMC Status Register */
2211 #define AT91C_PWMC_IMR ( ( AT91_REG * ) 0xFFFCC018 ) /* (PWMC) PWMC Interrupt Mask Register */
2212 #define AT91C_PWMC_MR ( ( AT91_REG * ) 0xFFFCC000 ) /* (PWMC) PWMC Mode Register */
2213 #define AT91C_PWMC_ENA ( ( AT91_REG * ) 0xFFFCC004 ) /* (PWMC) PWMC Enable Register */
2214 /* ========== Register definition for UDP peripheral ========== */
2215 #define AT91C_UDP_IMR ( ( AT91_REG * ) 0xFFFB0018 ) /* (UDP) Interrupt Mask Register */
2216 #define AT91C_UDP_FADDR ( ( AT91_REG * ) 0xFFFB0008 ) /* (UDP) Function Address Register */
2217 #define AT91C_UDP_NUM ( ( AT91_REG * ) 0xFFFB0000 ) /* (UDP) Frame Number Register */
2218 #define AT91C_UDP_FDR ( ( AT91_REG * ) 0xFFFB0050 ) /* (UDP) Endpoint FIFO Data Register */
2219 #define AT91C_UDP_ISR ( ( AT91_REG * ) 0xFFFB001C ) /* (UDP) Interrupt Status Register */
2220 #define AT91C_UDP_CSR ( ( AT91_REG * ) 0xFFFB0030 ) /* (UDP) Endpoint Control and Status Register */
2221 #define AT91C_UDP_IDR ( ( AT91_REG * ) 0xFFFB0014 ) /* (UDP) Interrupt Disable Register */
2222 #define AT91C_UDP_ICR ( ( AT91_REG * ) 0xFFFB0020 ) /* (UDP) Interrupt Clear Register */
2223 #define AT91C_UDP_RSTEP ( ( AT91_REG * ) 0xFFFB0028 ) /* (UDP) Reset Endpoint Register */
2224 #define AT91C_UDP_TXVC ( ( AT91_REG * ) 0xFFFB0074 ) /* (UDP) Transceiver Control Register */
2225 #define AT91C_UDP_GLBSTATE ( ( AT91_REG * ) 0xFFFB0004 ) /* (UDP) Global State Register */
2226 #define AT91C_UDP_IER ( ( AT91_REG * ) 0xFFFB0010 ) /* (UDP) Interrupt Enable Register */
2227 /* ========== Register definition for TC0 peripheral ========== */
2228 #define AT91C_TC0_SR ( ( AT91_REG * ) 0xFFFA0020 ) /* (TC0) Status Register */
2229 #define AT91C_TC0_RC ( ( AT91_REG * ) 0xFFFA001C ) /* (TC0) Register C */
2230 #define AT91C_TC0_RB ( ( AT91_REG * ) 0xFFFA0018 ) /* (TC0) Register B */
2231 #define AT91C_TC0_CCR ( ( AT91_REG * ) 0xFFFA0000 ) /* (TC0) Channel Control Register */
2232 #define AT91C_TC0_CMR ( ( AT91_REG * ) 0xFFFA0004 ) /* (TC0) Channel Mode Register (Capture Mode / Waveform Mode) */
2233 #define AT91C_TC0_IER ( ( AT91_REG * ) 0xFFFA0024 ) /* (TC0) Interrupt Enable Register */
2234 #define AT91C_TC0_RA ( ( AT91_REG * ) 0xFFFA0014 ) /* (TC0) Register A */
2235 #define AT91C_TC0_IDR ( ( AT91_REG * ) 0xFFFA0028 ) /* (TC0) Interrupt Disable Register */
2236 #define AT91C_TC0_CV ( ( AT91_REG * ) 0xFFFA0010 ) /* (TC0) Counter Value */
2237 #define AT91C_TC0_IMR ( ( AT91_REG * ) 0xFFFA002C ) /* (TC0) Interrupt Mask Register */
2238 /* ========== Register definition for TC1 peripheral ========== */
2239 #define AT91C_TC1_RB ( ( AT91_REG * ) 0xFFFA0058 ) /* (TC1) Register B */
2240 #define AT91C_TC1_CCR ( ( AT91_REG * ) 0xFFFA0040 ) /* (TC1) Channel Control Register */
2241 #define AT91C_TC1_IER ( ( AT91_REG * ) 0xFFFA0064 ) /* (TC1) Interrupt Enable Register */
2242 #define AT91C_TC1_IDR ( ( AT91_REG * ) 0xFFFA0068 ) /* (TC1) Interrupt Disable Register */
2243 #define AT91C_TC1_SR ( ( AT91_REG * ) 0xFFFA0060 ) /* (TC1) Status Register */
2244 #define AT91C_TC1_CMR ( ( AT91_REG * ) 0xFFFA0044 ) /* (TC1) Channel Mode Register (Capture Mode / Waveform Mode) */
2245 #define AT91C_TC1_RA ( ( AT91_REG * ) 0xFFFA0054 ) /* (TC1) Register A */
2246 #define AT91C_TC1_RC ( ( AT91_REG * ) 0xFFFA005C ) /* (TC1) Register C */
2247 #define AT91C_TC1_IMR ( ( AT91_REG * ) 0xFFFA006C ) /* (TC1) Interrupt Mask Register */
2248 #define AT91C_TC1_CV ( ( AT91_REG * ) 0xFFFA0050 ) /* (TC1) Counter Value */
2249 /* ========== Register definition for TC2 peripheral ========== */
2250 #define AT91C_TC2_CMR ( ( AT91_REG * ) 0xFFFA0084 ) /* (TC2) Channel Mode Register (Capture Mode / Waveform Mode) */
2251 #define AT91C_TC2_CCR ( ( AT91_REG * ) 0xFFFA0080 ) /* (TC2) Channel Control Register */
2252 #define AT91C_TC2_CV ( ( AT91_REG * ) 0xFFFA0090 ) /* (TC2) Counter Value */
2253 #define AT91C_TC2_RA ( ( AT91_REG * ) 0xFFFA0094 ) /* (TC2) Register A */
2254 #define AT91C_TC2_RB ( ( AT91_REG * ) 0xFFFA0098 ) /* (TC2) Register B */
2255 #define AT91C_TC2_IDR ( ( AT91_REG * ) 0xFFFA00A8 ) /* (TC2) Interrupt Disable Register */
2256 #define AT91C_TC2_IMR ( ( AT91_REG * ) 0xFFFA00AC ) /* (TC2) Interrupt Mask Register */
2257 #define AT91C_TC2_RC ( ( AT91_REG * ) 0xFFFA009C ) /* (TC2) Register C */
2258 #define AT91C_TC2_IER ( ( AT91_REG * ) 0xFFFA00A4 ) /* (TC2) Interrupt Enable Register */
2259 #define AT91C_TC2_SR ( ( AT91_REG * ) 0xFFFA00A0 ) /* (TC2) Status Register */
2260 /* ========== Register definition for TCB peripheral ========== */
2261 #define AT91C_TCB_BMR ( ( AT91_REG * ) 0xFFFA00C4 ) /* (TCB) TC Block Mode Register */
2262 #define AT91C_TCB_BCR ( ( AT91_REG * ) 0xFFFA00C0 ) /* (TCB) TC Block Control Register */
2263 /* ========== Register definition for CAN_MB0 peripheral ========== */
2264 #define AT91C_CAN_MB0_MDL ( ( AT91_REG * ) 0xFFFD0214 ) /* (CAN_MB0) MailBox Data Low Register */
2265 #define AT91C_CAN_MB0_MAM ( ( AT91_REG * ) 0xFFFD0204 ) /* (CAN_MB0) MailBox Acceptance Mask Register */
2266 #define AT91C_CAN_MB0_MCR ( ( AT91_REG * ) 0xFFFD021C ) /* (CAN_MB0) MailBox Control Register */
2267 #define AT91C_CAN_MB0_MID ( ( AT91_REG * ) 0xFFFD0208 ) /* (CAN_MB0) MailBox ID Register */
2268 #define AT91C_CAN_MB0_MSR ( ( AT91_REG * ) 0xFFFD0210 ) /* (CAN_MB0) MailBox Status Register */
2269 #define AT91C_CAN_MB0_MFID ( ( AT91_REG * ) 0xFFFD020C ) /* (CAN_MB0) MailBox Family ID Register */
2270 #define AT91C_CAN_MB0_MDH ( ( AT91_REG * ) 0xFFFD0218 ) /* (CAN_MB0) MailBox Data High Register */
2271 #define AT91C_CAN_MB0_MMR ( ( AT91_REG * ) 0xFFFD0200 ) /* (CAN_MB0) MailBox Mode Register */
2272 /* ========== Register definition for CAN_MB1 peripheral ========== */
2273 #define AT91C_CAN_MB1_MDL ( ( AT91_REG * ) 0xFFFD0234 ) /* (CAN_MB1) MailBox Data Low Register */
2274 #define AT91C_CAN_MB1_MID ( ( AT91_REG * ) 0xFFFD0228 ) /* (CAN_MB1) MailBox ID Register */
2275 #define AT91C_CAN_MB1_MMR ( ( AT91_REG * ) 0xFFFD0220 ) /* (CAN_MB1) MailBox Mode Register */
2276 #define AT91C_CAN_MB1_MSR ( ( AT91_REG * ) 0xFFFD0230 ) /* (CAN_MB1) MailBox Status Register */
2277 #define AT91C_CAN_MB1_MAM ( ( AT91_REG * ) 0xFFFD0224 ) /* (CAN_MB1) MailBox Acceptance Mask Register */
2278 #define AT91C_CAN_MB1_MDH ( ( AT91_REG * ) 0xFFFD0238 ) /* (CAN_MB1) MailBox Data High Register */
2279 #define AT91C_CAN_MB1_MCR ( ( AT91_REG * ) 0xFFFD023C ) /* (CAN_MB1) MailBox Control Register */
2280 #define AT91C_CAN_MB1_MFID ( ( AT91_REG * ) 0xFFFD022C ) /* (CAN_MB1) MailBox Family ID Register */
2281 /* ========== Register definition for CAN_MB2 peripheral ========== */
2282 #define AT91C_CAN_MB2_MCR ( ( AT91_REG * ) 0xFFFD025C ) /* (CAN_MB2) MailBox Control Register */
2283 #define AT91C_CAN_MB2_MDH ( ( AT91_REG * ) 0xFFFD0258 ) /* (CAN_MB2) MailBox Data High Register */
2284 #define AT91C_CAN_MB2_MID ( ( AT91_REG * ) 0xFFFD0248 ) /* (CAN_MB2) MailBox ID Register */
2285 #define AT91C_CAN_MB2_MDL ( ( AT91_REG * ) 0xFFFD0254 ) /* (CAN_MB2) MailBox Data Low Register */
2286 #define AT91C_CAN_MB2_MMR ( ( AT91_REG * ) 0xFFFD0240 ) /* (CAN_MB2) MailBox Mode Register */
2287 #define AT91C_CAN_MB2_MAM ( ( AT91_REG * ) 0xFFFD0244 ) /* (CAN_MB2) MailBox Acceptance Mask Register */
2288 #define AT91C_CAN_MB2_MFID ( ( AT91_REG * ) 0xFFFD024C ) /* (CAN_MB2) MailBox Family ID Register */
2289 #define AT91C_CAN_MB2_MSR ( ( AT91_REG * ) 0xFFFD0250 ) /* (CAN_MB2) MailBox Status Register */
2290 /* ========== Register definition for CAN_MB3 peripheral ========== */
2291 #define AT91C_CAN_MB3_MFID ( ( AT91_REG * ) 0xFFFD026C ) /* (CAN_MB3) MailBox Family ID Register */
2292 #define AT91C_CAN_MB3_MAM ( ( AT91_REG * ) 0xFFFD0264 ) /* (CAN_MB3) MailBox Acceptance Mask Register */
2293 #define AT91C_CAN_MB3_MID ( ( AT91_REG * ) 0xFFFD0268 ) /* (CAN_MB3) MailBox ID Register */
2294 #define AT91C_CAN_MB3_MCR ( ( AT91_REG * ) 0xFFFD027C ) /* (CAN_MB3) MailBox Control Register */
2295 #define AT91C_CAN_MB3_MMR ( ( AT91_REG * ) 0xFFFD0260 ) /* (CAN_MB3) MailBox Mode Register */
2296 #define AT91C_CAN_MB3_MSR ( ( AT91_REG * ) 0xFFFD0270 ) /* (CAN_MB3) MailBox Status Register */
2297 #define AT91C_CAN_MB3_MDL ( ( AT91_REG * ) 0xFFFD0274 ) /* (CAN_MB3) MailBox Data Low Register */
2298 #define AT91C_CAN_MB3_MDH ( ( AT91_REG * ) 0xFFFD0278 ) /* (CAN_MB3) MailBox Data High Register */
2299 /* ========== Register definition for CAN_MB4 peripheral ========== */
2300 #define AT91C_CAN_MB4_MID ( ( AT91_REG * ) 0xFFFD0288 ) /* (CAN_MB4) MailBox ID Register */
2301 #define AT91C_CAN_MB4_MMR ( ( AT91_REG * ) 0xFFFD0280 ) /* (CAN_MB4) MailBox Mode Register */
2302 #define AT91C_CAN_MB4_MDH ( ( AT91_REG * ) 0xFFFD0298 ) /* (CAN_MB4) MailBox Data High Register */
2303 #define AT91C_CAN_MB4_MFID ( ( AT91_REG * ) 0xFFFD028C ) /* (CAN_MB4) MailBox Family ID Register */
2304 #define AT91C_CAN_MB4_MSR ( ( AT91_REG * ) 0xFFFD0290 ) /* (CAN_MB4) MailBox Status Register */
2305 #define AT91C_CAN_MB4_MCR ( ( AT91_REG * ) 0xFFFD029C ) /* (CAN_MB4) MailBox Control Register */
2306 #define AT91C_CAN_MB4_MDL ( ( AT91_REG * ) 0xFFFD0294 ) /* (CAN_MB4) MailBox Data Low Register */
2307 #define AT91C_CAN_MB4_MAM ( ( AT91_REG * ) 0xFFFD0284 ) /* (CAN_MB4) MailBox Acceptance Mask Register */
2308 /* ========== Register definition for CAN_MB5 peripheral ========== */
2309 #define AT91C_CAN_MB5_MSR ( ( AT91_REG * ) 0xFFFD02B0 ) /* (CAN_MB5) MailBox Status Register */
2310 #define AT91C_CAN_MB5_MCR ( ( AT91_REG * ) 0xFFFD02BC ) /* (CAN_MB5) MailBox Control Register */
2311 #define AT91C_CAN_MB5_MFID ( ( AT91_REG * ) 0xFFFD02AC ) /* (CAN_MB5) MailBox Family ID Register */
2312 #define AT91C_CAN_MB5_MDH ( ( AT91_REG * ) 0xFFFD02B8 ) /* (CAN_MB5) MailBox Data High Register */
2313 #define AT91C_CAN_MB5_MID ( ( AT91_REG * ) 0xFFFD02A8 ) /* (CAN_MB5) MailBox ID Register */
2314 #define AT91C_CAN_MB5_MMR ( ( AT91_REG * ) 0xFFFD02A0 ) /* (CAN_MB5) MailBox Mode Register */
2315 #define AT91C_CAN_MB5_MDL ( ( AT91_REG * ) 0xFFFD02B4 ) /* (CAN_MB5) MailBox Data Low Register */
2316 #define AT91C_CAN_MB5_MAM ( ( AT91_REG * ) 0xFFFD02A4 ) /* (CAN_MB5) MailBox Acceptance Mask Register */
2317 /* ========== Register definition for CAN_MB6 peripheral ========== */
2318 #define AT91C_CAN_MB6_MFID ( ( AT91_REG * ) 0xFFFD02CC ) /* (CAN_MB6) MailBox Family ID Register */
2319 #define AT91C_CAN_MB6_MID ( ( AT91_REG * ) 0xFFFD02C8 ) /* (CAN_MB6) MailBox ID Register */
2320 #define AT91C_CAN_MB6_MAM ( ( AT91_REG * ) 0xFFFD02C4 ) /* (CAN_MB6) MailBox Acceptance Mask Register */
2321 #define AT91C_CAN_MB6_MSR ( ( AT91_REG * ) 0xFFFD02D0 ) /* (CAN_MB6) MailBox Status Register */
2322 #define AT91C_CAN_MB6_MDL ( ( AT91_REG * ) 0xFFFD02D4 ) /* (CAN_MB6) MailBox Data Low Register */
2323 #define AT91C_CAN_MB6_MCR ( ( AT91_REG * ) 0xFFFD02DC ) /* (CAN_MB6) MailBox Control Register */
2324 #define AT91C_CAN_MB6_MDH ( ( AT91_REG * ) 0xFFFD02D8 ) /* (CAN_MB6) MailBox Data High Register */
2325 #define AT91C_CAN_MB6_MMR ( ( AT91_REG * ) 0xFFFD02C0 ) /* (CAN_MB6) MailBox Mode Register */
2326 /* ========== Register definition for CAN_MB7 peripheral ========== */
2327 #define AT91C_CAN_MB7_MCR ( ( AT91_REG * ) 0xFFFD02FC ) /* (CAN_MB7) MailBox Control Register */
2328 #define AT91C_CAN_MB7_MDH ( ( AT91_REG * ) 0xFFFD02F8 ) /* (CAN_MB7) MailBox Data High Register */
2329 #define AT91C_CAN_MB7_MFID ( ( AT91_REG * ) 0xFFFD02EC ) /* (CAN_MB7) MailBox Family ID Register */
2330 #define AT91C_CAN_MB7_MDL ( ( AT91_REG * ) 0xFFFD02F4 ) /* (CAN_MB7) MailBox Data Low Register */
2331 #define AT91C_CAN_MB7_MID ( ( AT91_REG * ) 0xFFFD02E8 ) /* (CAN_MB7) MailBox ID Register */
2332 #define AT91C_CAN_MB7_MMR ( ( AT91_REG * ) 0xFFFD02E0 ) /* (CAN_MB7) MailBox Mode Register */
2333 #define AT91C_CAN_MB7_MAM ( ( AT91_REG * ) 0xFFFD02E4 ) /* (CAN_MB7) MailBox Acceptance Mask Register */
2334 #define AT91C_CAN_MB7_MSR ( ( AT91_REG * ) 0xFFFD02F0 ) /* (CAN_MB7) MailBox Status Register */
2335 /* ========== Register definition for CAN peripheral ========== */
2336 #define AT91C_CAN_TCR ( ( AT91_REG * ) 0xFFFD0024 ) /* (CAN) Transfer Command Register */
2337 #define AT91C_CAN_IMR ( ( AT91_REG * ) 0xFFFD000C ) /* (CAN) Interrupt Mask Register */
2338 #define AT91C_CAN_IER ( ( AT91_REG * ) 0xFFFD0004 ) /* (CAN) Interrupt Enable Register */
2339 #define AT91C_CAN_ECR ( ( AT91_REG * ) 0xFFFD0020 ) /* (CAN) Error Counter Register */
2340 #define AT91C_CAN_TIMESTP ( ( AT91_REG * ) 0xFFFD001C ) /* (CAN) Time Stamp Register */
2341 #define AT91C_CAN_MR ( ( AT91_REG * ) 0xFFFD0000 ) /* (CAN) Mode Register */
2342 #define AT91C_CAN_IDR ( ( AT91_REG * ) 0xFFFD0008 ) /* (CAN) Interrupt Disable Register */
2343 #define AT91C_CAN_ACR ( ( AT91_REG * ) 0xFFFD0028 ) /* (CAN) Abort Command Register */
2344 #define AT91C_CAN_TIM ( ( AT91_REG * ) 0xFFFD0018 ) /* (CAN) Timer Register */
2345 #define AT91C_CAN_SR ( ( AT91_REG * ) 0xFFFD0010 ) /* (CAN) Status Register */
2346 #define AT91C_CAN_BR ( ( AT91_REG * ) 0xFFFD0014 ) /* (CAN) Baudrate Register */
2347 #define AT91C_CAN_VR ( ( AT91_REG * ) 0xFFFD00FC ) /* (CAN) Version Register */
2348 /* ========== Register definition for EMAC peripheral ========== */
2349 #define AT91C_EMAC_ISR ( ( AT91_REG * ) 0xFFFDC024 ) /* (EMAC) Interrupt Status Register */
2350 #define AT91C_EMAC_SA4H ( ( AT91_REG * ) 0xFFFDC0B4 ) /* (EMAC) Specific Address 4 Top, Last 2 bytes */
2351 #define AT91C_EMAC_SA1L ( ( AT91_REG * ) 0xFFFDC098 ) /* (EMAC) Specific Address 1 Bottom, First 4 bytes */
2352 #define AT91C_EMAC_ELE ( ( AT91_REG * ) 0xFFFDC078 ) /* (EMAC) Excessive Length Errors Register */
2353 #define AT91C_EMAC_LCOL ( ( AT91_REG * ) 0xFFFDC05C ) /* (EMAC) Late Collision Register */
2354 #define AT91C_EMAC_RLE ( ( AT91_REG * ) 0xFFFDC088 ) /* (EMAC) Receive Length Field Mismatch Register */
2355 #define AT91C_EMAC_WOL ( ( AT91_REG * ) 0xFFFDC0C4 ) /* (EMAC) Wake On LAN Register */
2356 #define AT91C_EMAC_DTF ( ( AT91_REG * ) 0xFFFDC058 ) /* (EMAC) Deferred Transmission Frame Register */
2357 #define AT91C_EMAC_TUND ( ( AT91_REG * ) 0xFFFDC064 ) /* (EMAC) Transmit Underrun Error Register */
2358 #define AT91C_EMAC_NCR ( ( AT91_REG * ) 0xFFFDC000 ) /* (EMAC) Network Control Register */
2359 #define AT91C_EMAC_SA4L ( ( AT91_REG * ) 0xFFFDC0B0 ) /* (EMAC) Specific Address 4 Bottom, First 4 bytes */
2360 #define AT91C_EMAC_RSR ( ( AT91_REG * ) 0xFFFDC020 ) /* (EMAC) Receive Status Register */
2361 #define AT91C_EMAC_SA3L ( ( AT91_REG * ) 0xFFFDC0A8 ) /* (EMAC) Specific Address 3 Bottom, First 4 bytes */
2362 #define AT91C_EMAC_TSR ( ( AT91_REG * ) 0xFFFDC014 ) /* (EMAC) Transmit Status Register */
2363 #define AT91C_EMAC_IDR ( ( AT91_REG * ) 0xFFFDC02C ) /* (EMAC) Interrupt Disable Register */
2364 #define AT91C_EMAC_RSE ( ( AT91_REG * ) 0xFFFDC074 ) /* (EMAC) Receive Symbol Errors Register */
2365 #define AT91C_EMAC_ECOL ( ( AT91_REG * ) 0xFFFDC060 ) /* (EMAC) Excessive Collision Register */
2366 #define AT91C_EMAC_TID ( ( AT91_REG * ) 0xFFFDC0B8 ) /* (EMAC) Type ID Checking Register */
2367 #define AT91C_EMAC_HRB ( ( AT91_REG * ) 0xFFFDC090 ) /* (EMAC) Hash Address Bottom[31:0] */
2368 #define AT91C_EMAC_TBQP ( ( AT91_REG * ) 0xFFFDC01C ) /* (EMAC) Transmit Buffer Queue Pointer */
2369 #define AT91C_EMAC_USRIO ( ( AT91_REG * ) 0xFFFDC0C0 ) /* (EMAC) USER Input/Output Register */
2370 #define AT91C_EMAC_PTR ( ( AT91_REG * ) 0xFFFDC038 ) /* (EMAC) Pause Time Register */
2371 #define AT91C_EMAC_SA2H ( ( AT91_REG * ) 0xFFFDC0A4 ) /* (EMAC) Specific Address 2 Top, Last 2 bytes */
2372 #define AT91C_EMAC_ROV ( ( AT91_REG * ) 0xFFFDC070 ) /* (EMAC) Receive Overrun Errors Register */
2373 #define AT91C_EMAC_ALE ( ( AT91_REG * ) 0xFFFDC054 ) /* (EMAC) Alignment Error Register */
2374 #define AT91C_EMAC_RJA ( ( AT91_REG * ) 0xFFFDC07C ) /* (EMAC) Receive Jabbers Register */
2375 #define AT91C_EMAC_RBQP ( ( AT91_REG * ) 0xFFFDC018 ) /* (EMAC) Receive Buffer Queue Pointer */
2376 #define AT91C_EMAC_TPF ( ( AT91_REG * ) 0xFFFDC08C ) /* (EMAC) Transmitted Pause Frames Register */
2377 #define AT91C_EMAC_NCFGR ( ( AT91_REG * ) 0xFFFDC004 ) /* (EMAC) Network Configuration Register */
2378 #define AT91C_EMAC_HRT ( ( AT91_REG * ) 0xFFFDC094 ) /* (EMAC) Hash Address Top[63:32] */
2379 #define AT91C_EMAC_USF ( ( AT91_REG * ) 0xFFFDC080 ) /* (EMAC) Undersize Frames Register */
2380 #define AT91C_EMAC_FCSE ( ( AT91_REG * ) 0xFFFDC050 ) /* (EMAC) Frame Check Sequence Error Register */
2381 #define AT91C_EMAC_TPQ ( ( AT91_REG * ) 0xFFFDC0BC ) /* (EMAC) Transmit Pause Quantum Register */
2382 #define AT91C_EMAC_MAN ( ( AT91_REG * ) 0xFFFDC034 ) /* (EMAC) PHY Maintenance Register */
2383 #define AT91C_EMAC_FTO ( ( AT91_REG * ) 0xFFFDC040 ) /* (EMAC) Frames Transmitted OK Register */
2384 #define AT91C_EMAC_REV ( ( AT91_REG * ) 0xFFFDC0FC ) /* (EMAC) Revision Register */
2385 #define AT91C_EMAC_IMR ( ( AT91_REG * ) 0xFFFDC030 ) /* (EMAC) Interrupt Mask Register */
2386 #define AT91C_EMAC_SCF ( ( AT91_REG * ) 0xFFFDC044 ) /* (EMAC) Single Collision Frame Register */
2387 #define AT91C_EMAC_PFR ( ( AT91_REG * ) 0xFFFDC03C ) /* (EMAC) Pause Frames received Register */
2388 #define AT91C_EMAC_MCF ( ( AT91_REG * ) 0xFFFDC048 ) /* (EMAC) Multiple Collision Frame Register */
2389 #define AT91C_EMAC_NSR ( ( AT91_REG * ) 0xFFFDC008 ) /* (EMAC) Network Status Register */
2390 #define AT91C_EMAC_SA2L ( ( AT91_REG * ) 0xFFFDC0A0 ) /* (EMAC) Specific Address 2 Bottom, First 4 bytes */
2391 #define AT91C_EMAC_FRO ( ( AT91_REG * ) 0xFFFDC04C ) /* (EMAC) Frames Received OK Register */
2392 #define AT91C_EMAC_IER ( ( AT91_REG * ) 0xFFFDC028 ) /* (EMAC) Interrupt Enable Register */
2393 #define AT91C_EMAC_SA1H ( ( AT91_REG * ) 0xFFFDC09C ) /* (EMAC) Specific Address 1 Top, Last 2 bytes */
2394 #define AT91C_EMAC_CSE ( ( AT91_REG * ) 0xFFFDC068 ) /* (EMAC) Carrier Sense Error Register */
2395 #define AT91C_EMAC_SA3H ( ( AT91_REG * ) 0xFFFDC0AC ) /* (EMAC) Specific Address 3 Top, Last 2 bytes */
2396 #define AT91C_EMAC_RRE ( ( AT91_REG * ) 0xFFFDC06C ) /* (EMAC) Receive Resource Error Register */
2397 #define AT91C_EMAC_STE ( ( AT91_REG * ) 0xFFFDC084 ) /* (EMAC) SQE Test Error Register */
2398 /* ========== Register definition for PDC_ADC peripheral ========== */
2399 #define AT91C_ADC_PTSR ( ( AT91_REG * ) 0xFFFD8124 ) /* (PDC_ADC) PDC Transfer Status Register */
2400 #define AT91C_ADC_PTCR ( ( AT91_REG * ) 0xFFFD8120 ) /* (PDC_ADC) PDC Transfer Control Register */
2401 #define AT91C_ADC_TNPR ( ( AT91_REG * ) 0xFFFD8118 ) /* (PDC_ADC) Transmit Next Pointer Register */
2402 #define AT91C_ADC_TNCR ( ( AT91_REG * ) 0xFFFD811C ) /* (PDC_ADC) Transmit Next Counter Register */
2403 #define AT91C_ADC_RNPR ( ( AT91_REG * ) 0xFFFD8110 ) /* (PDC_ADC) Receive Next Pointer Register */
2404 #define AT91C_ADC_RNCR ( ( AT91_REG * ) 0xFFFD8114 ) /* (PDC_ADC) Receive Next Counter Register */
2405 #define AT91C_ADC_RPR ( ( AT91_REG * ) 0xFFFD8100 ) /* (PDC_ADC) Receive Pointer Register */
2406 #define AT91C_ADC_TCR ( ( AT91_REG * ) 0xFFFD810C ) /* (PDC_ADC) Transmit Counter Register */
2407 #define AT91C_ADC_TPR ( ( AT91_REG * ) 0xFFFD8108 ) /* (PDC_ADC) Transmit Pointer Register */
2408 #define AT91C_ADC_RCR ( ( AT91_REG * ) 0xFFFD8104 ) /* (PDC_ADC) Receive Counter Register */
2409 /* ========== Register definition for ADC peripheral ========== */
2410 #define AT91C_ADC_CDR2 ( ( AT91_REG * ) 0xFFFD8038 ) /* (ADC) ADC Channel Data Register 2 */
2411 #define AT91C_ADC_CDR3 ( ( AT91_REG * ) 0xFFFD803C ) /* (ADC) ADC Channel Data Register 3 */
2412 #define AT91C_ADC_CDR0 ( ( AT91_REG * ) 0xFFFD8030 ) /* (ADC) ADC Channel Data Register 0 */
2413 #define AT91C_ADC_CDR5 ( ( AT91_REG * ) 0xFFFD8044 ) /* (ADC) ADC Channel Data Register 5 */
2414 #define AT91C_ADC_CHDR ( ( AT91_REG * ) 0xFFFD8014 ) /* (ADC) ADC Channel Disable Register */
2415 #define AT91C_ADC_SR ( ( AT91_REG * ) 0xFFFD801C ) /* (ADC) ADC Status Register */
2416 #define AT91C_ADC_CDR4 ( ( AT91_REG * ) 0xFFFD8040 ) /* (ADC) ADC Channel Data Register 4 */
2417 #define AT91C_ADC_CDR1 ( ( AT91_REG * ) 0xFFFD8034 ) /* (ADC) ADC Channel Data Register 1 */
2418 #define AT91C_ADC_LCDR ( ( AT91_REG * ) 0xFFFD8020 ) /* (ADC) ADC Last Converted Data Register */
2419 #define AT91C_ADC_IDR ( ( AT91_REG * ) 0xFFFD8028 ) /* (ADC) ADC Interrupt Disable Register */
2420 #define AT91C_ADC_CR ( ( AT91_REG * ) 0xFFFD8000 ) /* (ADC) ADC Control Register */
2421 #define AT91C_ADC_CDR7 ( ( AT91_REG * ) 0xFFFD804C ) /* (ADC) ADC Channel Data Register 7 */
2422 #define AT91C_ADC_CDR6 ( ( AT91_REG * ) 0xFFFD8048 ) /* (ADC) ADC Channel Data Register 6 */
2423 #define AT91C_ADC_IER ( ( AT91_REG * ) 0xFFFD8024 ) /* (ADC) ADC Interrupt Enable Register */
2424 #define AT91C_ADC_CHER ( ( AT91_REG * ) 0xFFFD8010 ) /* (ADC) ADC Channel Enable Register */
2425 #define AT91C_ADC_CHSR ( ( AT91_REG * ) 0xFFFD8018 ) /* (ADC) ADC Channel Status Register */
2426 #define AT91C_ADC_MR ( ( AT91_REG * ) 0xFFFD8004 ) /* (ADC) ADC Mode Register */
2427 #define AT91C_ADC_IMR ( ( AT91_REG * ) 0xFFFD802C ) /* (ADC) ADC Interrupt Mask Register */
2428 /* ========== Register definition for PDC_AES peripheral ========== */
2429 #define AT91C_AES_TPR ( ( AT91_REG * ) 0xFFFA4108 ) /* (PDC_AES) Transmit Pointer Register */
2430 #define AT91C_AES_PTCR ( ( AT91_REG * ) 0xFFFA4120 ) /* (PDC_AES) PDC Transfer Control Register */
2431 #define AT91C_AES_RNPR ( ( AT91_REG * ) 0xFFFA4110 ) /* (PDC_AES) Receive Next Pointer Register */
2432 #define AT91C_AES_TNCR ( ( AT91_REG * ) 0xFFFA411C ) /* (PDC_AES) Transmit Next Counter Register */
2433 #define AT91C_AES_TCR ( ( AT91_REG * ) 0xFFFA410C ) /* (PDC_AES) Transmit Counter Register */
2434 #define AT91C_AES_RCR ( ( AT91_REG * ) 0xFFFA4104 ) /* (PDC_AES) Receive Counter Register */
2435 #define AT91C_AES_RNCR ( ( AT91_REG * ) 0xFFFA4114 ) /* (PDC_AES) Receive Next Counter Register */
2436 #define AT91C_AES_TNPR ( ( AT91_REG * ) 0xFFFA4118 ) /* (PDC_AES) Transmit Next Pointer Register */
2437 #define AT91C_AES_RPR ( ( AT91_REG * ) 0xFFFA4100 ) /* (PDC_AES) Receive Pointer Register */
2438 #define AT91C_AES_PTSR ( ( AT91_REG * ) 0xFFFA4124 ) /* (PDC_AES) PDC Transfer Status Register */
2439 /* ========== Register definition for AES peripheral ========== */
2440 #define AT91C_AES_IVxR ( ( AT91_REG * ) 0xFFFA4060 ) /* (AES) Initialization Vector x Register */
2441 #define AT91C_AES_MR ( ( AT91_REG * ) 0xFFFA4004 ) /* (AES) Mode Register */
2442 #define AT91C_AES_VR ( ( AT91_REG * ) 0xFFFA40FC ) /* (AES) AES Version Register */
2443 #define AT91C_AES_ODATAxR ( ( AT91_REG * ) 0xFFFA4050 ) /* (AES) Output Data x Register */
2444 #define AT91C_AES_IDATAxR ( ( AT91_REG * ) 0xFFFA4040 ) /* (AES) Input Data x Register */
2445 #define AT91C_AES_CR ( ( AT91_REG * ) 0xFFFA4000 ) /* (AES) Control Register */
2446 #define AT91C_AES_IDR ( ( AT91_REG * ) 0xFFFA4014 ) /* (AES) Interrupt Disable Register */
2447 #define AT91C_AES_IMR ( ( AT91_REG * ) 0xFFFA4018 ) /* (AES) Interrupt Mask Register */
2448 #define AT91C_AES_IER ( ( AT91_REG * ) 0xFFFA4010 ) /* (AES) Interrupt Enable Register */
2449 #define AT91C_AES_KEYWxR ( ( AT91_REG * ) 0xFFFA4020 ) /* (AES) Key Word x Register */
2450 #define AT91C_AES_ISR ( ( AT91_REG * ) 0xFFFA401C ) /* (AES) Interrupt Status Register */
2451 /* ========== Register definition for PDC_TDES peripheral ========== */
2452 #define AT91C_TDES_RNCR ( ( AT91_REG * ) 0xFFFA8114 ) /* (PDC_TDES) Receive Next Counter Register */
2453 #define AT91C_TDES_TCR ( ( AT91_REG * ) 0xFFFA810C ) /* (PDC_TDES) Transmit Counter Register */
2454 #define AT91C_TDES_RCR ( ( AT91_REG * ) 0xFFFA8104 ) /* (PDC_TDES) Receive Counter Register */
2455 #define AT91C_TDES_TNPR ( ( AT91_REG * ) 0xFFFA8118 ) /* (PDC_TDES) Transmit Next Pointer Register */
2456 #define AT91C_TDES_RNPR ( ( AT91_REG * ) 0xFFFA8110 ) /* (PDC_TDES) Receive Next Pointer Register */
2457 #define AT91C_TDES_RPR ( ( AT91_REG * ) 0xFFFA8100 ) /* (PDC_TDES) Receive Pointer Register */
2458 #define AT91C_TDES_TNCR ( ( AT91_REG * ) 0xFFFA811C ) /* (PDC_TDES) Transmit Next Counter Register */
2459 #define AT91C_TDES_TPR ( ( AT91_REG * ) 0xFFFA8108 ) /* (PDC_TDES) Transmit Pointer Register */
2460 #define AT91C_TDES_PTSR ( ( AT91_REG * ) 0xFFFA8124 ) /* (PDC_TDES) PDC Transfer Status Register */
2461 #define AT91C_TDES_PTCR ( ( AT91_REG * ) 0xFFFA8120 ) /* (PDC_TDES) PDC Transfer Control Register */
2462 /* ========== Register definition for TDES peripheral ========== */
2463 #define AT91C_TDES_KEY2WxR ( ( AT91_REG * ) 0xFFFA8028 ) /* (TDES) Key 2 Word x Register */
2464 #define AT91C_TDES_KEY3WxR ( ( AT91_REG * ) 0xFFFA8030 ) /* (TDES) Key 3 Word x Register */
2465 #define AT91C_TDES_IDR ( ( AT91_REG * ) 0xFFFA8014 ) /* (TDES) Interrupt Disable Register */
2466 #define AT91C_TDES_VR ( ( AT91_REG * ) 0xFFFA80FC ) /* (TDES) TDES Version Register */
2467 #define AT91C_TDES_IVxR ( ( AT91_REG * ) 0xFFFA8060 ) /* (TDES) Initialization Vector x Register */
2468 #define AT91C_TDES_ODATAxR ( ( AT91_REG * ) 0xFFFA8050 ) /* (TDES) Output Data x Register */
2469 #define AT91C_TDES_IMR ( ( AT91_REG * ) 0xFFFA8018 ) /* (TDES) Interrupt Mask Register */
2470 #define AT91C_TDES_MR ( ( AT91_REG * ) 0xFFFA8004 ) /* (TDES) Mode Register */
2471 #define AT91C_TDES_CR ( ( AT91_REG * ) 0xFFFA8000 ) /* (TDES) Control Register */
2472 #define AT91C_TDES_IER ( ( AT91_REG * ) 0xFFFA8010 ) /* (TDES) Interrupt Enable Register */
2473 #define AT91C_TDES_ISR ( ( AT91_REG * ) 0xFFFA801C ) /* (TDES) Interrupt Status Register */
2474 #define AT91C_TDES_IDATAxR ( ( AT91_REG * ) 0xFFFA8040 ) /* (TDES) Input Data x Register */
2475 #define AT91C_TDES_KEY1WxR ( ( AT91_REG * ) 0xFFFA8020 ) /* (TDES) Key 1 Word x Register */
2477 /* ***************************************************************************** */
2478 /* PIO DEFINITIONS FOR AT91SAM7X256 */
2479 /* ***************************************************************************** */
2480 #define AT91C_PIO_PA0 ( ( unsigned int ) 1 << 0 ) /* Pin Controlled by PA0 */
2481 #define AT91C_PA0_RXD0 ( ( unsigned int ) AT91C_PIO_PA0 ) /* USART 0 Receive Data */
2482 #define AT91C_PIO_PA1 ( ( unsigned int ) 1 << 1 ) /* Pin Controlled by PA1 */
2483 #define AT91C_PA1_TXD0 ( ( unsigned int ) AT91C_PIO_PA1 ) /* USART 0 Transmit Data */
2484 #define AT91C_PIO_PA10 ( ( unsigned int ) 1 << 10 ) /* Pin Controlled by PA10 */
2485 #define AT91C_PA10_TWD ( ( unsigned int ) AT91C_PIO_PA10 ) /* TWI Two-wire Serial Data */
2486 #define AT91C_PIO_PA11 ( ( unsigned int ) 1 << 11 ) /* Pin Controlled by PA11 */
2487 #define AT91C_PA11_TWCK ( ( unsigned int ) AT91C_PIO_PA11 ) /* TWI Two-wire Serial Clock */
2488 #define AT91C_PIO_PA12 ( ( unsigned int ) 1 << 12 ) /* Pin Controlled by PA12 */
2489 #define AT91C_PA12_NPCS00 ( ( unsigned int ) AT91C_PIO_PA12 ) /* SPI 0 Peripheral Chip Select 0 */
2490 #define AT91C_PIO_PA13 ( ( unsigned int ) 1 << 13 ) /* Pin Controlled by PA13 */
2491 #define AT91C_PA13_NPCS01 ( ( unsigned int ) AT91C_PIO_PA13 ) /* SPI 0 Peripheral Chip Select 1 */
2492 #define AT91C_PA13_PCK1 ( ( unsigned int ) AT91C_PIO_PA13 ) /* PMC Programmable Clock Output 1 */
2493 #define AT91C_PIO_PA14 ( ( unsigned int ) 1 << 14 ) /* Pin Controlled by PA14 */
2494 #define AT91C_PA14_NPCS02 ( ( unsigned int ) AT91C_PIO_PA14 ) /* SPI 0 Peripheral Chip Select 2 */
2495 #define AT91C_PA14_IRQ1 ( ( unsigned int ) AT91C_PIO_PA14 ) /* External Interrupt 1 */
2496 #define AT91C_PIO_PA15 ( ( unsigned int ) 1 << 15 ) /* Pin Controlled by PA15 */
2497 #define AT91C_PA15_NPCS03 ( ( unsigned int ) AT91C_PIO_PA15 ) /* SPI 0 Peripheral Chip Select 3 */
2498 #define AT91C_PA15_TCLK2 ( ( unsigned int ) AT91C_PIO_PA15 ) /* Timer Counter 2 external clock input */
2499 #define AT91C_PIO_PA16 ( ( unsigned int ) 1 << 16 ) /* Pin Controlled by PA16 */
2500 #define AT91C_PA16_MISO0 ( ( unsigned int ) AT91C_PIO_PA16 ) /* SPI 0 Master In Slave */
2501 #define AT91C_PIO_PA17 ( ( unsigned int ) 1 << 17 ) /* Pin Controlled by PA17 */
2502 #define AT91C_PA17_MOSI0 ( ( unsigned int ) AT91C_PIO_PA17 ) /* SPI 0 Master Out Slave */
2503 #define AT91C_PIO_PA18 ( ( unsigned int ) 1 << 18 ) /* Pin Controlled by PA18 */
2504 #define AT91C_PA18_SPCK0 ( ( unsigned int ) AT91C_PIO_PA18 ) /* SPI 0 Serial Clock */
2505 #define AT91C_PIO_PA19 ( ( unsigned int ) 1 << 19 ) /* Pin Controlled by PA19 */
2506 #define AT91C_PA19_CANRX ( ( unsigned int ) AT91C_PIO_PA19 ) /* CAN Receive */
2507 #define AT91C_PIO_PA2 ( ( unsigned int ) 1 << 2 ) /* Pin Controlled by PA2 */
2508 #define AT91C_PA2_SCK0 ( ( unsigned int ) AT91C_PIO_PA2 ) /* USART 0 Serial Clock */
2509 #define AT91C_PA2_NPCS11 ( ( unsigned int ) AT91C_PIO_PA2 ) /* SPI 1 Peripheral Chip Select 1 */
2510 #define AT91C_PIO_PA20 ( ( unsigned int ) 1 << 20 ) /* Pin Controlled by PA20 */
2511 #define AT91C_PA20_CANTX ( ( unsigned int ) AT91C_PIO_PA20 ) /* CAN Transmit */
2512 #define AT91C_PIO_PA21 ( ( unsigned int ) 1 << 21 ) /* Pin Controlled by PA21 */
2513 #define AT91C_PA21_TF ( ( unsigned int ) AT91C_PIO_PA21 ) /* SSC Transmit Frame Sync */
2514 #define AT91C_PA21_NPCS10 ( ( unsigned int ) AT91C_PIO_PA21 ) /* SPI 1 Peripheral Chip Select 0 */
2515 #define AT91C_PIO_PA22 ( ( unsigned int ) 1 << 22 ) /* Pin Controlled by PA22 */
2516 #define AT91C_PA22_TK ( ( unsigned int ) AT91C_PIO_PA22 ) /* SSC Transmit Clock */
2517 #define AT91C_PA22_SPCK1 ( ( unsigned int ) AT91C_PIO_PA22 ) /* SPI 1 Serial Clock */
2518 #define AT91C_PIO_PA23 ( ( unsigned int ) 1 << 23 ) /* Pin Controlled by PA23 */
2519 #define AT91C_PA23_TD ( ( unsigned int ) AT91C_PIO_PA23 ) /* SSC Transmit data */
2520 #define AT91C_PA23_MOSI1 ( ( unsigned int ) AT91C_PIO_PA23 ) /* SPI 1 Master Out Slave */
2521 #define AT91C_PIO_PA24 ( ( unsigned int ) 1 << 24 ) /* Pin Controlled by PA24 */
2522 #define AT91C_PA24_RD ( ( unsigned int ) AT91C_PIO_PA24 ) /* SSC Receive Data */
2523 #define AT91C_PA24_MISO1 ( ( unsigned int ) AT91C_PIO_PA24 ) /* SPI 1 Master In Slave */
2524 #define AT91C_PIO_PA25 ( ( unsigned int ) 1 << 25 ) /* Pin Controlled by PA25 */
2525 #define AT91C_PA25_RK ( ( unsigned int ) AT91C_PIO_PA25 ) /* SSC Receive Clock */
2526 #define AT91C_PA25_NPCS11 ( ( unsigned int ) AT91C_PIO_PA25 ) /* SPI 1 Peripheral Chip Select 1 */
2527 #define AT91C_PIO_PA26 ( ( unsigned int ) 1 << 26 ) /* Pin Controlled by PA26 */
2528 #define AT91C_PA26_RF ( ( unsigned int ) AT91C_PIO_PA26 ) /* SSC Receive Frame Sync */
2529 #define AT91C_PA26_NPCS12 ( ( unsigned int ) AT91C_PIO_PA26 ) /* SPI 1 Peripheral Chip Select 2 */
2530 #define AT91C_PIO_PA27 ( ( unsigned int ) 1 << 27 ) /* Pin Controlled by PA27 */
2531 #define AT91C_PA27_DRXD ( ( unsigned int ) AT91C_PIO_PA27 ) /* DBGU Debug Receive Data */
2532 #define AT91C_PA27_PCK3 ( ( unsigned int ) AT91C_PIO_PA27 ) /* PMC Programmable Clock Output 3 */
2533 #define AT91C_PIO_PA28 ( ( unsigned int ) 1 << 28 ) /* Pin Controlled by PA28 */
2534 #define AT91C_PA28_DTXD ( ( unsigned int ) AT91C_PIO_PA28 ) /* DBGU Debug Transmit Data */
2535 #define AT91C_PIO_PA29 ( ( unsigned int ) 1 << 29 ) /* Pin Controlled by PA29 */
2536 #define AT91C_PA29_FIQ ( ( unsigned int ) AT91C_PIO_PA29 ) /* AIC Fast Interrupt Input */
2537 #define AT91C_PA29_NPCS13 ( ( unsigned int ) AT91C_PIO_PA29 ) /* SPI 1 Peripheral Chip Select 3 */
2538 #define AT91C_PIO_PA3 ( ( unsigned int ) 1 << 3 ) /* Pin Controlled by PA3 */
2539 #define AT91C_PA3_RTS0 ( ( unsigned int ) AT91C_PIO_PA3 ) /* USART 0 Ready To Send */
2540 #define AT91C_PA3_NPCS12 ( ( unsigned int ) AT91C_PIO_PA3 ) /* SPI 1 Peripheral Chip Select 2 */
2541 #define AT91C_PIO_PA30 ( ( unsigned int ) 1 << 30 ) /* Pin Controlled by PA30 */
2542 #define AT91C_PA30_IRQ0 ( ( unsigned int ) AT91C_PIO_PA30 ) /* External Interrupt 0 */
2543 #define AT91C_PA30_PCK2 ( ( unsigned int ) AT91C_PIO_PA30 ) /* PMC Programmable Clock Output 2 */
2544 #define AT91C_PIO_PA4 ( ( unsigned int ) 1 << 4 ) /* Pin Controlled by PA4 */
2545 #define AT91C_PA4_CTS0 ( ( unsigned int ) AT91C_PIO_PA4 ) /* USART 0 Clear To Send */
2546 #define AT91C_PA4_NPCS13 ( ( unsigned int ) AT91C_PIO_PA4 ) /* SPI 1 Peripheral Chip Select 3 */
2547 #define AT91C_PIO_PA5 ( ( unsigned int ) 1 << 5 ) /* Pin Controlled by PA5 */
2548 #define AT91C_PA5_RXD1 ( ( unsigned int ) AT91C_PIO_PA5 ) /* USART 1 Receive Data */
2549 #define AT91C_PIO_PA6 ( ( unsigned int ) 1 << 6 ) /* Pin Controlled by PA6 */
2550 #define AT91C_PA6_TXD1 ( ( unsigned int ) AT91C_PIO_PA6 ) /* USART 1 Transmit Data */
2551 #define AT91C_PIO_PA7 ( ( unsigned int ) 1 << 7 ) /* Pin Controlled by PA7 */
2552 #define AT91C_PA7_SCK1 ( ( unsigned int ) AT91C_PIO_PA7 ) /* USART 1 Serial Clock */
2553 #define AT91C_PA7_NPCS01 ( ( unsigned int ) AT91C_PIO_PA7 ) /* SPI 0 Peripheral Chip Select 1 */
2554 #define AT91C_PIO_PA8 ( ( unsigned int ) 1 << 8 ) /* Pin Controlled by PA8 */
2555 #define AT91C_PA8_RTS1 ( ( unsigned int ) AT91C_PIO_PA8 ) /* USART 1 Ready To Send */
2556 #define AT91C_PA8_NPCS02 ( ( unsigned int ) AT91C_PIO_PA8 ) /* SPI 0 Peripheral Chip Select 2 */
2557 #define AT91C_PIO_PA9 ( ( unsigned int ) 1 << 9 ) /* Pin Controlled by PA9 */
2558 #define AT91C_PA9_CTS1 ( ( unsigned int ) AT91C_PIO_PA9 ) /* USART 1 Clear To Send */
2559 #define AT91C_PA9_NPCS03 ( ( unsigned int ) AT91C_PIO_PA9 ) /* SPI 0 Peripheral Chip Select 3 */
2560 #define AT91C_PIO_PB0 ( ( unsigned int ) 1 << 0 ) /* Pin Controlled by PB0 */
2561 #define AT91C_PB0_ETXCK_EREFCK ( ( unsigned int ) AT91C_PIO_PB0 ) /* Ethernet MAC Transmit Clock/Reference Clock */
2562 #define AT91C_PB0_PCK0 ( ( unsigned int ) AT91C_PIO_PB0 ) /* PMC Programmable Clock Output 0 */
2563 #define AT91C_PIO_PB1 ( ( unsigned int ) 1 << 1 ) /* Pin Controlled by PB1 */
2564 #define AT91C_PB1_ETXEN ( ( unsigned int ) AT91C_PIO_PB1 ) /* Ethernet MAC Transmit Enable */
2565 #define AT91C_PIO_PB10 ( ( unsigned int ) 1 << 10 ) /* Pin Controlled by PB10 */
2566 #define AT91C_PB10_ETX2 ( ( unsigned int ) AT91C_PIO_PB10 ) /* Ethernet MAC Transmit Data 2 */
2567 #define AT91C_PB10_NPCS11 ( ( unsigned int ) AT91C_PIO_PB10 ) /* SPI 1 Peripheral Chip Select 1 */
2568 #define AT91C_PIO_PB11 ( ( unsigned int ) 1 << 11 ) /* Pin Controlled by PB11 */
2569 #define AT91C_PB11_ETX3 ( ( unsigned int ) AT91C_PIO_PB11 ) /* Ethernet MAC Transmit Data 3 */
2570 #define AT91C_PB11_NPCS12 ( ( unsigned int ) AT91C_PIO_PB11 ) /* SPI 1 Peripheral Chip Select 2 */
2571 #define AT91C_PIO_PB12 ( ( unsigned int ) 1 << 12 ) /* Pin Controlled by PB12 */
2572 #define AT91C_PB12_ETXER ( ( unsigned int ) AT91C_PIO_PB12 ) /* Ethernet MAC Transmit Coding Error */
2573 #define AT91C_PB12_TCLK0 ( ( unsigned int ) AT91C_PIO_PB12 ) /* Timer Counter 0 external clock input */
2574 #define AT91C_PIO_PB13 ( ( unsigned int ) 1 << 13 ) /* Pin Controlled by PB13 */
2575 #define AT91C_PB13_ERX2 ( ( unsigned int ) AT91C_PIO_PB13 ) /* Ethernet MAC Receive Data 2 */
2576 #define AT91C_PB13_NPCS01 ( ( unsigned int ) AT91C_PIO_PB13 ) /* SPI 0 Peripheral Chip Select 1 */
2577 #define AT91C_PIO_PB14 ( ( unsigned int ) 1 << 14 ) /* Pin Controlled by PB14 */
2578 #define AT91C_PB14_ERX3 ( ( unsigned int ) AT91C_PIO_PB14 ) /* Ethernet MAC Receive Data 3 */
2579 #define AT91C_PB14_NPCS02 ( ( unsigned int ) AT91C_PIO_PB14 ) /* SPI 0 Peripheral Chip Select 2 */
2580 #define AT91C_PIO_PB15 ( ( unsigned int ) 1 << 15 ) /* Pin Controlled by PB15 */
2581 #define AT91C_PB15_ERXDV ( ( unsigned int ) AT91C_PIO_PB15 ) /* Ethernet MAC Receive Data Valid */
2582 #define AT91C_PIO_PB16 ( ( unsigned int ) 1 << 16 ) /* Pin Controlled by PB16 */
2583 #define AT91C_PB16_ECOL ( ( unsigned int ) AT91C_PIO_PB16 ) /* Ethernet MAC Collision Detected */
2584 #define AT91C_PB16_NPCS13 ( ( unsigned int ) AT91C_PIO_PB16 ) /* SPI 1 Peripheral Chip Select 3 */
2585 #define AT91C_PIO_PB17 ( ( unsigned int ) 1 << 17 ) /* Pin Controlled by PB17 */
2586 #define AT91C_PB17_ERXCK ( ( unsigned int ) AT91C_PIO_PB17 ) /* Ethernet MAC Receive Clock */
2587 #define AT91C_PB17_NPCS03 ( ( unsigned int ) AT91C_PIO_PB17 ) /* SPI 0 Peripheral Chip Select 3 */
2588 #define AT91C_PIO_PB18 ( ( unsigned int ) 1 << 18 ) /* Pin Controlled by PB18 */
2589 #define AT91C_PB18_EF100 ( ( unsigned int ) AT91C_PIO_PB18 ) /* Ethernet MAC Force 100 Mbits/sec */
2590 #define AT91C_PB18_ADTRG ( ( unsigned int ) AT91C_PIO_PB18 ) /* ADC External Trigger */
2591 #define AT91C_PIO_PB19 ( ( unsigned int ) 1 << 19 ) /* Pin Controlled by PB19 */
2592 #define AT91C_PB19_PWM0 ( ( unsigned int ) AT91C_PIO_PB19 ) /* PWM Channel 0 */
2593 #define AT91C_PB19_TCLK1 ( ( unsigned int ) AT91C_PIO_PB19 ) /* Timer Counter 1 external clock input */
2594 #define AT91C_PIO_PB2 ( ( unsigned int ) 1 << 2 ) /* Pin Controlled by PB2 */
2595 #define AT91C_PB2_ETX0 ( ( unsigned int ) AT91C_PIO_PB2 ) /* Ethernet MAC Transmit Data 0 */
2596 #define AT91C_PIO_PB20 ( ( unsigned int ) 1 << 20 ) /* Pin Controlled by PB20 */
2597 #define AT91C_PB20_PWM1 ( ( unsigned int ) AT91C_PIO_PB20 ) /* PWM Channel 1 */
2598 #define AT91C_PB20_PCK0 ( ( unsigned int ) AT91C_PIO_PB20 ) /* PMC Programmable Clock Output 0 */
2599 #define AT91C_PIO_PB21 ( ( unsigned int ) 1 << 21 ) /* Pin Controlled by PB21 */
2600 #define AT91C_PB21_PWM2 ( ( unsigned int ) AT91C_PIO_PB21 ) /* PWM Channel 2 */
2601 #define AT91C_PB21_PCK1 ( ( unsigned int ) AT91C_PIO_PB21 ) /* PMC Programmable Clock Output 1 */
2602 #define AT91C_PIO_PB22 ( ( unsigned int ) 1 << 22 ) /* Pin Controlled by PB22 */
2603 #define AT91C_PB22_PWM3 ( ( unsigned int ) AT91C_PIO_PB22 ) /* PWM Channel 3 */
2604 #define AT91C_PB22_PCK2 ( ( unsigned int ) AT91C_PIO_PB22 ) /* PMC Programmable Clock Output 2 */
2605 #define AT91C_PIO_PB23 ( ( unsigned int ) 1 << 23 ) /* Pin Controlled by PB23 */
2606 #define AT91C_PB23_TIOA0 ( ( unsigned int ) AT91C_PIO_PB23 ) /* Timer Counter 0 Multipurpose Timer I/O Pin A */
2607 #define AT91C_PB23_DCD1 ( ( unsigned int ) AT91C_PIO_PB23 ) /* USART 1 Data Carrier Detect */
2608 #define AT91C_PIO_PB24 ( ( unsigned int ) 1 << 24 ) /* Pin Controlled by PB24 */
2609 #define AT91C_PB24_TIOB0 ( ( unsigned int ) AT91C_PIO_PB24 ) /* Timer Counter 0 Multipurpose Timer I/O Pin B */
2610 #define AT91C_PB24_DSR1 ( ( unsigned int ) AT91C_PIO_PB24 ) /* USART 1 Data Set ready */
2611 #define AT91C_PIO_PB25 ( ( unsigned int ) 1 << 25 ) /* Pin Controlled by PB25 */
2612 #define AT91C_PB25_TIOA1 ( ( unsigned int ) AT91C_PIO_PB25 ) /* Timer Counter 1 Multipurpose Timer I/O Pin A */
2613 #define AT91C_PB25_DTR1 ( ( unsigned int ) AT91C_PIO_PB25 ) /* USART 1 Data Terminal ready */
2614 #define AT91C_PIO_PB26 ( ( unsigned int ) 1 << 26 ) /* Pin Controlled by PB26 */
2615 #define AT91C_PB26_TIOB1 ( ( unsigned int ) AT91C_PIO_PB26 ) /* Timer Counter 1 Multipurpose Timer I/O Pin B */
2616 #define AT91C_PB26_RI1 ( ( unsigned int ) AT91C_PIO_PB26 ) /* USART 1 Ring Indicator */
2617 #define AT91C_PIO_PB27 ( ( unsigned int ) 1 << 27 ) /* Pin Controlled by PB27 */
2618 #define AT91C_PB27_TIOA2 ( ( unsigned int ) AT91C_PIO_PB27 ) /* Timer Counter 2 Multipurpose Timer I/O Pin A */
2619 #define AT91C_PB27_PWM0 ( ( unsigned int ) AT91C_PIO_PB27 ) /* PWM Channel 0 */
2620 #define AT91C_PIO_PB28 ( ( unsigned int ) 1 << 28 ) /* Pin Controlled by PB28 */
2621 #define AT91C_PB28_TIOB2 ( ( unsigned int ) AT91C_PIO_PB28 ) /* Timer Counter 2 Multipurpose Timer I/O Pin B */
2622 #define AT91C_PB28_PWM1 ( ( unsigned int ) AT91C_PIO_PB28 ) /* PWM Channel 1 */
2623 #define AT91C_PIO_PB29 ( ( unsigned int ) 1 << 29 ) /* Pin Controlled by PB29 */
2624 #define AT91C_PB29_PCK1 ( ( unsigned int ) AT91C_PIO_PB29 ) /* PMC Programmable Clock Output 1 */
2625 #define AT91C_PB29_PWM2 ( ( unsigned int ) AT91C_PIO_PB29 ) /* PWM Channel 2 */
2626 #define AT91C_PIO_PB3 ( ( unsigned int ) 1 << 3 ) /* Pin Controlled by PB3 */
2627 #define AT91C_PB3_ETX1 ( ( unsigned int ) AT91C_PIO_PB3 ) /* Ethernet MAC Transmit Data 1 */
2628 #define AT91C_PIO_PB30 ( ( unsigned int ) 1 << 30 ) /* Pin Controlled by PB30 */
2629 #define AT91C_PB30_PCK2 ( ( unsigned int ) AT91C_PIO_PB30 ) /* PMC Programmable Clock Output 2 */
2630 #define AT91C_PB30_PWM3 ( ( unsigned int ) AT91C_PIO_PB30 ) /* PWM Channel 3 */
2631 #define AT91C_PIO_PB4 ( ( unsigned int ) 1 << 4 ) /* Pin Controlled by PB4 */
2632 #define AT91C_PB4_ECRS_ECRSDV ( ( unsigned int ) AT91C_PIO_PB4 ) /* Ethernet MAC Carrier Sense/Carrier Sense and Data Valid */
2633 #define AT91C_PIO_PB5 ( ( unsigned int ) 1 << 5 ) /* Pin Controlled by PB5 */
2634 #define AT91C_PB5_ERX0 ( ( unsigned int ) AT91C_PIO_PB5 ) /* Ethernet MAC Receive Data 0 */
2635 #define AT91C_PIO_PB6 ( ( unsigned int ) 1 << 6 ) /* Pin Controlled by PB6 */
2636 #define AT91C_PB6_ERX1 ( ( unsigned int ) AT91C_PIO_PB6 ) /* Ethernet MAC Receive Data 1 */
2637 #define AT91C_PIO_PB7 ( ( unsigned int ) 1 << 7 ) /* Pin Controlled by PB7 */
2638 #define AT91C_PB7_ERXER ( ( unsigned int ) AT91C_PIO_PB7 ) /* Ethernet MAC Receive Error */
2639 #define AT91C_PIO_PB8 ( ( unsigned int ) 1 << 8 ) /* Pin Controlled by PB8 */
2640 #define AT91C_PB8_EMDC ( ( unsigned int ) AT91C_PIO_PB8 ) /* Ethernet MAC Management Data Clock */
2641 #define AT91C_PIO_PB9 ( ( unsigned int ) 1 << 9 ) /* Pin Controlled by PB9 */
2642 #define AT91C_PB9_EMDIO ( ( unsigned int ) AT91C_PIO_PB9 ) /* Ethernet MAC Management Data Input/Output */
2644 /* ***************************************************************************** */
2645 /* PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256 */
2646 /* ***************************************************************************** */
2647 #define AT91C_ID_FIQ ( ( unsigned int ) 0 ) /* Advanced Interrupt Controller (FIQ) */
2648 #define AT91C_ID_SYS ( ( unsigned int ) 1 ) /* System Peripheral */
2649 #define AT91C_ID_PIOA ( ( unsigned int ) 2 ) /* Parallel IO Controller A */
2650 #define AT91C_ID_PIOB ( ( unsigned int ) 3 ) /* Parallel IO Controller B */
2651 #define AT91C_ID_SPI0 ( ( unsigned int ) 4 ) /* Serial Peripheral Interface 0 */
2652 #define AT91C_ID_SPI1 ( ( unsigned int ) 5 ) /* Serial Peripheral Interface 1 */
2653 #define AT91C_ID_US0 ( ( unsigned int ) 6 ) /* USART 0 */
2654 #define AT91C_ID_US1 ( ( unsigned int ) 7 ) /* USART 1 */
2655 #define AT91C_ID_SSC ( ( unsigned int ) 8 ) /* Serial Synchronous Controller */
2656 #define AT91C_ID_TWI ( ( unsigned int ) 9 ) /* Two-Wire Interface */
2657 #define AT91C_ID_PWMC ( ( unsigned int ) 10 ) /* PWM Controller */
2658 #define AT91C_ID_UDP ( ( unsigned int ) 11 ) /* USB Device Port */
2659 #define AT91C_ID_TC0 ( ( unsigned int ) 12 ) /* Timer Counter 0 */
2660 #define AT91C_ID_TC1 ( ( unsigned int ) 13 ) /* Timer Counter 1 */
2661 #define AT91C_ID_TC2 ( ( unsigned int ) 14 ) /* Timer Counter 2 */
2662 #define AT91C_ID_CAN ( ( unsigned int ) 15 ) /* Control Area Network Controller */
2663 #define AT91C_ID_EMAC ( ( unsigned int ) 16 ) /* Ethernet MAC */
2664 #define AT91C_ID_ADC ( ( unsigned int ) 17 ) /* Analog-to-Digital Converter */
2665 #define AT91C_ID_AES ( ( unsigned int ) 18 ) /* Advanced Encryption Standard 128-bit */
2666 #define AT91C_ID_TDES ( ( unsigned int ) 19 ) /* Triple Data Encryption Standard */
2667 #define AT91C_ID_20_Reserved ( ( unsigned int ) 20 ) /* Reserved */
2668 #define AT91C_ID_21_Reserved ( ( unsigned int ) 21 ) /* Reserved */
2669 #define AT91C_ID_22_Reserved ( ( unsigned int ) 22 ) /* Reserved */
2670 #define AT91C_ID_23_Reserved ( ( unsigned int ) 23 ) /* Reserved */
2671 #define AT91C_ID_24_Reserved ( ( unsigned int ) 24 ) /* Reserved */
2672 #define AT91C_ID_25_Reserved ( ( unsigned int ) 25 ) /* Reserved */
2673 #define AT91C_ID_26_Reserved ( ( unsigned int ) 26 ) /* Reserved */
2674 #define AT91C_ID_27_Reserved ( ( unsigned int ) 27 ) /* Reserved */
2675 #define AT91C_ID_28_Reserved ( ( unsigned int ) 28 ) /* Reserved */
2676 #define AT91C_ID_29_Reserved ( ( unsigned int ) 29 ) /* Reserved */
2677 #define AT91C_ID_IRQ0 ( ( unsigned int ) 30 ) /* Advanced Interrupt Controller (IRQ0) */
2678 #define AT91C_ID_IRQ1 ( ( unsigned int ) 31 ) /* Advanced Interrupt Controller (IRQ1) */
2680 /* ***************************************************************************** */
2681 /* BASE ADDRESS DEFINITIONS FOR AT91SAM7X256 */
2682 /* ***************************************************************************** */
2683 #define AT91C_BASE_SYS ( ( AT91PS_SYS ) 0xFFFFF000 ) /* (SYS) Base Address */
2684 #define AT91C_BASE_AIC ( ( AT91PS_AIC ) 0xFFFFF000 ) /* (AIC) Base Address */
2685 #define AT91C_BASE_PDC_DBGU ( ( AT91PS_PDC ) 0xFFFFF300 ) /* (PDC_DBGU) Base Address */
2686 #define AT91C_BASE_DBGU ( ( AT91PS_DBGU ) 0xFFFFF200 ) /* (DBGU) Base Address */
2687 #define AT91C_BASE_PIOA ( ( AT91PS_PIO ) 0xFFFFF400 ) /* (PIOA) Base Address */
2688 #define AT91C_BASE_PIOB ( ( AT91PS_PIO ) 0xFFFFF600 ) /* (PIOB) Base Address */
2689 #define AT91C_BASE_CKGR ( ( AT91PS_CKGR ) 0xFFFFFC20 ) /* (CKGR) Base Address */
2690 #define AT91C_BASE_PMC ( ( AT91PS_PMC ) 0xFFFFFC00 ) /* (PMC) Base Address */
2691 #define AT91C_BASE_RSTC ( ( AT91PS_RSTC ) 0xFFFFFD00 ) /* (RSTC) Base Address */
2692 #define AT91C_BASE_RTTC ( ( AT91PS_RTTC ) 0xFFFFFD20 ) /* (RTTC) Base Address */
2693 #define AT91C_BASE_PITC ( ( AT91PS_PITC ) 0xFFFFFD30 ) /* (PITC) Base Address */
2694 #define AT91C_BASE_WDTC ( ( AT91PS_WDTC ) 0xFFFFFD40 ) /* (WDTC) Base Address */
2695 #define AT91C_BASE_VREG ( ( AT91PS_VREG ) 0xFFFFFD60 ) /* (VREG) Base Address */
2696 #define AT91C_BASE_MC ( ( AT91PS_MC ) 0xFFFFFF00 ) /* (MC) Base Address */
2697 #define AT91C_BASE_PDC_SPI1 ( ( AT91PS_PDC ) 0xFFFE4100 ) /* (PDC_SPI1) Base Address */
2698 #define AT91C_BASE_SPI1 ( ( AT91PS_SPI ) 0xFFFE4000 ) /* (SPI1) Base Address */
2699 #define AT91C_BASE_PDC_SPI0 ( ( AT91PS_PDC ) 0xFFFE0100 ) /* (PDC_SPI0) Base Address */
2700 #define AT91C_BASE_SPI0 ( ( AT91PS_SPI ) 0xFFFE0000 ) /* (SPI0) Base Address */
2701 #define AT91C_BASE_PDC_US1 ( ( AT91PS_PDC ) 0xFFFC4100 ) /* (PDC_US1) Base Address */
2702 #define AT91C_BASE_US1 ( ( AT91PS_USART ) 0xFFFC4000 ) /* (US1) Base Address */
2703 #define AT91C_BASE_PDC_US0 ( ( AT91PS_PDC ) 0xFFFC0100 ) /* (PDC_US0) Base Address */
2704 #define AT91C_BASE_US0 ( ( AT91PS_USART ) 0xFFFC0000 ) /* (US0) Base Address */
2705 #define AT91C_BASE_PDC_SSC ( ( AT91PS_PDC ) 0xFFFD4100 ) /* (PDC_SSC) Base Address */
2706 #define AT91C_BASE_SSC ( ( AT91PS_SSC ) 0xFFFD4000 ) /* (SSC) Base Address */
2707 #define AT91C_BASE_TWI ( ( AT91PS_TWI ) 0xFFFB8000 ) /* (TWI) Base Address */
2708 #define AT91C_BASE_PWMC_CH3 ( ( AT91PS_PWMC_CH ) 0xFFFCC260 ) /* (PWMC_CH3) Base Address */
2709 #define AT91C_BASE_PWMC_CH2 ( ( AT91PS_PWMC_CH ) 0xFFFCC240 ) /* (PWMC_CH2) Base Address */
2710 #define AT91C_BASE_PWMC_CH1 ( ( AT91PS_PWMC_CH ) 0xFFFCC220 ) /* (PWMC_CH1) Base Address */
2711 #define AT91C_BASE_PWMC_CH0 ( ( AT91PS_PWMC_CH ) 0xFFFCC200 ) /* (PWMC_CH0) Base Address */
2712 #define AT91C_BASE_PWMC ( ( AT91PS_PWMC ) 0xFFFCC000 ) /* (PWMC) Base Address */
2713 #define AT91C_BASE_UDP ( ( AT91PS_UDP ) 0xFFFB0000 ) /* (UDP) Base Address */
2714 #define AT91C_BASE_TC0 ( ( AT91PS_TC ) 0xFFFA0000 ) /* (TC0) Base Address */
2715 #define AT91C_BASE_TC1 ( ( AT91PS_TC ) 0xFFFA0040 ) /* (TC1) Base Address */
2716 #define AT91C_BASE_TC2 ( ( AT91PS_TC ) 0xFFFA0080 ) /* (TC2) Base Address */
2717 #define AT91C_BASE_TCB ( ( AT91PS_TCB ) 0xFFFA0000 ) /* (TCB) Base Address */
2718 #define AT91C_BASE_CAN_MB0 ( ( AT91PS_CAN_MB ) 0xFFFD0200 ) /* (CAN_MB0) Base Address */
2719 #define AT91C_BASE_CAN_MB1 ( ( AT91PS_CAN_MB ) 0xFFFD0220 ) /* (CAN_MB1) Base Address */
2720 #define AT91C_BASE_CAN_MB2 ( ( AT91PS_CAN_MB ) 0xFFFD0240 ) /* (CAN_MB2) Base Address */
2721 #define AT91C_BASE_CAN_MB3 ( ( AT91PS_CAN_MB ) 0xFFFD0260 ) /* (CAN_MB3) Base Address */
2722 #define AT91C_BASE_CAN_MB4 ( ( AT91PS_CAN_MB ) 0xFFFD0280 ) /* (CAN_MB4) Base Address */
2723 #define AT91C_BASE_CAN_MB5 ( ( AT91PS_CAN_MB ) 0xFFFD02A0 ) /* (CAN_MB5) Base Address */
2724 #define AT91C_BASE_CAN_MB6 ( ( AT91PS_CAN_MB ) 0xFFFD02C0 ) /* (CAN_MB6) Base Address */
2725 #define AT91C_BASE_CAN_MB7 ( ( AT91PS_CAN_MB ) 0xFFFD02E0 ) /* (CAN_MB7) Base Address */
2726 #define AT91C_BASE_CAN ( ( AT91PS_CAN ) 0xFFFD0000 ) /* (CAN) Base Address */
2727 #define AT91C_BASE_EMAC ( ( AT91PS_EMAC ) 0xFFFDC000 ) /* (EMAC) Base Address */
2728 #define AT91C_BASE_PDC_ADC ( ( AT91PS_PDC ) 0xFFFD8100 ) /* (PDC_ADC) Base Address */
2729 #define AT91C_BASE_ADC ( ( AT91PS_ADC ) 0xFFFD8000 ) /* (ADC) Base Address */
2730 #define AT91C_BASE_PDC_AES ( ( AT91PS_PDC ) 0xFFFA4100 ) /* (PDC_AES) Base Address */
2731 #define AT91C_BASE_AES ( ( AT91PS_AES ) 0xFFFA4000 ) /* (AES) Base Address */
2732 #define AT91C_BASE_PDC_TDES ( ( AT91PS_PDC ) 0xFFFA8100 ) /* (PDC_TDES) Base Address */
2733 #define AT91C_BASE_TDES ( ( AT91PS_TDES ) 0xFFFA8000 ) /* (TDES) Base Address */
2735 /* ***************************************************************************** */
2736 /* MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256 */
2737 /* ***************************************************************************** */
2738 #define AT91C_ISRAM ( ( char * ) 0x00200000 ) /* Internal SRAM base address */
2739 #define AT91C_ISRAM_SIZE ( ( unsigned int ) 0x00010000 ) /* Internal SRAM size in byte (64 Kbyte) */
2740 #define AT91C_IFLASH ( ( char * ) 0x00100000 ) /* Internal ROM base address */
2741 #define AT91C_IFLASH_SIZE ( ( unsigned int ) 0x00040000 ) /* Internal ROM size in byte (256 Kbyte) */
2745 /* - Hardware register definition */
2747 /* - ***************************************************************************** */
2748 /* - SOFTWARE API DEFINITION FOR System Peripherals */
2749 /* - ***************************************************************************** */
2751 /* - ***************************************************************************** */
2752 /* - SOFTWARE API DEFINITION FOR Advanced Interrupt Controller */
2753 /* - ***************************************************************************** */
2754 /* - -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- */
2756 AT91C_AIC_PRIOR EQU( 0x7 << 0 );
2757 -( AIC ) Priority Level
2758 AT91C_AIC_PRIOR_LOWEST EQU( 0x0 );
2759 -( AIC ) Lowest priority level
2760 AT91C_AIC_PRIOR_HIGHEST EQU( 0x7 );
2761 -( AIC ) Highest priority level
2762 AT91C_AIC_SRCTYPE EQU( 0x3 << 5 );
2763 -( AIC ) Interrupt Source Type
2764 AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL EQU( 0x0 << 5 );
2765 -( AIC ) Internal Sources Code Label High - level Sensitive
2766 AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL EQU( 0x0 << 5 );
2767 -( AIC ) External Sources Code Label Low - level Sensitive
2768 AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE EQU( 0x1 << 5 );
2769 -( AIC ) Internal Sources Code Label Positive Edge triggered
2770 AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE EQU( 0x1 << 5 );
2771 -( AIC ) External Sources Code Label Negative Edge triggered
2772 AT91C_AIC_SRCTYPE_HIGH_LEVEL EQU( 0x2 << 5 );
2773 -( AIC ) Internal Or External Sources Code Label High - level Sensitive
2774 AT91C_AIC_SRCTYPE_POSITIVE_EDGE EQU( 0x3 << 5 );
2775 -( AIC ) Internal Or External Sources Code Label Positive Edge triggered
2776 /* - -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- */
2777 AT91C_AIC_NFIQ EQU( 0x1 << 0 );
2778 -( AIC ) NFIQ Status
2779 AT91C_AIC_NIRQ EQU( 0x1 << 1 );
2780 -( AIC ) NIRQ Status
2781 /* - -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- */
2782 AT91C_AIC_DCR_PROT EQU( 0x1 << 0 );
2783 -( AIC ) Protection Mode
2784 AT91C_AIC_DCR_GMSK EQU( 0x1 << 1 );
2785 -( AIC ) General Mask
2787 /* - ***************************************************************************** */
2788 /* - SOFTWARE API DEFINITION FOR Peripheral DMA Controller */
2789 /* - ***************************************************************************** */
2790 /* - -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- */
2791 AT91C_PDC_RXTEN EQU( 0x1 << 0 );
2792 -( PDC ) Receiver Transfer Enable
2793 AT91C_PDC_RXTDIS EQU( 0x1 << 1 );
2794 -( PDC ) Receiver Transfer Disable
2795 AT91C_PDC_TXTEN EQU( 0x1 << 8 );
2796 -( PDC ) Transmitter Transfer Enable
2797 AT91C_PDC_TXTDIS EQU( 0x1 << 9 );
2798 -( PDC ) Transmitter Transfer Disable
2799 /* - -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- */
2801 /* - ***************************************************************************** */
2802 /* - SOFTWARE API DEFINITION FOR Debug Unit */
2803 /* - ***************************************************************************** */
2804 /* - -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- */
2805 AT91C_US_RSTRX EQU( 0x1 << 2 );
2806 -( DBGU ) Reset Receiver
2807 AT91C_US_RSTTX EQU( 0x1 << 3 );
2808 -( DBGU ) Reset Transmitter
2809 AT91C_US_RXEN EQU( 0x1 << 4 );
2810 -( DBGU ) Receiver Enable
2811 AT91C_US_RXDIS EQU( 0x1 << 5 );
2812 -( DBGU ) Receiver Disable
2813 AT91C_US_TXEN EQU( 0x1 << 6 );
2814 -( DBGU ) Transmitter Enable
2815 AT91C_US_TXDIS EQU( 0x1 << 7 );
2816 -( DBGU ) Transmitter Disable
2817 AT91C_US_RSTSTA EQU( 0x1 << 8 );
2818 -( DBGU ) Reset Status Bits
2819 /* - -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- */
2820 AT91C_US_PAR EQU( 0x7 << 9 );
2821 -( DBGU ) Parity type
2822 AT91C_US_PAR_EVEN EQU( 0x0 << 9 );
2823 -( DBGU ) Even Parity
2824 AT91C_US_PAR_ODD EQU( 0x1 << 9 );
2825 -( DBGU ) Odd Parity
2826 AT91C_US_PAR_SPACE EQU( 0x2 << 9 );
2827 -( DBGU ) Parity forced to 0 ( Space )
2828 AT91C_US_PAR_MARK EQU( 0x3 << 9 );
2829 -( DBGU ) Parity forced to 1 ( Mark )
2830 AT91C_US_PAR_NONE EQU( 0x4 << 9 );
2832 AT91C_US_PAR_MULTI_DROP EQU( 0x6 << 9 );
2833 -( DBGU ) Multi - drop mode
2834 AT91C_US_CHMODE EQU( 0x3 << 14 );
2835 -( DBGU ) Channel Mode
2836 AT91C_US_CHMODE_NORMAL EQU( 0x0 << 14 );
2837 -( DBGU ) Normal Mode: The USART channel operates as an RX / TX USART.
2838 AT91C_US_CHMODE_AUTO EQU( 0x1 << 14 );
2839 -( DBGU ) Automatic Echo: Receiver Data Input is connected to the TXD pin.
2840 AT91C_US_CHMODE_LOCAL EQU( 0x2 << 14 );
2841 -( DBGU ) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
2842 AT91C_US_CHMODE_REMOTE EQU( 0x3 << 14 );
2843 -( DBGU ) Remote Loopback: RXD pin is internally connected to TXD pin.
2844 /* - -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- */
2845 AT91C_US_RXRDY EQU( 0x1 << 0 );
2846 -( DBGU ) RXRDY Interrupt
2847 AT91C_US_TXRDY EQU( 0x1 << 1 );
2848 -( DBGU ) TXRDY Interrupt
2849 AT91C_US_ENDRX EQU( 0x1 << 3 );
2850 -( DBGU ) End of Receive Transfer Interrupt
2851 AT91C_US_ENDTX EQU( 0x1 << 4 );
2852 -( DBGU ) End of Transmit Interrupt
2853 AT91C_US_OVRE EQU( 0x1 << 5 );
2854 -( DBGU ) Overrun Interrupt
2855 AT91C_US_FRAME EQU( 0x1 << 6 );
2856 -( DBGU ) Framing Error Interrupt
2857 AT91C_US_PARE EQU( 0x1 << 7 );
2858 -( DBGU ) Parity Error Interrupt
2859 AT91C_US_TXEMPTY EQU( 0x1 << 9 );
2860 -( DBGU ) TXEMPTY Interrupt
2861 AT91C_US_TXBUFE EQU( 0x1 << 11 );
2862 -( DBGU ) TXBUFE Interrupt
2863 AT91C_US_RXBUFF EQU( 0x1 << 12 );
2864 -( DBGU ) RXBUFF Interrupt
2865 AT91C_US_COMM_TX EQU( 0x1 << 30 );
2866 -( DBGU ) COMM_TX Interrupt
2867 AT91C_US_COMM_RX EQU( 0x1 << 31 );
2868 -( DBGU ) COMM_RX Interrupt
2869 /* - -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- */
2870 /* - -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- */
2871 /* - -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- */
2872 /* - -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- */
2873 AT91C_US_FORCE_NTRST EQU( 0x1 << 0 );
2874 -( DBGU ) Force NTRST in JTAG
2876 /* - ***************************************************************************** */
2877 /* - SOFTWARE API DEFINITION FOR Parallel Input Output Controller */
2878 /* - ***************************************************************************** */
2880 /* - ***************************************************************************** */
2881 /* - SOFTWARE API DEFINITION FOR Clock Generator Controller */
2882 /* - ***************************************************************************** */
2883 /* - -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- */
2884 AT91C_CKGR_MOSCEN EQU( 0x1 << 0 );
2885 -( CKGR ) Main Oscillator Enable
2886 AT91C_CKGR_OSCBYPASS EQU( 0x1 << 1 );
2887 -( CKGR ) Main Oscillator Bypass
2888 AT91C_CKGR_OSCOUNT EQU( 0xFF << 8 );
2889 -( CKGR ) Main Oscillator Start - up Time
2890 /* - -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- */
2891 AT91C_CKGR_MAINF EQU( 0xFFFF << 0 );
2892 -( CKGR ) Main Clock Frequency
2893 AT91C_CKGR_MAINRDY EQU( 0x1 << 16 );
2894 -( CKGR ) Main Clock Ready
2895 /* - -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- */
2896 AT91C_CKGR_DIV EQU( 0xFF << 0 );
2897 -( CKGR ) Divider Selected
2898 AT91C_CKGR_DIV_0 EQU( 0x0 );
2899 -( CKGR ) Divider output is 0
2900 AT91C_CKGR_DIV_BYPASS EQU( 0x1 );
2901 -( CKGR ) Divider is bypassed
2902 AT91C_CKGR_PLLCOUNT EQU( 0x3F << 8 );
2903 -( CKGR ) PLL Counter
2904 AT91C_CKGR_OUT EQU( 0x3 << 14 );
2905 -( CKGR ) PLL Output Frequency Range
2906 AT91C_CKGR_OUT_0 EQU( 0x0 << 14 );
2907 -( CKGR ) Please refer to the PLL datasheet
2908 AT91C_CKGR_OUT_1 EQU( 0x1 << 14 );
2909 -( CKGR ) Please refer to the PLL datasheet
2910 AT91C_CKGR_OUT_2 EQU( 0x2 << 14 );
2911 -( CKGR ) Please refer to the PLL datasheet
2912 AT91C_CKGR_OUT_3 EQU( 0x3 << 14 );
2913 -( CKGR ) Please refer to the PLL datasheet
2914 AT91C_CKGR_MUL EQU( 0x7FF << 16 );
2915 -( CKGR ) PLL Multiplier
2916 AT91C_CKGR_USBDIV EQU( 0x3 << 28 );
2920 AT91C_CKGR_USBDIV_0 EQU( 0x0 << 28 );
2921 -( CKGR ) Divider output is PLL clock output
2922 AT91C_CKGR_USBDIV_1 EQU( 0x1 << 28 );
2923 -( CKGR ) Divider output is PLL clock output divided by 2
2924 AT91C_CKGR_USBDIV_2 EQU( 0x2 << 28 );
2925 -( CKGR ) Divider output is PLL clock output divided by 4
2927 /* - ***************************************************************************** */
2928 /* - SOFTWARE API DEFINITION FOR Power Management Controller */
2929 /* - ***************************************************************************** */
2930 /* - -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- */
2931 AT91C_PMC_PCK EQU( 0x1 << 0 );
2932 -( PMC ) Processor Clock
2933 AT91C_PMC_UDP EQU( 0x1 << 7 );
2934 -( PMC ) USB Device Port Clock
2935 AT91C_PMC_PCK0 EQU( 0x1 << 8 );
2936 -( PMC ) Programmable Clock Output
2937 AT91C_PMC_PCK1 EQU( 0x1 << 9 );
2938 -( PMC ) Programmable Clock Output
2939 AT91C_PMC_PCK2 EQU( 0x1 << 10 );
2940 -( PMC ) Programmable Clock Output
2941 AT91C_PMC_PCK3 EQU( 0x1 << 11 );
2942 -( PMC ) Programmable Clock Output
2943 /* - -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- */
2944 /* - -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- */
2945 /* - -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- */
2946 /* - -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- */
2947 /* - -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- */
2948 /* - -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- */
2949 AT91C_PMC_CSS EQU( 0x3 << 0 );
2950 -( PMC ) Programmable Clock Selection
2951 AT91C_PMC_CSS_SLOW_CLK EQU( 0x0 );
2952 -( PMC ) Slow Clock is selected
2953 AT91C_PMC_CSS_MAIN_CLK EQU( 0x1 );
2954 -( PMC ) Main Clock is selected
2955 AT91C_PMC_CSS_PLL_CLK EQU( 0x3 );
2956 -( PMC ) Clock from PLL is selected
2957 AT91C_PMC_PRES EQU( 0x7 << 2 );
2958 -( PMC ) Programmable Clock Prescaler
2959 AT91C_PMC_PRES_CLK EQU( 0x0 << 2 );
2960 -( PMC ) Selected clock
2961 AT91C_PMC_PRES_CLK_2 EQU( 0x1 << 2 );
2962 -( PMC ) Selected clock divided by 2
2963 AT91C_PMC_PRES_CLK_4 EQU( 0x2 << 2 );
2964 -( PMC ) Selected clock divided by 4
2965 AT91C_PMC_PRES_CLK_8 EQU( 0x3 << 2 );
2966 -( PMC ) Selected clock divided by 8
2967 AT91C_PMC_PRES_CLK_16 EQU( 0x4 << 2 );
2968 -( PMC ) Selected clock divided by 16
2969 AT91C_PMC_PRES_CLK_32 EQU( 0x5 << 2 );
2970 -( PMC ) Selected clock divided by 32
2971 AT91C_PMC_PRES_CLK_64 EQU( 0x6 << 2 );
2972 -( PMC ) Selected clock divided by 64
2973 /* - -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- */
2974 /* - -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- */
2975 AT91C_PMC_MOSCS EQU( 0x1 << 0 );
2976 -( PMC ) MOSC Status / Enable / Disable / Mask
2977 AT91C_PMC_LOCK EQU( 0x1 << 2 );
2978 -( PMC ) PLL Status / Enable / Disable / Mask
2979 AT91C_PMC_MCKRDY EQU( 0x1 << 3 );
2980 -( PMC ) MCK_RDY Status / Enable / Disable / Mask
2981 AT91C_PMC_PCK0RDY EQU( 0x1 << 8 );
2982 -( PMC ) PCK0_RDY Status / Enable / Disable / Mask
2983 AT91C_PMC_PCK1RDY EQU( 0x1 << 9 );
2984 -( PMC ) PCK1_RDY Status / Enable / Disable / Mask
2985 AT91C_PMC_PCK2RDY EQU( 0x1 << 10 );
2986 -( PMC ) PCK2_RDY Status / Enable / Disable / Mask
2987 AT91C_PMC_PCK3RDY EQU( 0x1 << 11 );
2988 -( PMC ) PCK3_RDY Status / Enable / Disable / Mask
2989 /* - -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- */
2990 /* - -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- */
2991 /* - -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- */
2993 /* - ***************************************************************************** */
2994 /* - SOFTWARE API DEFINITION FOR Reset Controller Interface */
2995 /* - ***************************************************************************** */
2996 /* - -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- */
2997 AT91C_RSTC_PROCRST EQU( 0x1 << 0 );
2998 -( RSTC ) Processor Reset
2999 AT91C_RSTC_PERRST EQU( 0x1 << 2 );
3000 -( RSTC ) Peripheral Reset
3001 AT91C_RSTC_EXTRST EQU( 0x1 << 3 );
3002 -( RSTC ) External Reset
3003 AT91C_RSTC_KEY EQU( 0xFF << 24 );
3005 /* - -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- */
3006 AT91C_RSTC_URSTS EQU( 0x1 << 0 );
3007 -( RSTC ) User Reset Status
3008 AT91C_RSTC_BODSTS EQU( 0x1 << 1 );
3009 -( RSTC ) Brownout Detection Status
3010 AT91C_RSTC_RSTTYP EQU( 0x7 << 8 );
3011 -( RSTC ) Reset Type
3012 AT91C_RSTC_RSTTYP_POWERUP EQU( 0x0 << 8 );
3013 -( RSTC ) Power - up Reset.VDDCORE rising.
3014 AT91C_RSTC_RSTTYP_WAKEUP EQU( 0x1 << 8 );
3015 -( RSTC ) WakeUp Reset.VDDCORE rising.
3016 AT91C_RSTC_RSTTYP_WATCHDOG EQU( 0x2 << 8 );
3017 -( RSTC ) Watchdog Reset.Watchdog overflow occurred.
3018 AT91C_RSTC_RSTTYP_SOFTWARE EQU( 0x3 << 8 );
3019 -( RSTC ) Software Reset.Processor reset required by the software.
3020 AT91C_RSTC_RSTTYP_USER EQU( 0x4 << 8 );
3021 -( RSTC ) User Reset.NRST pin detected low.
3022 AT91C_RSTC_RSTTYP_BROWNOUT EQU( 0x5 << 8 );
3023 -( RSTC ) Brownout Reset occurred.
3024 AT91C_RSTC_NRSTL EQU( 0x1 << 16 );
3025 -( RSTC ) NRST pin level
3026 AT91C_RSTC_SRCMP EQU( 0x1 << 17 );
3027 -( RSTC ) Software Reset Command in Progress.
3028 /* - -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- */
3029 AT91C_RSTC_URSTEN EQU( 0x1 << 0 );
3030 -( RSTC ) User Reset Enable
3031 AT91C_RSTC_URSTIEN EQU( 0x1 << 4 );
3032 -( RSTC ) User Reset Interrupt Enable
3033 AT91C_RSTC_ERSTL EQU( 0xF << 8 );
3034 -( RSTC ) User Reset Enable
3035 AT91C_RSTC_BODIEN EQU( 0x1 << 16 );
3036 -( RSTC ) Brownout Detection Interrupt Enable
3038 /* - ***************************************************************************** */
3039 /* - SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface */
3040 /* - ***************************************************************************** */
3041 /* - -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- */
3042 AT91C_RTTC_RTPRES EQU( 0xFFFF << 0 );
3043 -( RTTC ) Real - time Timer Prescaler Value
3044 AT91C_RTTC_ALMIEN EQU( 0x1 << 16 );
3045 -( RTTC ) Alarm Interrupt Enable
3046 AT91C_RTTC_RTTINCIEN EQU( 0x1 << 17 );
3047 -( RTTC ) Real Time Timer Increment Interrupt Enable
3048 AT91C_RTTC_RTTRST EQU( 0x1 << 18 );
3049 -( RTTC ) Real Time Timer Restart
3050 /* - -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- */
3051 AT91C_RTTC_ALMV EQU( 0x0 << 0 );
3052 -( RTTC ) Alarm Value
3053 /* - -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- */
3054 AT91C_RTTC_CRTV EQU( 0x0 << 0 );
3055 -( RTTC ) Current Real - time Value
3056 /* - -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- */
3057 AT91C_RTTC_ALMS EQU( 0x1 << 0 );
3058 -( RTTC ) Real - time Alarm Status
3059 AT91C_RTTC_RTTINC EQU( 0x1 << 1 );
3060 -( RTTC ) Real - time Timer Increment
3062 /* - ***************************************************************************** */
3063 /* - SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface */
3064 /* - ***************************************************************************** */
3065 /* - -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- */
3066 AT91C_PITC_PIV EQU( 0xFFFFF << 0 );
3067 -( PITC ) Periodic Interval Value
3068 AT91C_PITC_PITEN EQU( 0x1 << 24 );
3069 -( PITC ) Periodic Interval Timer Enabled
3070 AT91C_PITC_PITIEN EQU( 0x1 << 25 );
3071 -( PITC ) Periodic Interval Timer Interrupt Enable
3072 /* - -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- */
3073 AT91C_PITC_PITS EQU( 0x1 << 0 );
3074 -( PITC ) Periodic Interval Timer Status
3075 /* - -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- */
3076 AT91C_PITC_CPIV EQU( 0xFFFFF << 0 );
3077 -( PITC ) Current Periodic Interval Value
3078 AT91C_PITC_PICNT EQU( 0xFFF << 20 );
3079 -( PITC ) Periodic Interval Counter
3080 /* - -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- */
3082 /* - ***************************************************************************** */
3083 /* - SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface */
3084 /* - ***************************************************************************** */
3085 /* - -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- */
3086 AT91C_WDTC_WDRSTT EQU( 0x1 << 0 );
3087 -( WDTC ) Watchdog Restart
3088 AT91C_WDTC_KEY EQU( 0xFF << 24 );
3089 -( WDTC ) Watchdog KEY Password
3090 /* - -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- */
3091 AT91C_WDTC_WDV EQU( 0xFFF << 0 );
3092 -( WDTC ) Watchdog Timer Restart
3093 AT91C_WDTC_WDFIEN EQU( 0x1 << 12 );
3094 -( WDTC ) Watchdog Fault Interrupt Enable
3095 AT91C_WDTC_WDRSTEN EQU( 0x1 << 13 );
3096 -( WDTC ) Watchdog Reset Enable
3097 AT91C_WDTC_WDRPROC EQU( 0x1 << 14 );
3098 -( WDTC ) Watchdog Timer Restart
3099 AT91C_WDTC_WDDIS EQU( 0x1 << 15 );
3100 -( WDTC ) Watchdog Disable
3101 AT91C_WDTC_WDD EQU( 0xFFF << 16 );
3102 -( WDTC ) Watchdog Delta Value
3103 AT91C_WDTC_WDDBGHLT EQU( 0x1 << 28 );
3104 -( WDTC ) Watchdog Debug Halt
3105 AT91C_WDTC_WDIDLEHLT EQU( 0x1 << 29 );
3106 -( WDTC ) Watchdog Idle Halt
3107 /* - -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- */
3108 AT91C_WDTC_WDUNF EQU( 0x1 << 0 );
3109 -( WDTC ) Watchdog Underflow
3110 AT91C_WDTC_WDERR EQU( 0x1 << 1 );
3111 -( WDTC ) Watchdog Error
3113 /* - ***************************************************************************** */
3114 /* - SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface */
3115 /* - ***************************************************************************** */
3116 /* - -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- */
3117 AT91C_VREG_PSTDBY EQU( 0x1 << 0 );
3118 -( VREG ) Voltage Regulator Power Standby Mode
3120 /* - ***************************************************************************** */
3121 /* - SOFTWARE API DEFINITION FOR Memory Controller Interface */
3122 /* - ***************************************************************************** */
3123 /* - -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- */
3124 AT91C_MC_RCB EQU( 0x1 << 0 );
3125 -( MC ) Remap Command Bit
3126 /* - -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- */
3127 AT91C_MC_UNDADD EQU( 0x1 << 0 );
3128 -( MC ) Undefined Address Abort Status
3129 AT91C_MC_MISADD EQU( 0x1 << 1 );
3130 -( MC ) Misaligned Address Abort Status
3131 AT91C_MC_ABTSZ EQU( 0x3 << 8 );
3132 -( MC ) Abort Size Status
3133 AT91C_MC_ABTSZ_BYTE EQU( 0x0 << 8 );
3135 AT91C_MC_ABTSZ_HWORD EQU( 0x1 << 8 );
3137 AT91C_MC_ABTSZ_WORD EQU( 0x2 << 8 );
3139 AT91C_MC_ABTTYP EQU( 0x3 << 10 );
3140 -( MC ) Abort Type Status
3141 AT91C_MC_ABTTYP_DATAR EQU( 0x0 << 10 );
3143 AT91C_MC_ABTTYP_DATAW EQU( 0x1 << 10 );
3145 AT91C_MC_ABTTYP_FETCH EQU( 0x2 << 10 );
3147 AT91C_MC_MST0 EQU( 0x1 << 16 );
3148 -( MC ) Master 0 Abort Source
3149 AT91C_MC_MST1 EQU( 0x1 << 17 );
3150 -( MC ) Master 1 Abort Source
3151 AT91C_MC_SVMST0 EQU( 0x1 << 24 );
3152 -( MC ) Saved Master 0 Abort Source
3153 AT91C_MC_SVMST1 EQU( 0x1 << 25 );
3154 -( MC ) Saved Master 1 Abort Source
3155 /* - -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- */
3156 AT91C_MC_FRDY EQU( 0x1 << 0 );
3158 AT91C_MC_LOCKE EQU( 0x1 << 2 );
3160 AT91C_MC_PROGE EQU( 0x1 << 3 );
3161 -( MC ) Programming Error
3162 AT91C_MC_NEBP EQU( 0x1 << 7 );
3163 -( MC ) No Erase Before Programming
3164 AT91C_MC_FWS EQU( 0x3 << 8 );
3165 -( MC ) Flash Wait State
3166 AT91C_MC_FWS_0FWS EQU( 0x0 << 8 );
3171 for Write operations
3172 AT91C_MC_FWS_1FWS EQU( 0x1 << 8 );
3177 for Write operations
3178 AT91C_MC_FWS_2FWS EQU( 0x2 << 8 );
3183 for Write operations
3184 AT91C_MC_FWS_3FWS EQU( 0x3 << 8 );
3189 for Write operations
3190 AT91C_MC_FMCN EQU( 0xFF << 16 );
3191 -( MC ) Flash Microsecond Cycle Number
3192 /* - -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- */
3193 AT91C_MC_FCMD EQU( 0xF << 0 );
3194 -( MC ) Flash Command
3195 AT91C_MC_FCMD_START_PROG EQU( 0x1 );
3196 -( MC ) Starts the programming of th epage specified by PAGEN.
3197 AT91C_MC_FCMD_LOCK EQU( 0x2 );
3198 -( MC ) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
3199 AT91C_MC_FCMD_PROG_AND_LOCK EQU( 0x3 );
3200 -( MC ) The lock sequence automatically happens after the programming sequence is completed.
3201 AT91C_MC_FCMD_UNLOCK EQU( 0x4 );
3202 -( MC ) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
3203 AT91C_MC_FCMD_ERASE_ALL EQU( 0x8 );
3204 -( MC ) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
3205 AT91C_MC_FCMD_SET_GP_NVM EQU( 0xB );
3206 -( MC ) Set General Purpose NVM bits.
3207 AT91C_MC_FCMD_CLR_GP_NVM EQU( 0xD );
3208 -( MC ) Clear General Purpose NVM bits.
3209 AT91C_MC_FCMD_SET_SECURITY EQU( 0xF );
3210 -( MC ) Set Security Bit.
3211 AT91C_MC_PAGEN EQU( 0x3FF << 8 );
3213 AT91C_MC_KEY EQU( 0xFF << 24 );
3214 -( MC ) Writing Protect Key
3215 /* - -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- */
3216 AT91C_MC_SECURITY EQU( 0x1 << 4 );
3217 -( MC ) Security Bit Status
3218 AT91C_MC_GPNVM0 EQU( 0x1 << 8 );
3219 -( MC ) Sector 0 Lock Status
3220 AT91C_MC_GPNVM1 EQU( 0x1 << 9 );
3221 -( MC ) Sector 1 Lock Status
3222 AT91C_MC_GPNVM2 EQU( 0x1 << 10 );
3223 -( MC ) Sector 2 Lock Status
3224 AT91C_MC_GPNVM3 EQU( 0x1 << 11 );
3225 -( MC ) Sector 3 Lock Status
3226 AT91C_MC_GPNVM4 EQU( 0x1 << 12 );
3227 -( MC ) Sector 4 Lock Status
3228 AT91C_MC_GPNVM5 EQU( 0x1 << 13 );
3229 -( MC ) Sector 5 Lock Status
3230 AT91C_MC_GPNVM6 EQU( 0x1 << 14 );
3231 -( MC ) Sector 6 Lock Status
3232 AT91C_MC_GPNVM7 EQU( 0x1 << 15 );
3233 -( MC ) Sector 7 Lock Status
3234 AT91C_MC_LOCKS0 EQU( 0x1 << 16 );
3235 -( MC ) Sector 0 Lock Status
3236 AT91C_MC_LOCKS1 EQU( 0x1 << 17 );
3237 -( MC ) Sector 1 Lock Status
3238 AT91C_MC_LOCKS2 EQU( 0x1 << 18 );
3239 -( MC ) Sector 2 Lock Status
3240 AT91C_MC_LOCKS3 EQU( 0x1 << 19 );
3241 -( MC ) Sector 3 Lock Status
3242 AT91C_MC_LOCKS4 EQU( 0x1 << 20 );
3243 -( MC ) Sector 4 Lock Status
3244 AT91C_MC_LOCKS5 EQU( 0x1 << 21 );
3245 -( MC ) Sector 5 Lock Status
3246 AT91C_MC_LOCKS6 EQU( 0x1 << 22 );
3247 -( MC ) Sector 6 Lock Status
3248 AT91C_MC_LOCKS7 EQU( 0x1 << 23 );
3249 -( MC ) Sector 7 Lock Status
3250 AT91C_MC_LOCKS8 EQU( 0x1 << 24 );
3251 -( MC ) Sector 8 Lock Status
3252 AT91C_MC_LOCKS9 EQU( 0x1 << 25 );
3253 -( MC ) Sector 9 Lock Status
3254 AT91C_MC_LOCKS10 EQU( 0x1 << 26 );
3255 -( MC ) Sector 10 Lock Status
3256 AT91C_MC_LOCKS11 EQU( 0x1 << 27 );
3257 -( MC ) Sector 11 Lock Status
3258 AT91C_MC_LOCKS12 EQU( 0x1 << 28 );
3259 -( MC ) Sector 12 Lock Status
3260 AT91C_MC_LOCKS13 EQU( 0x1 << 29 );
3261 -( MC ) Sector 13 Lock Status
3262 AT91C_MC_LOCKS14 EQU( 0x1 << 30 );
3263 -( MC ) Sector 14 Lock Status
3264 AT91C_MC_LOCKS15 EQU( 0x1 << 31 );
3265 -( MC ) Sector 15 Lock Status
3267 /* - ***************************************************************************** */
3268 /* - SOFTWARE API DEFINITION FOR Serial Parallel Interface */
3269 /* - ***************************************************************************** */
3270 /* - -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- */
3271 AT91C_SPI_SPIEN EQU( 0x1 << 0 );
3273 AT91C_SPI_SPIDIS EQU( 0x1 << 1 );
3274 -( SPI ) SPI Disable
3275 AT91C_SPI_SWRST EQU( 0x1 << 7 );
3276 -( SPI ) SPI Software reset
3277 AT91C_SPI_LASTXFER EQU( 0x1 << 24 );
3278 -( SPI ) SPI Last Transfer
3279 /* - -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- */
3280 AT91C_SPI_MSTR EQU( 0x1 << 0 );
3281 -( SPI ) Master / Slave Mode
3282 AT91C_SPI_PS EQU( 0x1 << 1 );
3283 -( SPI ) Peripheral Select
3284 AT91C_SPI_PS_FIXED EQU( 0x0 << 1 );
3285 -( SPI ) Fixed Peripheral Select
3286 AT91C_SPI_PS_VARIABLE EQU( 0x1 << 1 );
3287 -( SPI ) Variable Peripheral Select
3288 AT91C_SPI_PCSDEC EQU( 0x1 << 2 );
3289 -( SPI ) Chip Select Decode
3290 AT91C_SPI_FDIV EQU( 0x1 << 3 );
3291 -( SPI ) Clock Selection
3292 AT91C_SPI_MODFDIS EQU( 0x1 << 4 );
3293 -( SPI ) Mode Fault Detection
3294 AT91C_SPI_LLB EQU( 0x1 << 7 );
3295 -( SPI ) Clock Selection
3296 AT91C_SPI_PCS EQU( 0xF << 16 );
3297 -( SPI ) Peripheral Chip Select
3298 AT91C_SPI_DLYBCS EQU( 0xFF << 24 );
3299 -( SPI ) Delay Between Chip Selects
3300 /* - -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- */
3301 AT91C_SPI_RD EQU( 0xFFFF << 0 );
3302 -( SPI ) Receive Data
3303 AT91C_SPI_RPCS EQU( 0xF << 16 );
3304 -( SPI ) Peripheral Chip Select Status
3305 /* - -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- */
3306 AT91C_SPI_TD EQU( 0xFFFF << 0 );
3307 -( SPI ) Transmit Data
3308 AT91C_SPI_TPCS EQU( 0xF << 16 );
3309 -( SPI ) Peripheral Chip Select Status
3310 /* - -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */
3311 AT91C_SPI_RDRF EQU( 0x1 << 0 );
3312 -( SPI ) Receive Data Register Full
3313 AT91C_SPI_TDRE EQU( 0x1 << 1 );
3314 -( SPI ) Transmit Data Register Empty
3315 AT91C_SPI_MODF EQU( 0x1 << 2 );
3316 -( SPI ) Mode Fault Error
3317 AT91C_SPI_OVRES EQU( 0x1 << 3 );
3318 -( SPI ) Overrun Error Status
3319 AT91C_SPI_ENDRX EQU( 0x1 << 4 );
3320 -( SPI ) End of Receiver Transfer
3321 AT91C_SPI_ENDTX EQU( 0x1 << 5 );
3322 -( SPI ) End of Receiver Transfer
3323 AT91C_SPI_RXBUFF EQU( 0x1 << 6 );
3324 -( SPI ) RXBUFF Interrupt
3325 AT91C_SPI_TXBUFE EQU( 0x1 << 7 );
3326 -( SPI ) TXBUFE Interrupt
3327 AT91C_SPI_NSSR EQU( 0x1 << 8 );
3328 -( SPI ) NSSR Interrupt
3329 AT91C_SPI_TXEMPTY EQU( 0x1 << 9 );
3330 -( SPI ) TXEMPTY Interrupt
3331 AT91C_SPI_SPIENS EQU( 0x1 << 16 );
3332 -( SPI ) Enable Status
3333 /* - -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */
3334 /* - -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */
3335 /* - -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- */
3336 /* - -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- */
3337 AT91C_SPI_CPOL EQU( 0x1 << 0 );
3338 -( SPI ) Clock Polarity
3339 AT91C_SPI_NCPHA EQU( 0x1 << 1 );
3340 -( SPI ) Clock Phase
3341 AT91C_SPI_CSAAT EQU( 0x1 << 3 );
3342 -( SPI ) Chip Select Active After Transfer
3343 AT91C_SPI_BITS EQU( 0xF << 4 );
3344 -( SPI ) Bits Per Transfer
3345 AT91C_SPI_BITS_8 EQU( 0x0 << 4 );
3346 -( SPI ) 8 Bits Per transfer
3347 AT91C_SPI_BITS_9 EQU( 0x1 << 4 );
3348 -( SPI ) 9 Bits Per transfer
3349 AT91C_SPI_BITS_10 EQU( 0x2 << 4 );
3350 -( SPI ) 10 Bits Per transfer
3351 AT91C_SPI_BITS_11 EQU( 0x3 << 4 );
3352 -( SPI ) 11 Bits Per transfer
3353 AT91C_SPI_BITS_12 EQU( 0x4 << 4 );
3354 -( SPI ) 12 Bits Per transfer
3355 AT91C_SPI_BITS_13 EQU( 0x5 << 4 );
3356 -( SPI ) 13 Bits Per transfer
3357 AT91C_SPI_BITS_14 EQU( 0x6 << 4 );
3358 -( SPI ) 14 Bits Per transfer
3359 AT91C_SPI_BITS_15 EQU( 0x7 << 4 );
3360 -( SPI ) 15 Bits Per transfer
3361 AT91C_SPI_BITS_16 EQU( 0x8 << 4 );
3362 -( SPI ) 16 Bits Per transfer
3363 AT91C_SPI_SCBR EQU( 0xFF << 8 );
3364 -( SPI ) Serial Clock Baud Rate
3365 AT91C_SPI_DLYBS EQU( 0xFF << 16 );
3366 -( SPI ) Delay Before SPCK
3367 AT91C_SPI_DLYBCT EQU( 0xFF << 24 );
3368 -( SPI ) Delay Between Consecutive Transfers
3370 /* - ***************************************************************************** */
3371 /* - SOFTWARE API DEFINITION FOR Usart */
3372 /* - ***************************************************************************** */
3373 /* - -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- */
3374 AT91C_US_STTBRK EQU( 0x1 << 9 );
3375 -( USART ) Start Break
3376 AT91C_US_STPBRK EQU( 0x1 << 10 );
3377 -( USART ) Stop Break
3378 AT91C_US_STTTO EQU( 0x1 << 11 );
3379 -( USART ) Start Time - out
3380 AT91C_US_SENDA EQU( 0x1 << 12 );
3381 -( USART ) Send Address
3382 AT91C_US_RSTIT EQU( 0x1 << 13 );
3383 -( USART ) Reset Iterations
3384 AT91C_US_RSTNACK EQU( 0x1 << 14 );
3385 -( USART ) Reset Non Acknowledge
3386 AT91C_US_RETTO EQU( 0x1 << 15 );
3387 -( USART ) Rearm Time - out
3388 AT91C_US_DTREN EQU( 0x1 << 16 );
3389 -( USART ) Data Terminal ready Enable
3390 AT91C_US_DTRDIS EQU( 0x1 << 17 );
3391 -( USART ) Data Terminal ready Disable
3392 AT91C_US_RTSEN EQU( 0x1 << 18 );
3393 -( USART ) Request to Send enable
3394 AT91C_US_RTSDIS EQU( 0x1 << 19 );
3395 -( USART ) Request to Send Disable
3396 /* - -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- */
3397 AT91C_US_USMODE EQU( 0xF << 0 );
3398 -( USART ) Usart mode
3399 AT91C_US_USMODE_NORMAL EQU( 0x0 );
3401 AT91C_US_USMODE_RS485 EQU( 0x1 );
3403 AT91C_US_USMODE_HWHSH EQU( 0x2 );
3404 -( USART ) Hardware Handshaking
3405 AT91C_US_USMODE_MODEM EQU( 0x3 );
3407 AT91C_US_USMODE_ISO7816_0 EQU( 0x4 );
3408 -( USART ) ISO7816 protocol: T = 0
3409 AT91C_US_USMODE_ISO7816_1 EQU( 0x6 );
3410 -( USART ) ISO7816 protocol: T = 1
3411 AT91C_US_USMODE_IRDA EQU( 0x8 );
3413 AT91C_US_USMODE_SWHSH EQU( 0xC );
3414 -( USART ) Software Handshaking
3415 AT91C_US_CLKS EQU( 0x3 << 4 );
3416 -( USART ) Clock Selection ( Baud Rate generator Input Clock
3417 AT91C_US_CLKS_CLOCK EQU( 0x0 << 4 );
3419 AT91C_US_CLKS_FDIV1 EQU( 0x1 << 4 );
3421 AT91C_US_CLKS_SLOW EQU( 0x2 << 4 );
3422 -( USART ) slow_clock( ARM )
3423 AT91C_US_CLKS_EXT EQU( 0x3 << 4 );
3424 -( USART ) External( SCK )
3425 AT91C_US_CHRL EQU( 0x3 << 6 );
3426 -( USART ) Clock Selection ( Baud Rate generator Input Clock
3427 AT91C_US_CHRL_5_BITS EQU( 0x0 << 6 );
3428 -( USART ) Character Length : 5 bits
3429 AT91C_US_CHRL_6_BITS EQU( 0x1 << 6 );
3430 -( USART ) Character Length : 6 bits
3431 AT91C_US_CHRL_7_BITS EQU( 0x2 << 6 );
3432 -( USART ) Character Length : 7 bits
3433 AT91C_US_CHRL_8_BITS EQU( 0x3 << 6 );
3434 -( USART ) Character Length : 8 bits
3435 AT91C_US_SYNC EQU( 0x1 << 8 );
3436 -( USART ) Synchronous Mode Select
3437 AT91C_US_NBSTOP EQU( 0x3 << 12 );
3438 -( USART ) Number of Stop bits
3439 AT91C_US_NBSTOP_1_BIT EQU( 0x0 << 12 );
3440 -( USART ) 1 stop bit
3441 AT91C_US_NBSTOP_15_BIT EQU( 0x1 << 12 );
3442 -( USART ) Asynchronous( SYNC = 0 ) 2 stop bits Synchronous( SYNC = 1 ) 2 stop bits
3443 AT91C_US_NBSTOP_2_BIT EQU( 0x2 << 12 );
3444 -( USART ) 2 stop bits
3445 AT91C_US_MSBF EQU( 0x1 << 16 );
3446 -( USART ) Bit Order
3447 AT91C_US_MODE9 EQU( 0x1 << 17 );
3448 -( USART ) 9 - bit Character length
3449 AT91C_US_CKLO EQU( 0x1 << 18 );
3450 -( USART ) Clock Output Select
3451 AT91C_US_OVER EQU( 0x1 << 19 );
3452 -( USART ) Over Sampling Mode
3453 AT91C_US_INACK EQU( 0x1 << 20 );
3454 -( USART ) Inhibit Non Acknowledge
3455 AT91C_US_DSNACK EQU( 0x1 << 21 );
3456 -( USART ) Disable Successive NACK
3457 AT91C_US_MAX_ITER EQU( 0x1 << 24 );
3458 -( USART ) Number of Repetitions
3459 AT91C_US_FILTER EQU( 0x1 << 28 );
3460 -( USART ) Receive Line Filter
3461 /* - -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- */
3462 AT91C_US_RXBRK EQU( 0x1 << 2 );
3463 -( USART ) Break Received / End of Break
3464 AT91C_US_TIMEOUT EQU( 0x1 << 8 );
3465 -( USART ) Receiver Time - out
3466 AT91C_US_ITERATION EQU( 0x1 << 10 );
3467 -( USART ) Max number of Repetitions Reached
3468 AT91C_US_NACK EQU( 0x1 << 13 );
3469 -( USART ) Non Acknowledge
3470 AT91C_US_RIIC EQU( 0x1 << 16 );
3471 -( USART ) Ring INdicator Input Change Flag
3472 AT91C_US_DSRIC EQU( 0x1 << 17 );
3473 -( USART ) Data Set Ready Input Change Flag
3474 AT91C_US_DCDIC EQU( 0x1 << 18 );
3475 -( USART ) Data Carrier Flag
3476 AT91C_US_CTSIC EQU( 0x1 << 19 );
3477 -( USART ) Clear To Send Input Change Flag
3478 /* - -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- */
3479 /* - -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- */
3480 /* - -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- */
3481 AT91C_US_RI EQU( 0x1 << 20 );
3482 -( USART ) Image of RI Input
3483 AT91C_US_DSR EQU( 0x1 << 21 );
3484 -( USART ) Image of DSR Input
3485 AT91C_US_DCD EQU( 0x1 << 22 );
3486 -( USART ) Image of DCD Input
3487 AT91C_US_CTS EQU( 0x1 << 23 );
3488 -( USART ) Image of CTS Input
3490 /* - ***************************************************************************** */
3491 /* - SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface */
3492 /* - ***************************************************************************** */
3493 /* - -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- */
3494 AT91C_SSC_RXEN EQU( 0x1 << 0 );
3495 -( SSC ) Receive Enable
3496 AT91C_SSC_RXDIS EQU( 0x1 << 1 );
3497 -( SSC ) Receive Disable
3498 AT91C_SSC_TXEN EQU( 0x1 << 8 );
3499 -( SSC ) Transmit Enable
3500 AT91C_SSC_TXDIS EQU( 0x1 << 9 );
3501 -( SSC ) Transmit Disable
3502 AT91C_SSC_SWRST EQU( 0x1 << 15 );
3503 -( SSC ) Software Reset
3504 /* - -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- */
3505 AT91C_SSC_CKS EQU( 0x3 << 0 );
3506 -( SSC ) Receive / Transmit Clock Selection
3507 AT91C_SSC_CKS_DIV EQU( 0x0 );
3508 -( SSC ) Divided Clock
3509 AT91C_SSC_CKS_TK EQU( 0x1 );
3510 -( SSC ) TK Clock signal
3511 AT91C_SSC_CKS_RK EQU( 0x2 );
3513 AT91C_SSC_CKO EQU( 0x7 << 2 );
3514 -( SSC ) Receive / Transmit Clock Output Mode Selection
3515 AT91C_SSC_CKO_NONE EQU( 0x0 << 2 );
3516 -( SSC ) Receive / Transmit Clock Output Mode:None RK pin: Input - only
3517 AT91C_SSC_CKO_CONTINUOUS EQU( 0x1 << 2 );
3518 -( SSC ) Continuous Receive / Transmit Clock RK pin:Output
3519 AT91C_SSC_CKO_DATA_TX EQU( 0x2 << 2 );
3520 -( SSC ) Receive / Transmit Clock only during data transfers RK pin:Output
3521 AT91C_SSC_CKI EQU( 0x1 << 5 );
3522 -( SSC ) Receive / Transmit Clock Inversion
3523 AT91C_SSC_START EQU( 0xF << 8 );
3524 -( SSC ) Receive / Transmit Start Selection
3525 AT91C_SSC_START_CONTINUOUS EQU( 0x0 << 8 );
3526 -( SSC ) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
3527 AT91C_SSC_START_TX EQU( 0x1 << 8 );
3528 -( SSC ) Transmit / Receive start
3529 AT91C_SSC_START_LOW_RF EQU( 0x2 << 8 );
3530 -( SSC ) Detection of a low level on RF input
3531 AT91C_SSC_START_HIGH_RF EQU( 0x3 << 8 );
3532 -( SSC ) Detection of a high level on RF input
3533 AT91C_SSC_START_FALL_RF EQU( 0x4 << 8 );
3534 -( SSC ) Detection of a falling edge on RF input
3535 AT91C_SSC_START_RISE_RF EQU( 0x5 << 8 );
3536 -( SSC ) Detection of a rising edge on RF input
3537 AT91C_SSC_START_LEVEL_RF EQU( 0x6 << 8 );
3538 -( SSC ) Detection of any level change on RF input
3539 AT91C_SSC_START_EDGE_RF EQU( 0x7 << 8 );
3540 -( SSC ) Detection of any edge on RF input
3541 AT91C_SSC_START_0 EQU( 0x8 << 8 );
3543 AT91C_SSC_STTDLY EQU( 0xFF << 16 );
3544 -( SSC ) Receive / Transmit Start Delay
3545 AT91C_SSC_PERIOD EQU( 0xFF << 24 );
3546 -( SSC ) Receive / Transmit Period Divider Selection
3547 /* - -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- */
3548 AT91C_SSC_DATLEN EQU( 0x1F << 0 );
3549 -( SSC ) Data Length
3550 AT91C_SSC_LOOP EQU( 0x1 << 5 );
3552 AT91C_SSC_MSBF EQU( 0x1 << 7 );
3553 -( SSC ) Most Significant Bit First
3554 AT91C_SSC_DATNB EQU( 0xF << 8 );
3555 -( SSC ) Data Number per Frame
3556 AT91C_SSC_FSLEN EQU( 0xF << 16 );
3557 -( SSC ) Receive / Transmit Frame Sync length
3558 AT91C_SSC_FSOS EQU( 0x7 << 20 );
3559 -( SSC ) Receive / Transmit Frame Sync Output Selection
3560 AT91C_SSC_FSOS_NONE EQU( 0x0 << 20 );
3561 -( SSC ) Selected Receive / Transmit Frame Sync Signal:None RK pin Input - only
3562 AT91C_SSC_FSOS_NEGATIVE EQU( 0x1 << 20 );
3563 -( SSC ) Selected Receive / Transmit Frame Sync Signal:Negative Pulse
3564 AT91C_SSC_FSOS_POSITIVE EQU( 0x2 << 20 );
3565 -( SSC ) Selected Receive / Transmit Frame Sync Signal:Positive Pulse
3566 AT91C_SSC_FSOS_LOW EQU( 0x3 << 20 );
3567 -( SSC ) Selected Receive / Transmit Frame Sync Signal:Driver Low during data transfer
3568 AT91C_SSC_FSOS_HIGH EQU( 0x4 << 20 );
3569 -( SSC ) Selected Receive / Transmit Frame Sync Signal:Driver High during data transfer
3570 AT91C_SSC_FSOS_TOGGLE EQU( 0x5 << 20 );
3571 -( SSC ) Selected Receive / Transmit Frame Sync Signal:Toggling at each start of data transfer
3572 AT91C_SSC_FSEDGE EQU( 0x1 << 24 );
3573 -( SSC ) Frame Sync Edge Detection
3574 /* - -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- */
3575 /* - -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- */
3576 AT91C_SSC_DATDEF EQU( 0x1 << 5 );
3577 -( SSC ) Data Default Value
3578 AT91C_SSC_FSDEN EQU( 0x1 << 23 );
3579 -( SSC ) Frame Sync Data Enable
3580 /* - -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- */
3581 AT91C_SSC_TXRDY EQU( 0x1 << 0 );
3582 -( SSC ) Transmit Ready
3583 AT91C_SSC_TXEMPTY EQU( 0x1 << 1 );
3584 -( SSC ) Transmit Empty
3585 AT91C_SSC_ENDTX EQU( 0x1 << 2 );
3586 -( SSC ) End Of Transmission
3587 AT91C_SSC_TXBUFE EQU( 0x1 << 3 );
3588 -( SSC ) Transmit Buffer Empty
3589 AT91C_SSC_RXRDY EQU( 0x1 << 4 );
3590 -( SSC ) Receive Ready
3591 AT91C_SSC_OVRUN EQU( 0x1 << 5 );
3592 -( SSC ) Receive Overrun
3593 AT91C_SSC_ENDRX EQU( 0x1 << 6 );
3594 -( SSC ) End of Reception
3595 AT91C_SSC_RXBUFF EQU( 0x1 << 7 );
3596 -( SSC ) Receive Buffer Full
3597 AT91C_SSC_TXSYN EQU( 0x1 << 10 );
3598 -( SSC ) Transmit Sync
3599 AT91C_SSC_RXSYN EQU( 0x1 << 11 );
3600 -( SSC ) Receive Sync
3601 AT91C_SSC_TXENA EQU( 0x1 << 16 );
3602 -( SSC ) Transmit Enable
3603 AT91C_SSC_RXENA EQU( 0x1 << 17 );
3604 -( SSC ) Receive Enable
3605 /* - -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- */
3606 /* - -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- */
3607 /* - -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- */
3609 /* - ***************************************************************************** */
3610 /* - SOFTWARE API DEFINITION FOR Two-wire Interface */
3611 /* - ***************************************************************************** */
3612 /* - -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- */
3613 AT91C_TWI_START EQU( 0x1 << 0 );
3614 -( TWI ) Send a START Condition
3615 AT91C_TWI_STOP EQU( 0x1 << 1 );
3616 -( TWI ) Send a STOP Condition
3617 AT91C_TWI_MSEN EQU( 0x1 << 2 );
3618 -( TWI ) TWI Master Transfer Enabled
3619 AT91C_TWI_MSDIS EQU( 0x1 << 3 );
3620 -( TWI ) TWI Master Transfer Disabled
3621 AT91C_TWI_SWRST EQU( 0x1 << 7 );
3622 -( TWI ) Software Reset
3623 /* - -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- */
3624 AT91C_TWI_IADRSZ EQU( 0x3 << 8 );
3625 -( TWI ) Internal Device Address Size
3626 AT91C_TWI_IADRSZ_NO EQU( 0x0 << 8 );
3627 -( TWI ) No internal device address
3628 AT91C_TWI_IADRSZ_1_BYTE EQU( 0x1 << 8 );
3629 -( TWI ) One - byte internal device address
3630 AT91C_TWI_IADRSZ_2_BYTE EQU( 0x2 << 8 );
3631 -( TWI ) Two - byte internal device address
3632 AT91C_TWI_IADRSZ_3_BYTE EQU( 0x3 << 8 );
3633 -( TWI ) Three - byte internal device address
3634 AT91C_TWI_MREAD EQU( 0x1 << 12 );
3635 -( TWI ) Master Read Direction
3636 AT91C_TWI_DADR EQU( 0x7F << 16 );
3637 -( TWI ) Device Address
3638 /* - -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- */
3639 AT91C_TWI_CLDIV EQU( 0xFF << 0 );
3640 -( TWI ) Clock Low Divider
3641 AT91C_TWI_CHDIV EQU( 0xFF << 8 );
3642 -( TWI ) Clock High Divider
3643 AT91C_TWI_CKDIV EQU( 0x7 << 16 );
3644 -( TWI ) Clock Divider
3645 /* - -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- */
3646 AT91C_TWI_TXCOMP EQU( 0x1 << 0 );
3647 -( TWI ) Transmission Completed
3648 AT91C_TWI_RXRDY EQU( 0x1 << 1 );
3649 -( TWI ) Receive holding register ReaDY
3650 AT91C_TWI_TXRDY EQU( 0x1 << 2 );
3651 -( TWI ) Transmit holding register ReaDY
3652 AT91C_TWI_OVRE EQU( 0x1 << 6 );
3653 -( TWI ) Overrun Error
3654 AT91C_TWI_UNRE EQU( 0x1 << 7 );
3655 -( TWI ) Underrun Error
3656 AT91C_TWI_NACK EQU( 0x1 << 8 );
3657 -( TWI ) Not Acknowledged
3658 /* - -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- */
3659 /* - -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- */
3660 /* - -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- */
3662 /* - ***************************************************************************** */
3663 /* - SOFTWARE API DEFINITION FOR PWMC Channel Interface */
3664 /* - ***************************************************************************** */
3665 /* - -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- */
3666 AT91C_PWMC_CPRE EQU( 0xF << 0 );
3667 -( PWMC_CH ) Channel Pre - scaler:PWMC_CLKx
3668 AT91C_PWMC_CPRE_MCK EQU( 0x0 );
3670 AT91C_PWMC_CPRE_MCKA EQU( 0xB );
3672 AT91C_PWMC_CPRE_MCKB EQU( 0xC );
3674 AT91C_PWMC_CALG EQU( 0x1 << 8 );
3675 -( PWMC_CH ) Channel Alignment
3676 AT91C_PWMC_CPOL EQU( 0x1 << 9 );
3677 -( PWMC_CH ) Channel Polarity
3678 AT91C_PWMC_CPD EQU( 0x1 << 10 );
3679 -( PWMC_CH ) Channel Update Period
3680 /* - -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- */
3681 AT91C_PWMC_CDTY EQU( 0x0 << 0 );
3682 -( PWMC_CH ) Channel Duty Cycle
3683 /* - -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- */
3684 AT91C_PWMC_CPRD EQU( 0x0 << 0 );
3685 -( PWMC_CH ) Channel Period
3686 /* - -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- */
3687 AT91C_PWMC_CCNT EQU( 0x0 << 0 );
3688 -( PWMC_CH ) Channel Counter
3689 /* - -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- */
3690 AT91C_PWMC_CUPD EQU( 0x0 << 0 );
3691 -( PWMC_CH ) Channel Update
3693 /* - ***************************************************************************** */
3694 /* - SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface */
3695 /* - ***************************************************************************** */
3696 /* - -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- */
3697 AT91C_PWMC_DIVA EQU( 0xFF << 0 );
3698 -( PWMC ) CLKA divide factor.
3699 AT91C_PWMC_PREA EQU( 0xF << 8 );
3700 -( PWMC ) Divider Input Clock Prescaler A
3701 AT91C_PWMC_PREA_MCK EQU( 0x0 << 8 );
3703 AT91C_PWMC_DIVB EQU( 0xFF << 16 );
3704 -( PWMC ) CLKB divide factor.
3705 AT91C_PWMC_PREB EQU( 0xF << 24 );
3706 -( PWMC ) Divider Input Clock Prescaler B
3707 AT91C_PWMC_PREB_MCK EQU( 0x0 << 24 );
3709 /* - -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- */
3710 AT91C_PWMC_CHID0 EQU( 0x1 << 0 );
3711 -( PWMC ) Channel ID 0
3712 AT91C_PWMC_CHID1 EQU( 0x1 << 1 );
3713 -( PWMC ) Channel ID 1
3714 AT91C_PWMC_CHID2 EQU( 0x1 << 2 );
3715 -( PWMC ) Channel ID 2
3716 AT91C_PWMC_CHID3 EQU( 0x1 << 3 );
3717 -( PWMC ) Channel ID 3
3718 /* - -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- */
3719 /* - -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- */
3720 /* - -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- */
3721 /* - -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- */
3722 /* - -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- */
3723 /* - -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- */
3725 /* - ***************************************************************************** */
3726 /* - SOFTWARE API DEFINITION FOR USB Device Interface */
3727 /* - ***************************************************************************** */
3728 /* - -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- */
3729 AT91C_UDP_FRM_NUM EQU( 0x7FF << 0 );
3730 -( UDP ) Frame Number as Defined in the Packet Field Formats
3731 AT91C_UDP_FRM_ERR EQU( 0x1 << 16 );
3732 -( UDP ) Frame Error
3733 AT91C_UDP_FRM_OK EQU( 0x1 << 17 );
3735 /* - -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- */
3736 AT91C_UDP_FADDEN EQU( 0x1 << 0 );
3737 -( UDP ) Function Address Enable
3738 AT91C_UDP_CONFG EQU( 0x1 << 1 );
3740 AT91C_UDP_ESR EQU( 0x1 << 2 );
3741 -( UDP ) Enable Send Resume
3742 AT91C_UDP_RSMINPR EQU( 0x1 << 3 );
3743 -( UDP ) A Resume Has Been Sent to the Host
3744 AT91C_UDP_RMWUPE EQU( 0x1 << 4 );
3745 -( UDP ) Remote Wake Up Enable
3746 /* - -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- */
3747 AT91C_UDP_FADD EQU( 0xFF << 0 );
3748 -( UDP ) Function Address Value
3749 AT91C_UDP_FEN EQU( 0x1 << 8 );
3750 -( UDP ) Function Enable
3751 /* - -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- */
3752 AT91C_UDP_EPINT0 EQU( 0x1 << 0 );
3753 -( UDP ) Endpoint 0 Interrupt
3754 AT91C_UDP_EPINT1 EQU( 0x1 << 1 );
3755 -( UDP ) Endpoint 0 Interrupt
3756 AT91C_UDP_EPINT2 EQU( 0x1 << 2 );
3757 -( UDP ) Endpoint 2 Interrupt
3758 AT91C_UDP_EPINT3 EQU( 0x1 << 3 );
3759 -( UDP ) Endpoint 3 Interrupt
3760 AT91C_UDP_EPINT4 EQU( 0x1 << 4 );
3761 -( UDP ) Endpoint 4 Interrupt
3762 AT91C_UDP_EPINT5 EQU( 0x1 << 5 );
3763 -( UDP ) Endpoint 5 Interrupt
3764 AT91C_UDP_RXSUSP EQU( 0x1 << 8 );
3765 -( UDP ) USB Suspend Interrupt
3766 AT91C_UDP_RXRSM EQU( 0x1 << 9 );
3767 -( UDP ) USB Resume Interrupt
3768 AT91C_UDP_EXTRSM EQU( 0x1 << 10 );
3769 -( UDP ) USB External Resume Interrupt
3770 AT91C_UDP_SOFINT EQU( 0x1 << 11 );
3771 -( UDP ) USB Start Of frame Interrupt
3772 AT91C_UDP_WAKEUP EQU( 0x1 << 13 );
3773 -( UDP ) USB Resume Interrupt
3774 /* - -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- */
3775 /* - -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- */
3776 /* - -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- */
3777 AT91C_UDP_ENDBUSRES EQU( 0x1 << 12 );
3778 -( UDP ) USB End Of Bus Reset Interrupt
3779 /* - -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- */
3780 /* - -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- */
3781 AT91C_UDP_EP0 EQU( 0x1 << 0 );
3782 -( UDP ) Reset Endpoint 0
3783 AT91C_UDP_EP1 EQU( 0x1 << 1 );
3784 -( UDP ) Reset Endpoint 1
3785 AT91C_UDP_EP2 EQU( 0x1 << 2 );
3786 -( UDP ) Reset Endpoint 2
3787 AT91C_UDP_EP3 EQU( 0x1 << 3 );
3788 -( UDP ) Reset Endpoint 3
3789 AT91C_UDP_EP4 EQU( 0x1 << 4 );
3790 -( UDP ) Reset Endpoint 4
3791 AT91C_UDP_EP5 EQU( 0x1 << 5 );
3792 -( UDP ) Reset Endpoint 5
3793 /* - -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- */
3794 AT91C_UDP_TXCOMP EQU( 0x1 << 0 );
3795 -( UDP ) Generates an IN packet with data previously written in the DPR
3796 AT91C_UDP_RX_DATA_BK0 EQU( 0x1 << 1 );
3797 -( UDP ) Receive Data Bank 0
3798 AT91C_UDP_RXSETUP EQU( 0x1 << 2 );
3799 -( UDP ) Sends STALL to the Host( Control endpoints )
3800 AT91C_UDP_ISOERROR EQU( 0x1 << 3 );
3801 -( UDP ) Isochronous error( Isochronous endpoints )
3802 AT91C_UDP_TXPKTRDY EQU( 0x1 << 4 );
3803 -( UDP ) Transmit Packet Ready
3804 AT91C_UDP_FORCESTALL EQU( 0x1 << 5 );
3805 -( UDP ) Force Stall( used by Control, Bulk and Isochronous endpoints ).
3806 AT91C_UDP_RX_DATA_BK1 EQU( 0x1 << 6 );
3807 -( UDP ) Receive Data Bank 1 ( only used by endpoints with ping - pong attributes ).
3808 AT91C_UDP_DIR EQU( 0x1 << 7 );
3809 -( UDP ) Transfer Direction
3810 AT91C_UDP_EPTYPE EQU( 0x7 << 8 );
3811 -( UDP ) Endpoint type
3812 AT91C_UDP_EPTYPE_CTRL EQU( 0x0 << 8 );
3814 AT91C_UDP_EPTYPE_ISO_OUT EQU( 0x1 << 8 );
3815 -( UDP ) Isochronous OUT
3816 AT91C_UDP_EPTYPE_BULK_OUT EQU( 0x2 << 8 );
3818 AT91C_UDP_EPTYPE_INT_OUT EQU( 0x3 << 8 );
3819 -( UDP ) Interrupt OUT
3820 AT91C_UDP_EPTYPE_ISO_IN EQU( 0x5 << 8 );
3821 -( UDP ) Isochronous IN
3822 AT91C_UDP_EPTYPE_BULK_IN EQU( 0x6 << 8 );
3824 AT91C_UDP_EPTYPE_INT_IN EQU( 0x7 << 8 );
3825 -( UDP ) Interrupt IN
3826 AT91C_UDP_DTGLE EQU( 0x1 << 11 );
3827 -( UDP ) Data Toggle
3828 AT91C_UDP_EPEDS EQU( 0x1 << 15 );
3829 -( UDP ) Endpoint Enable Disable
3830 AT91C_UDP_RXBYTECNT EQU( 0x7FF << 16 );
3831 -( UDP ) Number Of Bytes Available in the FIFO
3832 /* - -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- */
3833 AT91C_UDP_TXVDIS EQU( 0x1 << 8 );
3835 AT91C_UDP_PUON EQU( 0x1 << 9 );
3836 -( UDP ) Pull - up ON
3838 /* - ***************************************************************************** */
3839 /* - SOFTWARE API DEFINITION FOR Timer Counter Channel Interface */
3840 /* - ***************************************************************************** */
3841 /* - -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- */
3842 AT91C_TC_CLKEN EQU( 0x1 << 0 );
3843 -( TC ) Counter Clock Enable Command
3844 AT91C_TC_CLKDIS EQU( 0x1 << 1 );
3845 -( TC ) Counter Clock Disable Command
3846 AT91C_TC_SWTRG EQU( 0x1 << 2 );
3847 -( TC ) Software Trigger Command
3848 /* - -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- */
3849 AT91C_TC_CLKS EQU( 0x7 << 0 );
3850 -( TC ) Clock Selection
3851 AT91C_TC_CLKS_TIMER_DIV1_CLOCK EQU( 0x0 );
3852 -( TC ) Clock selected:TIMER_DIV1_CLOCK
3853 AT91C_TC_CLKS_TIMER_DIV2_CLOCK EQU( 0x1 );
3854 -( TC ) Clock selected:TIMER_DIV2_CLOCK
3855 AT91C_TC_CLKS_TIMER_DIV3_CLOCK EQU( 0x2 );
3856 -( TC ) Clock selected:TIMER_DIV3_CLOCK
3857 AT91C_TC_CLKS_TIMER_DIV4_CLOCK EQU( 0x3 );
3858 -( TC ) Clock selected:TIMER_DIV4_CLOCK
3859 AT91C_TC_CLKS_TIMER_DIV5_CLOCK EQU( 0x4 );
3860 -( TC ) Clock selected:TIMER_DIV5_CLOCK
3861 AT91C_TC_CLKS_XC0 EQU( 0x5 );
3862 -( TC ) Clock selected:XC0
3863 AT91C_TC_CLKS_XC1 EQU( 0x6 );
3864 -( TC ) Clock selected:XC1
3865 AT91C_TC_CLKS_XC2 EQU( 0x7 );
3866 -( TC ) Clock selected:XC2
3867 AT91C_TC_CLKI EQU( 0x1 << 3 );
3868 -( TC ) Clock Invert
3869 AT91C_TC_BURST EQU( 0x3 << 4 );
3870 -( TC ) Burst Signal Selection
3871 AT91C_TC_BURST_NONE EQU( 0x0 << 4 );
3872 -( TC ) The clock is not gated by an external signal
3873 AT91C_TC_BURST_XC0 EQU( 0x1 << 4 );
3874 -( TC ) XC0 is ANDed with the selected clock
3875 AT91C_TC_BURST_XC1 EQU( 0x2 << 4 );
3876 -( TC ) XC1 is ANDed with the selected clock
3877 AT91C_TC_BURST_XC2 EQU( 0x3 << 4 );
3878 -( TC ) XC2 is ANDed with the selected clock
3879 AT91C_TC_CPCSTOP EQU( 0x1 << 6 );
3880 -( TC ) Counter Clock Stopped with RC Compare
3881 AT91C_TC_LDBSTOP EQU( 0x1 << 6 );
3882 -( TC ) Counter Clock Stopped with RB Loading
3883 AT91C_TC_CPCDIS EQU( 0x1 << 7 );
3884 -( TC ) Counter Clock Disable with RC Compare
3885 AT91C_TC_LDBDIS EQU( 0x1 << 7 );
3886 -( TC ) Counter Clock Disabled with RB Loading
3887 AT91C_TC_ETRGEDG EQU( 0x3 << 8 );
3888 -( TC ) External Trigger Edge Selection
3889 AT91C_TC_ETRGEDG_NONE EQU( 0x0 << 8 );
3891 AT91C_TC_ETRGEDG_RISING EQU( 0x1 << 8 );
3892 -( TC ) Edge:rising edge
3893 AT91C_TC_ETRGEDG_FALLING EQU( 0x2 << 8 );
3894 -( TC ) Edge:falling edge
3895 AT91C_TC_ETRGEDG_BOTH EQU( 0x3 << 8 );
3896 -( TC ) Edge:each edge
3897 AT91C_TC_EEVTEDG EQU( 0x3 << 8 );
3898 -( TC ) External Event Edge Selection
3899 AT91C_TC_EEVTEDG_NONE EQU( 0x0 << 8 );
3901 AT91C_TC_EEVTEDG_RISING EQU( 0x1 << 8 );
3902 -( TC ) Edge:rising edge
3903 AT91C_TC_EEVTEDG_FALLING EQU( 0x2 << 8 );
3904 -( TC ) Edge:falling edge
3905 AT91C_TC_EEVTEDG_BOTH EQU( 0x3 << 8 );
3906 -( TC ) Edge:each edge
3907 AT91C_TC_EEVT EQU( 0x3 << 10 );
3908 -( TC ) External Event Selection
3909 AT91C_TC_EEVT_TIOB EQU( 0x0 << 10 );
3910 -( TC ) Signal selected as external event:TIOB TIOB direction: input
3911 AT91C_TC_EEVT_XC0 EQU( 0x1 << 10 );
3912 -( TC ) Signal selected as external event:XC0 TIOB direction: output
3913 AT91C_TC_EEVT_XC1 EQU( 0x2 << 10 );
3914 -( TC ) Signal selected as external event:XC1 TIOB direction: output
3915 AT91C_TC_EEVT_XC2 EQU( 0x3 << 10 );
3916 -( TC ) Signal selected as external event:XC2 TIOB direction: output
3917 AT91C_TC_ABETRG EQU( 0x1 << 10 );
3918 -( TC ) TIOA or TIOB External Trigger Selection
3919 AT91C_TC_ENETRG EQU( 0x1 << 12 );
3920 -( TC ) External Event Trigger enable
3921 AT91C_TC_WAVESEL EQU( 0x3 << 13 );
3922 -( TC ) Waveform Selection
3923 AT91C_TC_WAVESEL_UP EQU( 0x0 << 13 );
3924 -( TC ) UP mode without atomatic trigger on RC Compare
3925 AT91C_TC_WAVESEL_UPDOWN EQU( 0x1 << 13 );
3926 -( TC ) UPDOWN mode without automatic trigger on RC Compare
3927 AT91C_TC_WAVESEL_UP_AUTO EQU( 0x2 << 13 );
3928 -( TC ) UP mode with automatic trigger on RC Compare
3929 AT91C_TC_WAVESEL_UPDOWN_AUTO EQU( 0x3 << 13 );
3930 -( TC ) UPDOWN mode with automatic trigger on RC Compare
3931 AT91C_TC_CPCTRG EQU( 0x1 << 14 );
3932 -( TC ) RC Compare Trigger Enable
3933 AT91C_TC_WAVE EQU( 0x1 << 15 );
3935 AT91C_TC_ACPA EQU( 0x3 << 16 );
3936 -( TC ) RA Compare Effect on TIOA
3937 AT91C_TC_ACPA_NONE EQU( 0x0 << 16 );
3939 AT91C_TC_ACPA_SET EQU( 0x1 << 16 );
3941 AT91C_TC_ACPA_CLEAR EQU( 0x2 << 16 );
3942 -( TC ) Effect:clear
3943 AT91C_TC_ACPA_TOGGLE EQU( 0x3 << 16 );
3944 -( TC ) Effect:toggle
3945 AT91C_TC_LDRA EQU( 0x3 << 16 );
3946 -( TC ) RA Loading Selection
3947 AT91C_TC_LDRA_NONE EQU( 0x0 << 16 );
3949 AT91C_TC_LDRA_RISING EQU( 0x1 << 16 );
3950 -( TC ) Edge:rising edge of TIOA
3951 AT91C_TC_LDRA_FALLING EQU( 0x2 << 16 );
3952 -( TC ) Edge:falling edge of TIOA
3953 AT91C_TC_LDRA_BOTH EQU( 0x3 << 16 );
3954 -( TC ) Edge:each edge of TIOA
3955 AT91C_TC_ACPC EQU( 0x3 << 18 );
3956 -( TC ) RC Compare Effect on TIOA
3957 AT91C_TC_ACPC_NONE EQU( 0x0 << 18 );
3959 AT91C_TC_ACPC_SET EQU( 0x1 << 18 );
3961 AT91C_TC_ACPC_CLEAR EQU( 0x2 << 18 );
3962 -( TC ) Effect:clear
3963 AT91C_TC_ACPC_TOGGLE EQU( 0x3 << 18 );
3964 -( TC ) Effect:toggle
3965 AT91C_TC_LDRB EQU( 0x3 << 18 );
3966 -( TC ) RB Loading Selection
3967 AT91C_TC_LDRB_NONE EQU( 0x0 << 18 );
3969 AT91C_TC_LDRB_RISING EQU( 0x1 << 18 );
3970 -( TC ) Edge:rising edge of TIOA
3971 AT91C_TC_LDRB_FALLING EQU( 0x2 << 18 );
3972 -( TC ) Edge:falling edge of TIOA
3973 AT91C_TC_LDRB_BOTH EQU( 0x3 << 18 );
3974 -( TC ) Edge:each edge of TIOA
3975 AT91C_TC_AEEVT EQU( 0x3 << 20 );
3976 -( TC ) External Event Effect on TIOA
3977 AT91C_TC_AEEVT_NONE EQU( 0x0 << 20 );
3979 AT91C_TC_AEEVT_SET EQU( 0x1 << 20 );
3981 AT91C_TC_AEEVT_CLEAR EQU( 0x2 << 20 );
3982 -( TC ) Effect:clear
3983 AT91C_TC_AEEVT_TOGGLE EQU( 0x3 << 20 );
3984 -( TC ) Effect:toggle
3985 AT91C_TC_ASWTRG EQU( 0x3 << 22 );
3986 -( TC ) Software Trigger Effect on TIOA
3987 AT91C_TC_ASWTRG_NONE EQU( 0x0 << 22 );
3989 AT91C_TC_ASWTRG_SET EQU( 0x1 << 22 );
3991 AT91C_TC_ASWTRG_CLEAR EQU( 0x2 << 22 );
3992 -( TC ) Effect:clear
3993 AT91C_TC_ASWTRG_TOGGLE EQU( 0x3 << 22 );
3994 -( TC ) Effect:toggle
3995 AT91C_TC_BCPB EQU( 0x3 << 24 );
3996 -( TC ) RB Compare Effect on TIOB
3997 AT91C_TC_BCPB_NONE EQU( 0x0 << 24 );
3999 AT91C_TC_BCPB_SET EQU( 0x1 << 24 );
4001 AT91C_TC_BCPB_CLEAR EQU( 0x2 << 24 );
4002 -( TC ) Effect:clear
4003 AT91C_TC_BCPB_TOGGLE EQU( 0x3 << 24 );
4004 -( TC ) Effect:toggle
4005 AT91C_TC_BCPC EQU( 0x3 << 26 );
4006 -( TC ) RC Compare Effect on TIOB
4007 AT91C_TC_BCPC_NONE EQU( 0x0 << 26 );
4009 AT91C_TC_BCPC_SET EQU( 0x1 << 26 );
4011 AT91C_TC_BCPC_CLEAR EQU( 0x2 << 26 );
4012 -( TC ) Effect:clear
4013 AT91C_TC_BCPC_TOGGLE EQU( 0x3 << 26 );
4014 -( TC ) Effect:toggle
4015 AT91C_TC_BEEVT EQU( 0x3 << 28 );
4016 -( TC ) External Event Effect on TIOB
4017 AT91C_TC_BEEVT_NONE EQU( 0x0 << 28 );
4019 AT91C_TC_BEEVT_SET EQU( 0x1 << 28 );
4021 AT91C_TC_BEEVT_CLEAR EQU( 0x2 << 28 );
4022 -( TC ) Effect:clear
4023 AT91C_TC_BEEVT_TOGGLE EQU( 0x3 << 28 );
4024 -( TC ) Effect:toggle
4025 AT91C_TC_BSWTRG EQU( 0x3 << 30 );
4026 -( TC ) Software Trigger Effect on TIOB
4027 AT91C_TC_BSWTRG_NONE EQU( 0x0 << 30 );
4029 AT91C_TC_BSWTRG_SET EQU( 0x1 << 30 );
4031 AT91C_TC_BSWTRG_CLEAR EQU( 0x2 << 30 );
4032 -( TC ) Effect:clear
4033 AT91C_TC_BSWTRG_TOGGLE EQU( 0x3 << 30 );
4034 -( TC ) Effect:toggle
4035 /* - -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- */
4036 AT91C_TC_COVFS EQU( 0x1 << 0 );
4037 -( TC ) Counter Overflow
4038 AT91C_TC_LOVRS EQU( 0x1 << 1 );
4039 -( TC ) Load Overrun
4040 AT91C_TC_CPAS EQU( 0x1 << 2 );
4042 AT91C_TC_CPBS EQU( 0x1 << 3 );
4044 AT91C_TC_CPCS EQU( 0x1 << 4 );
4046 AT91C_TC_LDRAS EQU( 0x1 << 5 );
4048 AT91C_TC_LDRBS EQU( 0x1 << 6 );
4050 AT91C_TC_ETRGS EQU( 0x1 << 7 );
4051 -( TC ) External Trigger
4052 AT91C_TC_CLKSTA EQU( 0x1 << 16 );
4053 -( TC ) Clock Enabling
4054 AT91C_TC_MTIOA EQU( 0x1 << 17 );
4056 AT91C_TC_MTIOB EQU( 0x1 << 18 );
4058 /* - -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- */
4059 /* - -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- */
4060 /* - -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- */
4062 /* - ***************************************************************************** */
4063 /* - SOFTWARE API DEFINITION FOR Timer Counter Interface */
4064 /* - ***************************************************************************** */
4065 /* - -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- */
4066 AT91C_TCB_SYNC EQU( 0x1 << 0 );
4067 -( TCB ) Synchro Command
4068 /* - -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- */
4069 AT91C_TCB_TC0XC0S EQU( 0x3 << 0 );
4070 -( TCB ) External Clock Signal 0 Selection
4071 AT91C_TCB_TC0XC0S_TCLK0 EQU( 0x0 );
4072 -( TCB ) TCLK0 connected to XC0
4073 AT91C_TCB_TC0XC0S_NONE EQU( 0x1 );
4074 -( TCB ) None signal connected to XC0
4075 AT91C_TCB_TC0XC0S_TIOA1 EQU( 0x2 );
4076 -( TCB ) TIOA1 connected to XC0
4077 AT91C_TCB_TC0XC0S_TIOA2 EQU( 0x3 );
4078 -( TCB ) TIOA2 connected to XC0
4079 AT91C_TCB_TC1XC1S EQU( 0x3 << 2 );
4080 -( TCB ) External Clock Signal 1 Selection
4081 AT91C_TCB_TC1XC1S_TCLK1 EQU( 0x0 << 2 );
4082 -( TCB ) TCLK1 connected to XC1
4083 AT91C_TCB_TC1XC1S_NONE EQU( 0x1 << 2 );
4084 -( TCB ) None signal connected to XC1
4085 AT91C_TCB_TC1XC1S_TIOA0 EQU( 0x2 << 2 );
4086 -( TCB ) TIOA0 connected to XC1
4087 AT91C_TCB_TC1XC1S_TIOA2 EQU( 0x3 << 2 );
4088 -( TCB ) TIOA2 connected to XC1
4089 AT91C_TCB_TC2XC2S EQU( 0x3 << 4 );
4090 -( TCB ) External Clock Signal 2 Selection
4091 AT91C_TCB_TC2XC2S_TCLK2 EQU( 0x0 << 4 );
4092 -( TCB ) TCLK2 connected to XC2
4093 AT91C_TCB_TC2XC2S_NONE EQU( 0x1 << 4 );
4094 -( TCB ) None signal connected to XC2
4095 AT91C_TCB_TC2XC2S_TIOA0 EQU( 0x2 << 4 );
4096 -( TCB ) TIOA0 connected to XC2
4097 AT91C_TCB_TC2XC2S_TIOA1 EQU( 0x3 << 4 );
4098 -( TCB ) TIOA2 connected to XC2
4100 /* - ***************************************************************************** */
4101 /* - SOFTWARE API DEFINITION FOR Control Area Network MailBox Interface */
4102 /* - ***************************************************************************** */
4103 /* - -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- */
4104 AT91C_CAN_MTIMEMARK EQU( 0xFFFF << 0 );
4105 -( CAN_MB ) Mailbox Timemark
4106 AT91C_CAN_PRIOR EQU( 0xF << 16 );
4107 -( CAN_MB ) Mailbox Priority
4108 AT91C_CAN_MOT EQU( 0x7 << 24 );
4109 -( CAN_MB ) Mailbox Object Type
4110 AT91C_CAN_MOT_DIS EQU( 0x0 << 24 );
4112 AT91C_CAN_MOT_RX EQU( 0x1 << 24 );
4114 AT91C_CAN_MOT_RXOVERWRITE EQU( 0x2 << 24 );
4116 AT91C_CAN_MOT_TX EQU( 0x3 << 24 );
4118 AT91C_CAN_MOT_CONSUMER EQU( 0x4 << 24 );
4120 AT91C_CAN_MOT_PRODUCER EQU( 0x5 << 24 );
4122 /* - -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- */
4123 AT91C_CAN_MIDvB EQU( 0x3FFFF << 0 );
4124 -( CAN_MB ) Complementary bits
4126 for identifier in extended mode
4127 AT91C_CAN_MIDvA EQU( 0x7FF << 18 );
4128 -( CAN_MB ) Identifier
4130 for standard frame mode
4131 AT91C_CAN_MIDE EQU( 0x1 << 29 );
4132 -( CAN_MB ) Identifier Version
4133 /* - -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- */
4134 /* - -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- */
4135 /* - -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- */
4136 AT91C_CAN_MTIMESTAMP EQU( 0xFFFF << 0 );
4137 -( CAN_MB ) Timer Value
4138 AT91C_CAN_MDLC EQU( 0xF << 16 );
4139 -( CAN_MB ) Mailbox Data Length Code
4140 AT91C_CAN_MRTR EQU( 0x1 << 20 );
4141 -( CAN_MB ) Mailbox Remote Transmission Request
4142 AT91C_CAN_MABT EQU( 0x1 << 22 );
4143 -( CAN_MB ) Mailbox Message Abort
4144 AT91C_CAN_MRDY EQU( 0x1 << 23 );
4145 -( CAN_MB ) Mailbox Ready
4146 AT91C_CAN_MMI EQU( 0x1 << 24 );
4147 -( CAN_MB ) Mailbox Message Ignored
4148 /* - -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- */
4149 /* - -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- */
4150 /* - -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- */
4151 AT91C_CAN_MACR EQU( 0x1 << 22 );
4152 -( CAN_MB ) Abort Request
4155 AT91C_CAN_MTCR EQU( 0x1 << 23 );
4156 -( CAN_MB ) Mailbox Transfer Command
4158 /* - ***************************************************************************** */
4159 /* - SOFTWARE API DEFINITION FOR Control Area Network Interface */
4160 /* - ***************************************************************************** */
4161 /* - -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- */
4162 AT91C_CAN_CANEN EQU( 0x1 << 0 );
4163 -( CAN ) CAN Controller Enable
4164 AT91C_CAN_LPM EQU( 0x1 << 1 );
4165 -( CAN ) Disable / Enable Low Power Mode
4166 AT91C_CAN_ABM EQU( 0x1 << 2 );
4167 -( CAN ) Disable / Enable Autobaud / Listen Mode
4168 AT91C_CAN_OVL EQU( 0x1 << 3 );
4169 -( CAN ) Disable / Enable Overload Frame
4170 AT91C_CAN_TEOF EQU( 0x1 << 4 );
4171 -( CAN ) Time Stamp messages at each end of Frame
4172 AT91C_CAN_TTM EQU( 0x1 << 5 );
4173 -( CAN ) Disable / Enable Time Trigger Mode
4174 AT91C_CAN_TIMFRZ EQU( 0x1 << 6 );
4175 -( CAN ) Enable Timer Freeze
4176 AT91C_CAN_DRPT EQU( 0x1 << 7 );
4177 -( CAN ) Disable Repeat
4178 /* - -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- */
4179 AT91C_CAN_MB0 EQU( 0x1 << 0 );
4180 -( CAN ) Mailbox 0 Flag
4181 AT91C_CAN_MB1 EQU( 0x1 << 1 );
4182 -( CAN ) Mailbox 1 Flag
4183 AT91C_CAN_MB2 EQU( 0x1 << 2 );
4184 -( CAN ) Mailbox 2 Flag
4185 AT91C_CAN_MB3 EQU( 0x1 << 3 );
4186 -( CAN ) Mailbox 3 Flag
4187 AT91C_CAN_MB4 EQU( 0x1 << 4 );
4188 -( CAN ) Mailbox 4 Flag
4189 AT91C_CAN_MB5 EQU( 0x1 << 5 );
4190 -( CAN ) Mailbox 5 Flag
4191 AT91C_CAN_MB6 EQU( 0x1 << 6 );
4192 -( CAN ) Mailbox 6 Flag
4193 AT91C_CAN_MB7 EQU( 0x1 << 7 );
4194 -( CAN ) Mailbox 7 Flag
4195 AT91C_CAN_MB8 EQU( 0x1 << 8 );
4196 -( CAN ) Mailbox 8 Flag
4197 AT91C_CAN_MB9 EQU( 0x1 << 9 );
4198 -( CAN ) Mailbox 9 Flag
4199 AT91C_CAN_MB10 EQU( 0x1 << 10 );
4200 -( CAN ) Mailbox 10 Flag
4201 AT91C_CAN_MB11 EQU( 0x1 << 11 );
4202 -( CAN ) Mailbox 11 Flag
4203 AT91C_CAN_MB12 EQU( 0x1 << 12 );
4204 -( CAN ) Mailbox 12 Flag
4205 AT91C_CAN_MB13 EQU( 0x1 << 13 );
4206 -( CAN ) Mailbox 13 Flag
4207 AT91C_CAN_MB14 EQU( 0x1 << 14 );
4208 -( CAN ) Mailbox 14 Flag
4209 AT91C_CAN_MB15 EQU( 0x1 << 15 );
4210 -( CAN ) Mailbox 15 Flag
4211 AT91C_CAN_ERRA EQU( 0x1 << 16 );
4212 -( CAN ) Error Active Mode Flag
4213 AT91C_CAN_WARN EQU( 0x1 << 17 );
4214 -( CAN ) Warning Limit Flag
4215 AT91C_CAN_ERRP EQU( 0x1 << 18 );
4216 -( CAN ) Error Passive Mode Flag
4217 AT91C_CAN_BOFF EQU( 0x1 << 19 );
4218 -( CAN ) Bus Off Mode Flag
4219 AT91C_CAN_SLEEP EQU( 0x1 << 20 );
4221 AT91C_CAN_WAKEUP EQU( 0x1 << 21 );
4222 -( CAN ) Wakeup Flag
4223 AT91C_CAN_TOVF EQU( 0x1 << 22 );
4224 -( CAN ) Timer Overflow Flag
4225 AT91C_CAN_TSTP EQU( 0x1 << 23 );
4226 -( CAN ) Timestamp Flag
4227 AT91C_CAN_CERR EQU( 0x1 << 24 );
4229 AT91C_CAN_SERR EQU( 0x1 << 25 );
4230 -( CAN ) Stuffing Error
4231 AT91C_CAN_AERR EQU( 0x1 << 26 );
4232 -( CAN ) Acknowledgment Error
4233 AT91C_CAN_FERR EQU( 0x1 << 27 );
4235 AT91C_CAN_BERR EQU( 0x1 << 28 );
4237 /* - -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- */
4238 /* - -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- */
4239 /* - -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- */
4240 AT91C_CAN_RBSY EQU( 0x1 << 29 );
4241 -( CAN ) Receiver Busy
4242 AT91C_CAN_TBSY EQU( 0x1 << 30 );
4243 -( CAN ) Transmitter Busy
4244 AT91C_CAN_OVLY EQU( 0x1 << 31 );
4245 -( CAN ) Overload Busy
4246 /* - -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- */
4247 AT91C_CAN_PHASE2 EQU( 0x7 << 0 );
4248 -( CAN ) Phase 2 segment
4249 AT91C_CAN_PHASE1 EQU( 0x7 << 4 );
4250 -( CAN ) Phase 1 segment
4251 AT91C_CAN_PROPAG EQU( 0x7 << 8 );
4252 -( CAN ) Programmation time segment
4253 AT91C_CAN_SYNC EQU( 0x3 << 12 );
4254 -( CAN ) Re - synchronization jump width segment
4255 AT91C_CAN_BRP EQU( 0x7F << 16 );
4256 -( CAN ) Baudrate Prescaler
4257 AT91C_CAN_SMP EQU( 0x1 << 24 );
4258 -( CAN ) Sampling mode
4259 /* - -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- */
4260 AT91C_CAN_TIMER EQU( 0xFFFF << 0 );
4261 -( CAN ) Timer field
4262 /* - -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- */
4263 /* - -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- */
4264 AT91C_CAN_REC EQU( 0xFF << 0 );
4265 -( CAN ) Receive Error Counter
4266 AT91C_CAN_TEC EQU( 0xFF << 16 );
4267 -( CAN ) Transmit Error Counter
4268 /* - -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- */
4269 AT91C_CAN_TIMRST EQU( 0x1 << 31 );
4270 -( CAN ) Timer Reset Field
4271 /* - -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- */
4273 /* - ***************************************************************************** */
4274 /* - SOFTWARE API DEFINITION FOR Ethernet MAC 10/100 */
4275 /* - ***************************************************************************** */
4276 /* - -------- EMAC_NCR : (EMAC Offset: 0x0) -------- */
4277 AT91C_EMAC_LB EQU( 0x1 << 0 );
4278 -( EMAC ) Loopback.Optional.When set, loopback signal is at high level.
4279 AT91C_EMAC_LLB EQU( 0x1 << 1 );
4280 -( EMAC ) Loopback local.
4281 AT91C_EMAC_RE EQU( 0x1 << 2 );
4282 -( EMAC ) Receive enable.
4283 AT91C_EMAC_TE EQU( 0x1 << 3 );
4284 -( EMAC ) Transmit enable.
4285 AT91C_EMAC_MPE EQU( 0x1 << 4 );
4286 -( EMAC ) Management port enable.
4287 AT91C_EMAC_CLRSTAT EQU( 0x1 << 5 );
4288 -( EMAC ) Clear statistics registers.
4289 AT91C_EMAC_INCSTAT EQU( 0x1 << 6 );
4290 -( EMAC ) Increment statistics registers.
4291 AT91C_EMAC_WESTAT EQU( 0x1 << 7 );
4292 -( EMAC ) Write enable
4294 for statistics registers.
4295 AT91C_EMAC_BP EQU( 0x1 << 8 );
4296 -( EMAC ) Back pressure.
4297 AT91C_EMAC_TSTART EQU( 0x1 << 9 );
4298 -( EMAC ) Start Transmission.
4299 AT91C_EMAC_THALT EQU( 0x1 << 10 );
4300 -( EMAC ) Transmission Halt.
4301 AT91C_EMAC_TPFR EQU( 0x1 << 11 );
4302 -( EMAC ) Transmit pause frame
4303 AT91C_EMAC_TZQ EQU( 0x1 << 12 );
4304 -( EMAC ) Transmit zero quantum pause frame
4305 /* - -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- */
4306 AT91C_EMAC_SPD EQU( 0x1 << 0 );
4308 AT91C_EMAC_FD EQU( 0x1 << 1 );
4309 -( EMAC ) Full duplex.
4310 AT91C_EMAC_JFRAME EQU( 0x1 << 3 );
4311 -( EMAC ) Jumbo Frames.
4312 AT91C_EMAC_CAF EQU( 0x1 << 4 );
4313 -( EMAC ) Copy all frames.
4314 AT91C_EMAC_NBC EQU( 0x1 << 5 );
4315 -( EMAC ) No broadcast.
4316 AT91C_EMAC_MTI EQU( 0x1 << 6 );
4317 -( EMAC ) Multicast hash event enable
4318 AT91C_EMAC_UNI EQU( 0x1 << 7 );
4319 -( EMAC ) Unicast hash enable.
4320 AT91C_EMAC_BIG EQU( 0x1 << 8 );
4321 -( EMAC ) Receive 1522 bytes.
4322 AT91C_EMAC_EAE EQU( 0x1 << 9 );
4323 -( EMAC ) External address match enable.
4324 AT91C_EMAC_CLK EQU( 0x3 << 10 );
4326 AT91C_EMAC_CLK_HCLK_8 EQU( 0x0 << 10 );
4327 -( EMAC ) HCLK divided by 8
4328 AT91C_EMAC_CLK_HCLK_16 EQU( 0x1 << 10 );
4329 -( EMAC ) HCLK divided by 16
4330 AT91C_EMAC_CLK_HCLK_32 EQU( 0x2 << 10 );
4331 -( EMAC ) HCLK divided by 32
4332 AT91C_EMAC_CLK_HCLK_64 EQU( 0x3 << 10 );
4333 -( EMAC ) HCLK divided by 64
4334 AT91C_EMAC_RTY EQU( 0x1 << 12 );
4336 AT91C_EMAC_PAE EQU( 0x1 << 13 );
4338 AT91C_EMAC_RBOF EQU( 0x3 << 14 );
4340 AT91C_EMAC_RBOF_OFFSET_0 EQU( 0x0 << 14 );
4341 -( EMAC ) no offset from start of receive buffer
4342 AT91C_EMAC_RBOF_OFFSET_1 EQU( 0x1 << 14 );
4343 -( EMAC ) one byte offset from start of receive buffer
4344 AT91C_EMAC_RBOF_OFFSET_2 EQU( 0x2 << 14 );
4345 -( EMAC ) two bytes offset from start of receive buffer
4346 AT91C_EMAC_RBOF_OFFSET_3 EQU( 0x3 << 14 );
4347 -( EMAC ) three bytes offset from start of receive buffer
4348 AT91C_EMAC_RLCE EQU( 0x1 << 16 );
4349 -( EMAC ) Receive Length field Checking Enable
4350 AT91C_EMAC_DRFCS EQU( 0x1 << 17 );
4351 -( EMAC ) Discard Receive FCS
4352 AT91C_EMAC_EFRHD EQU( 0x1 << 18 );
4354 AT91C_EMAC_IRXFCS EQU( 0x1 << 19 );
4355 -( EMAC ) Ignore RX FCS
4356 /* - -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- */
4357 AT91C_EMAC_LINKR EQU( 0x1 << 0 );
4359 AT91C_EMAC_MDIO EQU( 0x1 << 1 );
4361 AT91C_EMAC_IDLE EQU( 0x1 << 2 );
4363 /* - -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- */
4364 AT91C_EMAC_UBR EQU( 0x1 << 0 );
4366 AT91C_EMAC_COL EQU( 0x1 << 1 );
4368 AT91C_EMAC_RLES EQU( 0x1 << 2 );
4370 AT91C_EMAC_TGO EQU( 0x1 << 3 );
4371 -( EMAC ) Transmit Go
4372 AT91C_EMAC_BEX EQU( 0x1 << 4 );
4373 -( EMAC ) Buffers exhausted mid frame
4374 AT91C_EMAC_COMP EQU( 0x1 << 5 );
4376 AT91C_EMAC_UND EQU( 0x1 << 6 );
4378 /* - -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- */
4379 AT91C_EMAC_BNA EQU( 0x1 << 0 );
4381 AT91C_EMAC_REC EQU( 0x1 << 1 );
4383 AT91C_EMAC_OVR EQU( 0x1 << 2 );
4385 /* - -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- */
4386 AT91C_EMAC_MFD EQU( 0x1 << 0 );
4388 AT91C_EMAC_RCOMP EQU( 0x1 << 1 );
4390 AT91C_EMAC_RXUBR EQU( 0x1 << 2 );
4392 AT91C_EMAC_TXUBR EQU( 0x1 << 3 );
4394 AT91C_EMAC_TUNDR EQU( 0x1 << 4 );
4396 AT91C_EMAC_RLEX EQU( 0x1 << 5 );
4398 AT91C_EMAC_TXERR EQU( 0x1 << 6 );
4400 AT91C_EMAC_TCOMP EQU( 0x1 << 7 );
4402 AT91C_EMAC_LINK EQU( 0x1 << 9 );
4404 AT91C_EMAC_ROVR EQU( 0x1 << 10 );
4406 AT91C_EMAC_HRESP EQU( 0x1 << 11 );
4408 AT91C_EMAC_PFRE EQU( 0x1 << 12 );
4410 AT91C_EMAC_PTZ EQU( 0x1 << 13 );
4412 /* - -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- */
4413 /* - -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- */
4414 /* - -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- */
4415 /* - -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- */
4416 AT91C_EMAC_DATA EQU( 0xFFFF << 0 );
4418 AT91C_EMAC_CODE EQU( 0x3 << 16 );
4420 AT91C_EMAC_REGA EQU( 0x1F << 18 );
4422 AT91C_EMAC_PHYA EQU( 0x1F << 23 );
4424 AT91C_EMAC_RW EQU( 0x3 << 28 );
4426 AT91C_EMAC_SOF EQU( 0x3 << 30 );
4428 /* - -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- */
4429 AT91C_EMAC_RMII EQU( 0x1 << 0 );
4430 -( EMAC ) Reduce MII
4431 /* - -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- */
4432 AT91C_EMAC_IP EQU( 0xFFFF << 0 );
4433 -( EMAC ) ARP request IP address
4434 AT91C_EMAC_MAG EQU( 0x1 << 16 );
4435 -( EMAC ) Magic packet event enable
4436 AT91C_EMAC_ARP EQU( 0x1 << 17 );
4437 -( EMAC ) ARP request event enable
4438 AT91C_EMAC_SA1 EQU( 0x1 << 18 );
4439 -( EMAC ) Specific address register 1 event enable
4440 /* - -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- */
4441 AT91C_EMAC_REVREF EQU( 0xFFFF << 0 );
4443 AT91C_EMAC_PARTREF EQU( 0xFFFF << 16 );
4446 /* - ***************************************************************************** */
4447 /* - SOFTWARE API DEFINITION FOR Analog to Digital Convertor */
4448 /* - ***************************************************************************** */
4449 /* - -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- */
4450 AT91C_ADC_SWRST EQU( 0x1 << 0 );
4451 -( ADC ) Software Reset
4452 AT91C_ADC_START EQU( 0x1 << 1 );
4453 -( ADC ) Start Conversion
4454 /* - -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- */
4455 AT91C_ADC_TRGEN EQU( 0x1 << 0 );
4456 -( ADC ) Trigger Enable
4457 AT91C_ADC_TRGEN_DIS EQU( 0x0 );
4458 -( ADC ) Hardware triggers are disabled.Starting a conversion is only possible by software
4459 AT91C_ADC_TRGEN_EN EQU( 0x1 );
4460 -( ADC ) Hardware trigger selected by TRGSEL field is enabled.
4461 AT91C_ADC_TRGSEL EQU( 0x7 << 1 );
4462 -( ADC ) Trigger Selection
4463 AT91C_ADC_TRGSEL_TIOA0 EQU( 0x0 << 1 );
4464 -( ADC ) Selected TRGSEL = TIAO0
4465 AT91C_ADC_TRGSEL_TIOA1 EQU( 0x1 << 1 );
4466 -( ADC ) Selected TRGSEL = TIAO1
4467 AT91C_ADC_TRGSEL_TIOA2 EQU( 0x2 << 1 );
4468 -( ADC ) Selected TRGSEL = TIAO2
4469 AT91C_ADC_TRGSEL_TIOA3 EQU( 0x3 << 1 );
4470 -( ADC ) Selected TRGSEL = TIAO3
4471 AT91C_ADC_TRGSEL_TIOA4 EQU( 0x4 << 1 );
4472 -( ADC ) Selected TRGSEL = TIAO4
4473 AT91C_ADC_TRGSEL_TIOA5 EQU( 0x5 << 1 );
4474 -( ADC ) Selected TRGSEL = TIAO5
4475 AT91C_ADC_TRGSEL_EXT EQU( 0x6 << 1 );
4476 -( ADC ) Selected TRGSEL = External Trigger
4477 AT91C_ADC_LOWRES EQU( 0x1 << 4 );
4478 -( ADC ) Resolution.
4479 AT91C_ADC_LOWRES_10_BIT EQU( 0x0 << 4 );
4480 -( ADC ) 10 - bit resolution
4481 AT91C_ADC_LOWRES_8_BIT EQU( 0x1 << 4 );
4482 -( ADC ) 8 - bit resolution
4483 AT91C_ADC_SLEEP EQU( 0x1 << 5 );
4485 AT91C_ADC_SLEEP_NORMAL_MODE EQU( 0x0 << 5 );
4486 -( ADC ) Normal Mode
4487 AT91C_ADC_SLEEP_MODE EQU( 0x1 << 5 );
4489 AT91C_ADC_PRESCAL EQU( 0x3F << 8 );
4490 -( ADC ) Prescaler rate selection
4491 AT91C_ADC_STARTUP EQU( 0x1F << 16 );
4492 -( ADC ) Startup Time
4493 AT91C_ADC_SHTIM EQU( 0xF << 24 );
4494 -( ADC ) Sample & Hold Time
4495 /* - -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- */
4496 AT91C_ADC_CH0 EQU( 0x1 << 0 );
4498 AT91C_ADC_CH1 EQU( 0x1 << 1 );
4500 AT91C_ADC_CH2 EQU( 0x1 << 2 );
4502 AT91C_ADC_CH3 EQU( 0x1 << 3 );
4504 AT91C_ADC_CH4 EQU( 0x1 << 4 );
4506 AT91C_ADC_CH5 EQU( 0x1 << 5 );
4508 AT91C_ADC_CH6 EQU( 0x1 << 6 );
4510 AT91C_ADC_CH7 EQU( 0x1 << 7 );
4512 /* - -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- */
4513 /* - -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- */
4514 /* - -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- */
4515 AT91C_ADC_EOC0 EQU( 0x1 << 0 );
4516 -( ADC ) End of Conversion
4517 AT91C_ADC_EOC1 EQU( 0x1 << 1 );
4518 -( ADC ) End of Conversion
4519 AT91C_ADC_EOC2 EQU( 0x1 << 2 );
4520 -( ADC ) End of Conversion
4521 AT91C_ADC_EOC3 EQU( 0x1 << 3 );
4522 -( ADC ) End of Conversion
4523 AT91C_ADC_EOC4 EQU( 0x1 << 4 );
4524 -( ADC ) End of Conversion
4525 AT91C_ADC_EOC5 EQU( 0x1 << 5 );
4526 -( ADC ) End of Conversion
4527 AT91C_ADC_EOC6 EQU( 0x1 << 6 );
4528 -( ADC ) End of Conversion
4529 AT91C_ADC_EOC7 EQU( 0x1 << 7 );
4530 -( ADC ) End of Conversion
4531 AT91C_ADC_OVRE0 EQU( 0x1 << 8 );
4532 -( ADC ) Overrun Error
4533 AT91C_ADC_OVRE1 EQU( 0x1 << 9 );
4534 -( ADC ) Overrun Error
4535 AT91C_ADC_OVRE2 EQU( 0x1 << 10 );
4536 -( ADC ) Overrun Error
4537 AT91C_ADC_OVRE3 EQU( 0x1 << 11 );
4538 -( ADC ) Overrun Error
4539 AT91C_ADC_OVRE4 EQU( 0x1 << 12 );
4540 -( ADC ) Overrun Error
4541 AT91C_ADC_OVRE5 EQU( 0x1 << 13 );
4542 -( ADC ) Overrun Error
4543 AT91C_ADC_OVRE6 EQU( 0x1 << 14 );
4544 -( ADC ) Overrun Error
4545 AT91C_ADC_OVRE7 EQU( 0x1 << 15 );
4546 -( ADC ) Overrun Error
4547 AT91C_ADC_DRDY EQU( 0x1 << 16 );
4549 AT91C_ADC_GOVRE EQU( 0x1 << 17 );
4550 -( ADC ) General Overrun
4551 AT91C_ADC_ENDRX EQU( 0x1 << 18 );
4552 -( ADC ) End of Receiver Transfer
4553 AT91C_ADC_RXBUFF EQU( 0x1 << 19 );
4554 -( ADC ) RXBUFF Interrupt
4555 /* - -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- */
4556 AT91C_ADC_LDATA EQU( 0x3FF << 0 );
4557 -( ADC ) Last Data Converted
4558 /* - -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- */
4559 /* - -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- */
4560 /* - -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- */
4561 /* - -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- */
4562 AT91C_ADC_DATA EQU( 0x3FF << 0 );
4563 -( ADC ) Converted Data
4564 /* - -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- */
4565 /* - -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- */
4566 /* - -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- */
4567 /* - -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- */
4568 /* - -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- */
4569 /* - -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- */
4570 /* - -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- */
4572 /* - ***************************************************************************** */
4573 /* - SOFTWARE API DEFINITION FOR Advanced Encryption Standard */
4574 /* - ***************************************************************************** */
4575 /* - -------- AES_CR : (AES Offset: 0x0) Control Register -------- */
4576 AT91C_AES_START EQU( 0x1 << 0 );
4577 -( AES ) Starts Processing
4578 AT91C_AES_SWRST EQU( 0x1 << 8 );
4579 -( AES ) Software Reset
4580 AT91C_AES_LOADSEED EQU( 0x1 << 16 );
4581 -( AES ) Random Number Generator Seed Loading
4582 /* - -------- AES_MR : (AES Offset: 0x4) Mode Register -------- */
4583 AT91C_AES_CIPHER EQU( 0x1 << 0 );
4584 -( AES ) Processing Mode
4585 AT91C_AES_PROCDLY EQU( 0xF << 4 );
4586 -( AES ) Processing Delay
4587 AT91C_AES_SMOD EQU( 0x3 << 8 );
4589 AT91C_AES_SMOD_MANUAL EQU( 0x0 << 8 );
4590 -( AES ) Manual Mode:The START bit in register AES_CR must be set to begin encryption or decryption.
4591 AT91C_AES_SMOD_AUTO EQU( 0x1 << 8 );
4592 -( AES ) Auto Mode:no action in AES_CR is necessary( cf datasheet ).
4593 AT91C_AES_SMOD_PDC EQU( 0x2 << 8 );
4594 -( AES ) PDC Mode( cf datasheet ).
4595 AT91C_AES_OPMOD EQU( 0x7 << 12 );
4596 -( AES ) Operation Mode
4597 AT91C_AES_OPMOD_ECB EQU( 0x0 << 12 );
4598 -( AES ) ECB Electronic CodeBook mode.
4599 AT91C_AES_OPMOD_CBC EQU( 0x1 << 12 );
4600 -( AES ) CBC Cipher Block Chaining mode.
4601 AT91C_AES_OPMOD_OFB EQU( 0x2 << 12 );
4602 -( AES ) OFB Output Feedback mode.
4603 AT91C_AES_OPMOD_CFB EQU( 0x3 << 12 );
4604 -( AES ) CFB Cipher Feedback mode.
4605 AT91C_AES_OPMOD_CTR EQU( 0x4 << 12 );
4606 -( AES ) CTR Counter mode.
4607 AT91C_AES_LOD EQU( 0x1 << 15 );
4608 -( AES ) Last Output Data Mode
4609 AT91C_AES_CFBS EQU( 0x7 << 16 );
4610 -( AES ) Cipher Feedback Data Size
4611 AT91C_AES_CFBS_128_BIT EQU( 0x0 << 16 );
4613 AT91C_AES_CFBS_64_BIT EQU( 0x1 << 16 );
4615 AT91C_AES_CFBS_32_BIT EQU( 0x2 << 16 );
4617 AT91C_AES_CFBS_16_BIT EQU( 0x3 << 16 );
4619 AT91C_AES_CFBS_8_BIT EQU( 0x4 << 16 );
4621 AT91C_AES_CKEY EQU( 0xF << 20 );
4622 -( AES ) Countermeasure Key
4623 AT91C_AES_CTYPE EQU( 0x1F << 24 );
4624 -( AES ) Countermeasure Type
4625 AT91C_AES_CTYPE_TYPE1_EN EQU( 0x1 << 24 );
4626 -( AES ) Countermeasure type 1 is enabled.
4627 AT91C_AES_CTYPE_TYPE2_EN EQU( 0x2 << 24 );
4628 -( AES ) Countermeasure type 2 is enabled.
4629 AT91C_AES_CTYPE_TYPE3_EN EQU( 0x4 << 24 );
4630 -( AES ) Countermeasure type 3 is enabled.
4631 AT91C_AES_CTYPE_TYPE4_EN EQU( 0x8 << 24 );
4632 -( AES ) Countermeasure type 4 is enabled.
4633 AT91C_AES_CTYPE_TYPE5_EN EQU( 0x10 << 24 );
4634 -( AES ) Countermeasure type 5 is enabled.
4635 /* - -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- */
4636 AT91C_AES_DATRDY EQU( 0x1 << 0 );
4638 AT91C_AES_ENDRX EQU( 0x1 << 1 );
4639 -( AES ) PDC Read Buffer End
4640 AT91C_AES_ENDTX EQU( 0x1 << 2 );
4641 -( AES ) PDC Write Buffer End
4642 AT91C_AES_RXBUFF EQU( 0x1 << 3 );
4643 -( AES ) PDC Read Buffer Full
4644 AT91C_AES_TXBUFE EQU( 0x1 << 4 );
4645 -( AES ) PDC Write Buffer Empty
4646 AT91C_AES_URAD EQU( 0x1 << 8 );
4647 -( AES ) Unspecified Register Access Detection
4648 /* - -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- */
4649 /* - -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- */
4650 /* - -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- */
4651 AT91C_AES_URAT EQU( 0x7 << 12 );
4652 -( AES ) Unspecified Register Access Type Status
4653 AT91C_AES_URAT_IN_DAT_WRITE_DATPROC EQU( 0x0 << 12 );
4654 -( AES ) Input data register written during the data processing in PDC mode.
4655 AT91C_AES_URAT_OUT_DAT_READ_DATPROC EQU( 0x1 << 12 );
4656 -( AES ) Output data register read during the data processing.
4657 AT91C_AES_URAT_MODEREG_WRITE_DATPROC EQU( 0x2 << 12 );
4658 -( AES ) Mode register written during the data processing.
4659 AT91C_AES_URAT_OUT_DAT_READ_SUBKEY EQU( 0x3 << 12 );
4660 -( AES ) Output data register read during the sub - keys generation.
4661 AT91C_AES_URAT_MODEREG_WRITE_SUBKEY EQU( 0x4 << 12 );
4662 -( AES ) Mode register written during the sub - keys generation.
4663 AT91C_AES_URAT_WO_REG_READ EQU( 0x5 << 12 );
4664 -( AES ) Write - only register read access.
4666 /* - ***************************************************************************** */
4667 /* - SOFTWARE API DEFINITION FOR Triple Data Encryption Standard */
4668 /* - ***************************************************************************** */
4669 /* - -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- */
4670 AT91C_TDES_START EQU( 0x1 << 0 );
4671 -( TDES ) Starts Processing
4672 AT91C_TDES_SWRST EQU( 0x1 << 8 );
4673 -( TDES ) Software Reset
4674 /* - -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- */
4675 AT91C_TDES_CIPHER EQU( 0x1 << 0 );
4676 -( TDES ) Processing Mode
4677 AT91C_TDES_TDESMOD EQU( 0x1 << 1 );
4678 -( TDES ) Single or Triple DES Mode
4679 AT91C_TDES_KEYMOD EQU( 0x1 << 4 );
4681 AT91C_TDES_SMOD EQU( 0x3 << 8 );
4682 -( TDES ) Start Mode
4683 AT91C_TDES_SMOD_MANUAL EQU( 0x0 << 8 );
4684 -( TDES ) Manual Mode:The START bit in register TDES_CR must be set to begin encryption or decryption.
4685 AT91C_TDES_SMOD_AUTO EQU( 0x1 << 8 );
4686 -( TDES ) Auto Mode:no action in TDES_CR is necessary( cf datasheet ).
4687 AT91C_TDES_SMOD_PDC EQU( 0x2 << 8 );
4688 -( TDES ) PDC Mode( cf datasheet ).
4689 AT91C_TDES_OPMOD EQU( 0x3 << 12 );
4690 -( TDES ) Operation Mode
4691 AT91C_TDES_OPMOD_ECB EQU( 0x0 << 12 );
4692 -( TDES ) ECB Electronic CodeBook mode.
4693 AT91C_TDES_OPMOD_CBC EQU( 0x1 << 12 );
4694 -( TDES ) CBC Cipher Block Chaining mode.
4695 AT91C_TDES_OPMOD_OFB EQU( 0x2 << 12 );
4696 -( TDES ) OFB Output Feedback mode.
4697 AT91C_TDES_OPMOD_CFB EQU( 0x3 << 12 );
4698 -( TDES ) CFB Cipher Feedback mode.
4699 AT91C_TDES_LOD EQU( 0x1 << 15 );
4700 -( TDES ) Last Output Data Mode
4701 AT91C_TDES_CFBS EQU( 0x3 << 16 );
4702 -( TDES ) Cipher Feedback Data Size
4703 AT91C_TDES_CFBS_64_BIT EQU( 0x0 << 16 );
4705 AT91C_TDES_CFBS_32_BIT EQU( 0x1 << 16 );
4707 AT91C_TDES_CFBS_16_BIT EQU( 0x2 << 16 );
4709 AT91C_TDES_CFBS_8_BIT EQU( 0x3 << 16 );
4711 /* - -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- */
4712 AT91C_TDES_DATRDY EQU( 0x1 << 0 );
4714 AT91C_TDES_ENDRX EQU( 0x1 << 1 );
4715 -( TDES ) PDC Read Buffer End
4716 AT91C_TDES_ENDTX EQU( 0x1 << 2 );
4717 -( TDES ) PDC Write Buffer End
4718 AT91C_TDES_RXBUFF EQU( 0x1 << 3 );
4719 -( TDES ) PDC Read Buffer Full
4720 AT91C_TDES_TXBUFE EQU( 0x1 << 4 );
4721 -( TDES ) PDC Write Buffer Empty
4722 AT91C_TDES_URAD EQU( 0x1 << 8 );
4723 -( TDES ) Unspecified Register Access Detection
4724 /* - -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- */
4725 /* - -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- */
4726 /* - -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- */
4727 AT91C_TDES_URAT EQU( 0x3 << 12 );
4728 -( TDES ) Unspecified Register Access Type Status
4729 AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC EQU( 0x0 << 12 );
4730 -( TDES ) Input data register written during the data processing in PDC mode.
4731 AT91C_TDES_URAT_OUT_DAT_READ_DATPROC EQU( 0x1 << 12 );
4732 -( TDES ) Output data register read during the data processing.
4733 AT91C_TDES_URAT_MODEREG_WRITE_DATPROC EQU( 0x2 << 12 );
4734 -( TDES ) Mode register written during the data processing.
4735 AT91C_TDES_URAT_WO_REG_READ EQU( 0x3 << 12 );
4736 -( TDES ) Write - only register read access.
4738 /* - ***************************************************************************** */
4739 /* - REGISTER ADDRESS DEFINITION FOR AT91SAM7X256 */
4740 /* - ***************************************************************************** */
4741 /* - ========== Register definition for SYS peripheral ========== */
4742 /* - ========== Register definition for AIC peripheral ========== */
4743 AT91C_AIC_IVR EQU( 0xFFFFF100 );
4744 -( AIC ) IRQ Vector Register
4745 AT91C_AIC_SMR EQU( 0xFFFFF000 );
4746 -( AIC ) Source Mode Register
4747 AT91C_AIC_FVR EQU( 0xFFFFF104 );
4748 -( AIC ) FIQ Vector Register
4749 AT91C_AIC_DCR EQU( 0xFFFFF138 );
4750 -( AIC ) Debug Control Register( Protect )
4751 AT91C_AIC_EOICR EQU( 0xFFFFF130 );
4752 -( AIC ) End of Interrupt Command Register
4753 AT91C_AIC_SVR EQU( 0xFFFFF080 );
4754 -( AIC ) Source Vector Register
4755 AT91C_AIC_FFSR EQU( 0xFFFFF148 );
4756 -( AIC ) Fast Forcing Status Register
4757 AT91C_AIC_ICCR EQU( 0xFFFFF128 );
4758 -( AIC ) Interrupt Clear Command Register
4759 AT91C_AIC_ISR EQU( 0xFFFFF108 );
4760 -( AIC ) Interrupt Status Register
4761 AT91C_AIC_IMR EQU( 0xFFFFF110 );
4762 -( AIC ) Interrupt Mask Register
4763 AT91C_AIC_IPR EQU( 0xFFFFF10C );
4764 -( AIC ) Interrupt Pending Register
4765 AT91C_AIC_FFER EQU( 0xFFFFF140 );
4766 -( AIC ) Fast Forcing Enable Register
4767 AT91C_AIC_IECR EQU( 0xFFFFF120 );
4768 -( AIC ) Interrupt Enable Command Register
4769 AT91C_AIC_ISCR EQU( 0xFFFFF12C );
4770 -( AIC ) Interrupt Set Command Register
4771 AT91C_AIC_FFDR EQU( 0xFFFFF144 );
4772 -( AIC ) Fast Forcing Disable Register
4773 AT91C_AIC_CISR EQU( 0xFFFFF114 );
4774 -( AIC ) Core Interrupt Status Register
4775 AT91C_AIC_IDCR EQU( 0xFFFFF124 );
4776 -( AIC ) Interrupt Disable Command Register
4777 AT91C_AIC_SPU EQU( 0xFFFFF134 );
4778 -( AIC ) Spurious Vector Register
4779 /* - ========== Register definition for PDC_DBGU peripheral ========== */
4780 AT91C_DBGU_TCR EQU( 0xFFFFF30C );
4781 -( PDC_DBGU ) Transmit Counter Register
4782 AT91C_DBGU_RNPR EQU( 0xFFFFF310 );
4783 -( PDC_DBGU ) Receive Next Pointer Register
4784 AT91C_DBGU_TNPR EQU( 0xFFFFF318 );
4785 -( PDC_DBGU ) Transmit Next Pointer Register
4786 AT91C_DBGU_TPR EQU( 0xFFFFF308 );
4787 -( PDC_DBGU ) Transmit Pointer Register
4788 AT91C_DBGU_RPR EQU( 0xFFFFF300 );
4789 -( PDC_DBGU ) Receive Pointer Register
4790 AT91C_DBGU_RCR EQU( 0xFFFFF304 );
4791 -( PDC_DBGU ) Receive Counter Register
4792 AT91C_DBGU_RNCR EQU( 0xFFFFF314 );
4793 -( PDC_DBGU ) Receive Next Counter Register
4794 AT91C_DBGU_PTCR EQU( 0xFFFFF320 );
4795 -( PDC_DBGU ) PDC Transfer Control Register
4796 AT91C_DBGU_PTSR EQU( 0xFFFFF324 );
4797 -( PDC_DBGU ) PDC Transfer Status Register
4798 AT91C_DBGU_TNCR EQU( 0xFFFFF31C );
4799 -( PDC_DBGU ) Transmit Next Counter Register
4800 /* - ========== Register definition for DBGU peripheral ========== */
4801 AT91C_DBGU_EXID EQU( 0xFFFFF244 );
4802 -( DBGU ) Chip ID Extension Register
4803 AT91C_DBGU_BRGR EQU( 0xFFFFF220 );
4804 -( DBGU ) Baud Rate Generator Register
4805 AT91C_DBGU_IDR EQU( 0xFFFFF20C );
4806 -( DBGU ) Interrupt Disable Register
4807 AT91C_DBGU_CSR EQU( 0xFFFFF214 );
4808 -( DBGU ) Channel Status Register
4809 AT91C_DBGU_CIDR EQU( 0xFFFFF240 );
4810 -( DBGU ) Chip ID Register
4811 AT91C_DBGU_MR EQU( 0xFFFFF204 );
4812 -( DBGU ) Mode Register
4813 AT91C_DBGU_IMR EQU( 0xFFFFF210 );
4814 -( DBGU ) Interrupt Mask Register
4815 AT91C_DBGU_CR EQU( 0xFFFFF200 );
4816 -( DBGU ) Control Register
4817 AT91C_DBGU_FNTR EQU( 0xFFFFF248 );
4818 -( DBGU ) Force NTRST Register
4819 AT91C_DBGU_THR EQU( 0xFFFFF21C );
4820 -( DBGU ) Transmitter Holding Register
4821 AT91C_DBGU_RHR EQU( 0xFFFFF218 );
4822 -( DBGU ) Receiver Holding Register
4823 AT91C_DBGU_IER EQU( 0xFFFFF208 );
4824 -( DBGU ) Interrupt Enable Register
4825 /* - ========== Register definition for PIOA peripheral ========== */
4826 AT91C_PIOA_ODR EQU( 0xFFFFF414 );
4827 -( PIOA ) Output Disable Registerr
4828 AT91C_PIOA_SODR EQU( 0xFFFFF430 );
4829 -( PIOA ) Set Output Data Register
4830 AT91C_PIOA_ISR EQU( 0xFFFFF44C );
4831 -( PIOA ) Interrupt Status Register
4832 AT91C_PIOA_ABSR EQU( 0xFFFFF478 );
4833 -( PIOA ) AB Select Status Register
4834 AT91C_PIOA_IER EQU( 0xFFFFF440 );
4835 -( PIOA ) Interrupt Enable Register
4836 AT91C_PIOA_PPUDR EQU( 0xFFFFF460 );
4837 -( PIOA ) Pull - up Disable Register
4838 AT91C_PIOA_IMR EQU( 0xFFFFF448 );
4839 -( PIOA ) Interrupt Mask Register
4840 AT91C_PIOA_PER EQU( 0xFFFFF400 );
4841 -( PIOA ) PIO Enable Register
4842 AT91C_PIOA_IFDR EQU( 0xFFFFF424 );
4843 -( PIOA ) Input Filter Disable Register
4844 AT91C_PIOA_OWDR EQU( 0xFFFFF4A4 );
4845 -( PIOA ) Output Write Disable Register
4846 AT91C_PIOA_MDSR EQU( 0xFFFFF458 );
4847 -( PIOA ) Multi - driver Status Register
4848 AT91C_PIOA_IDR EQU( 0xFFFFF444 );
4849 -( PIOA ) Interrupt Disable Register
4850 AT91C_PIOA_ODSR EQU( 0xFFFFF438 );
4851 -( PIOA ) Output Data Status Register
4852 AT91C_PIOA_PPUSR EQU( 0xFFFFF468 );
4853 -( PIOA ) Pull - up Status Register
4854 AT91C_PIOA_OWSR EQU( 0xFFFFF4A8 );
4855 -( PIOA ) Output Write Status Register
4856 AT91C_PIOA_BSR EQU( 0xFFFFF474 );
4857 -( PIOA ) Select B Register
4858 AT91C_PIOA_OWER EQU( 0xFFFFF4A0 );
4859 -( PIOA ) Output Write Enable Register
4860 AT91C_PIOA_IFER EQU( 0xFFFFF420 );
4861 -( PIOA ) Input Filter Enable Register
4862 AT91C_PIOA_PDSR EQU( 0xFFFFF43C );
4863 -( PIOA ) Pin Data Status Register
4864 AT91C_PIOA_PPUER EQU( 0xFFFFF464 );
4865 -( PIOA ) Pull - up Enable Register
4866 AT91C_PIOA_OSR EQU( 0xFFFFF418 );
4867 -( PIOA ) Output Status Register
4868 AT91C_PIOA_ASR EQU( 0xFFFFF470 );
4869 -( PIOA ) Select A Register
4870 AT91C_PIOA_MDDR EQU( 0xFFFFF454 );
4871 -( PIOA ) Multi - driver Disable Register
4872 AT91C_PIOA_CODR EQU( 0xFFFFF434 );
4873 -( PIOA ) Clear Output Data Register
4874 AT91C_PIOA_MDER EQU( 0xFFFFF450 );
4875 -( PIOA ) Multi - driver Enable Register
4876 AT91C_PIOA_PDR EQU( 0xFFFFF404 );
4877 -( PIOA ) PIO Disable Register
4878 AT91C_PIOA_IFSR EQU( 0xFFFFF428 );
4879 -( PIOA ) Input Filter Status Register
4880 AT91C_PIOA_OER EQU( 0xFFFFF410 );
4881 -( PIOA ) Output Enable Register
4882 AT91C_PIOA_PSR EQU( 0xFFFFF408 );
4883 -( PIOA ) PIO Status Register
4884 /* - ========== Register definition for PIOB peripheral ========== */
4885 AT91C_PIOB_OWDR EQU( 0xFFFFF6A4 );
4886 -( PIOB ) Output Write Disable Register
4887 AT91C_PIOB_MDER EQU( 0xFFFFF650 );
4888 -( PIOB ) Multi - driver Enable Register
4889 AT91C_PIOB_PPUSR EQU( 0xFFFFF668 );
4890 -( PIOB ) Pull - up Status Register
4891 AT91C_PIOB_IMR EQU( 0xFFFFF648 );
4892 -( PIOB ) Interrupt Mask Register
4893 AT91C_PIOB_ASR EQU( 0xFFFFF670 );
4894 -( PIOB ) Select A Register
4895 AT91C_PIOB_PPUDR EQU( 0xFFFFF660 );
4896 -( PIOB ) Pull - up Disable Register
4897 AT91C_PIOB_PSR EQU( 0xFFFFF608 );
4898 -( PIOB ) PIO Status Register
4899 AT91C_PIOB_IER EQU( 0xFFFFF640 );
4900 -( PIOB ) Interrupt Enable Register
4901 AT91C_PIOB_CODR EQU( 0xFFFFF634 );
4902 -( PIOB ) Clear Output Data Register
4903 AT91C_PIOB_OWER EQU( 0xFFFFF6A0 );
4904 -( PIOB ) Output Write Enable Register
4905 AT91C_PIOB_ABSR EQU( 0xFFFFF678 );
4906 -( PIOB ) AB Select Status Register
4907 AT91C_PIOB_IFDR EQU( 0xFFFFF624 );
4908 -( PIOB ) Input Filter Disable Register
4909 AT91C_PIOB_PDSR EQU( 0xFFFFF63C );
4910 -( PIOB ) Pin Data Status Register
4911 AT91C_PIOB_IDR EQU( 0xFFFFF644 );
4912 -( PIOB ) Interrupt Disable Register
4913 AT91C_PIOB_OWSR EQU( 0xFFFFF6A8 );
4914 -( PIOB ) Output Write Status Register
4915 AT91C_PIOB_PDR EQU( 0xFFFFF604 );
4916 -( PIOB ) PIO Disable Register
4917 AT91C_PIOB_ODR EQU( 0xFFFFF614 );
4918 -( PIOB ) Output Disable Registerr
4919 AT91C_PIOB_IFSR EQU( 0xFFFFF628 );
4920 -( PIOB ) Input Filter Status Register
4921 AT91C_PIOB_PPUER EQU( 0xFFFFF664 );
4922 -( PIOB ) Pull - up Enable Register
4923 AT91C_PIOB_SODR EQU( 0xFFFFF630 );
4924 -( PIOB ) Set Output Data Register
4925 AT91C_PIOB_ISR EQU( 0xFFFFF64C );
4926 -( PIOB ) Interrupt Status Register
4927 AT91C_PIOB_ODSR EQU( 0xFFFFF638 );
4928 -( PIOB ) Output Data Status Register
4929 AT91C_PIOB_OSR EQU( 0xFFFFF618 );
4930 -( PIOB ) Output Status Register
4931 AT91C_PIOB_MDSR EQU( 0xFFFFF658 );
4932 -( PIOB ) Multi - driver Status Register
4933 AT91C_PIOB_IFER EQU( 0xFFFFF620 );
4934 -( PIOB ) Input Filter Enable Register
4935 AT91C_PIOB_BSR EQU( 0xFFFFF674 );
4936 -( PIOB ) Select B Register
4937 AT91C_PIOB_MDDR EQU( 0xFFFFF654 );
4938 -( PIOB ) Multi - driver Disable Register
4939 AT91C_PIOB_OER EQU( 0xFFFFF610 );
4940 -( PIOB ) Output Enable Register
4941 AT91C_PIOB_PER EQU( 0xFFFFF600 );
4942 -( PIOB ) PIO Enable Register
4943 /* - ========== Register definition for CKGR peripheral ========== */
4944 AT91C_CKGR_MOR EQU( 0xFFFFFC20 );
4945 -( CKGR ) Main Oscillator Register
4946 AT91C_CKGR_PLLR EQU( 0xFFFFFC2C );
4947 -( CKGR ) PLL Register
4948 AT91C_CKGR_MCFR EQU( 0xFFFFFC24 );
4949 -( CKGR ) Main Clock Frequency Register
4950 /* - ========== Register definition for PMC peripheral ========== */
4951 AT91C_PMC_IDR EQU( 0xFFFFFC64 );
4952 -( PMC ) Interrupt Disable Register
4953 AT91C_PMC_MOR EQU( 0xFFFFFC20 );
4954 -( PMC ) Main Oscillator Register
4955 AT91C_PMC_PLLR EQU( 0xFFFFFC2C );
4956 -( PMC ) PLL Register
4957 AT91C_PMC_PCER EQU( 0xFFFFFC10 );
4958 -( PMC ) Peripheral Clock Enable Register
4959 AT91C_PMC_PCKR EQU( 0xFFFFFC40 );
4960 -( PMC ) Programmable Clock Register
4961 AT91C_PMC_MCKR EQU( 0xFFFFFC30 );
4962 -( PMC ) Master Clock Register
4963 AT91C_PMC_SCDR EQU( 0xFFFFFC04 );
4964 -( PMC ) System Clock Disable Register
4965 AT91C_PMC_PCDR EQU( 0xFFFFFC14 );
4966 -( PMC ) Peripheral Clock Disable Register
4967 AT91C_PMC_SCSR EQU( 0xFFFFFC08 );
4968 -( PMC ) System Clock Status Register
4969 AT91C_PMC_PCSR EQU( 0xFFFFFC18 );
4970 -( PMC ) Peripheral Clock Status Register
4971 AT91C_PMC_MCFR EQU( 0xFFFFFC24 );
4972 -( PMC ) Main Clock Frequency Register
4973 AT91C_PMC_SCER EQU( 0xFFFFFC00 );
4974 -( PMC ) System Clock Enable Register
4975 AT91C_PMC_IMR EQU( 0xFFFFFC6C );
4976 -( PMC ) Interrupt Mask Register
4977 AT91C_PMC_IER EQU( 0xFFFFFC60 );
4978 -( PMC ) Interrupt Enable Register
4979 AT91C_PMC_SR EQU( 0xFFFFFC68 );
4980 -( PMC ) Status Register
4981 /* - ========== Register definition for RSTC peripheral ========== */
4982 AT91C_RSTC_RCR EQU( 0xFFFFFD00 );
4983 -( RSTC ) Reset Control Register
4984 AT91C_RSTC_RMR EQU( 0xFFFFFD08 );
4985 -( RSTC ) Reset Mode Register
4986 AT91C_RSTC_RSR EQU( 0xFFFFFD04 );
4987 -( RSTC ) Reset Status Register
4988 /* - ========== Register definition for RTTC peripheral ========== */
4989 AT91C_RTTC_RTSR EQU( 0xFFFFFD2C );
4990 -( RTTC ) Real - time Status Register
4991 AT91C_RTTC_RTMR EQU( 0xFFFFFD20 );
4992 -( RTTC ) Real - time Mode Register
4993 AT91C_RTTC_RTVR EQU( 0xFFFFFD28 );
4994 -( RTTC ) Real - time Value Register
4995 AT91C_RTTC_RTAR EQU( 0xFFFFFD24 );
4996 -( RTTC ) Real - time Alarm Register
4997 /* - ========== Register definition for PITC peripheral ========== */
4998 AT91C_PITC_PIVR EQU( 0xFFFFFD38 );
4999 -( PITC ) Period Interval Value Register
5000 AT91C_PITC_PISR EQU( 0xFFFFFD34 );
5001 -( PITC ) Period Interval Status Register
5002 AT91C_PITC_PIIR EQU( 0xFFFFFD3C );
5003 -( PITC ) Period Interval Image Register
5004 AT91C_PITC_PIMR EQU( 0xFFFFFD30 );
5005 -( PITC ) Period Interval Mode Register
5006 /* - ========== Register definition for WDTC peripheral ========== */
5007 AT91C_WDTC_WDCR EQU( 0xFFFFFD40 );
5008 -( WDTC ) Watchdog Control Register
5009 AT91C_WDTC_WDSR EQU( 0xFFFFFD48 );
5010 -( WDTC ) Watchdog Status Register
5011 AT91C_WDTC_WDMR EQU( 0xFFFFFD44 );
5012 -( WDTC ) Watchdog Mode Register
5013 /* - ========== Register definition for VREG peripheral ========== */
5014 AT91C_VREG_MR EQU( 0xFFFFFD60 );
5015 -( VREG ) Voltage Regulator Mode Register
5016 /* - ========== Register definition for MC peripheral ========== */
5017 AT91C_MC_ASR EQU( 0xFFFFFF04 );
5018 -( MC ) MC Abort Status Register
5019 AT91C_MC_RCR EQU( 0xFFFFFF00 );
5020 -( MC ) MC Remap Control Register
5021 AT91C_MC_FCR EQU( 0xFFFFFF64 );
5022 -( MC ) MC Flash Command Register
5023 AT91C_MC_AASR EQU( 0xFFFFFF08 );
5024 -( MC ) MC Abort Address Status Register
5025 AT91C_MC_FSR EQU( 0xFFFFFF68 );
5026 -( MC ) MC Flash Status Register
5027 AT91C_MC_FMR EQU( 0xFFFFFF60 );
5028 -( MC ) MC Flash Mode Register
5029 /* - ========== Register definition for PDC_SPI1 peripheral ========== */
5030 AT91C_SPI1_PTCR EQU( 0xFFFE4120 );
5031 -( PDC_SPI1 ) PDC Transfer Control Register
5032 AT91C_SPI1_RPR EQU( 0xFFFE4100 );
5033 -( PDC_SPI1 ) Receive Pointer Register
5034 AT91C_SPI1_TNCR EQU( 0xFFFE411C );
5035 -( PDC_SPI1 ) Transmit Next Counter Register
5036 AT91C_SPI1_TPR EQU( 0xFFFE4108 );
5037 -( PDC_SPI1 ) Transmit Pointer Register
5038 AT91C_SPI1_TNPR EQU( 0xFFFE4118 );
5039 -( PDC_SPI1 ) Transmit Next Pointer Register
5040 AT91C_SPI1_TCR EQU( 0xFFFE410C );
5041 -( PDC_SPI1 ) Transmit Counter Register
5042 AT91C_SPI1_RCR EQU( 0xFFFE4104 );
5043 -( PDC_SPI1 ) Receive Counter Register
5044 AT91C_SPI1_RNPR EQU( 0xFFFE4110 );
5045 -( PDC_SPI1 ) Receive Next Pointer Register
5046 AT91C_SPI1_RNCR EQU( 0xFFFE4114 );
5047 -( PDC_SPI1 ) Receive Next Counter Register
5048 AT91C_SPI1_PTSR EQU( 0xFFFE4124 );
5049 -( PDC_SPI1 ) PDC Transfer Status Register
5050 /* - ========== Register definition for SPI1 peripheral ========== */
5051 AT91C_SPI1_IMR EQU( 0xFFFE401C );
5052 -( SPI1 ) Interrupt Mask Register
5053 AT91C_SPI1_IER EQU( 0xFFFE4014 );
5054 -( SPI1 ) Interrupt Enable Register
5055 AT91C_SPI1_MR EQU( 0xFFFE4004 );
5056 -( SPI1 ) Mode Register
5057 AT91C_SPI1_RDR EQU( 0xFFFE4008 );
5058 -( SPI1 ) Receive Data Register
5059 AT91C_SPI1_IDR EQU( 0xFFFE4018 );
5060 -( SPI1 ) Interrupt Disable Register
5061 AT91C_SPI1_SR EQU( 0xFFFE4010 );
5062 -( SPI1 ) Status Register
5063 AT91C_SPI1_TDR EQU( 0xFFFE400C );
5064 -( SPI1 ) Transmit Data Register
5065 AT91C_SPI1_CR EQU( 0xFFFE4000 );
5066 -( SPI1 ) Control Register
5067 AT91C_SPI1_CSR EQU( 0xFFFE4030 );
5068 -( SPI1 ) Chip Select Register
5069 /* - ========== Register definition for PDC_SPI0 peripheral ========== */
5070 AT91C_SPI0_PTCR EQU( 0xFFFE0120 );
5071 -( PDC_SPI0 ) PDC Transfer Control Register
5072 AT91C_SPI0_TPR EQU( 0xFFFE0108 );
5073 -( PDC_SPI0 ) Transmit Pointer Register
5074 AT91C_SPI0_TCR EQU( 0xFFFE010C );
5075 -( PDC_SPI0 ) Transmit Counter Register
5076 AT91C_SPI0_RCR EQU( 0xFFFE0104 );
5077 -( PDC_SPI0 ) Receive Counter Register
5078 AT91C_SPI0_PTSR EQU( 0xFFFE0124 );
5079 -( PDC_SPI0 ) PDC Transfer Status Register
5080 AT91C_SPI0_RNPR EQU( 0xFFFE0110 );
5081 -( PDC_SPI0 ) Receive Next Pointer Register
5082 AT91C_SPI0_RPR EQU( 0xFFFE0100 );
5083 -( PDC_SPI0 ) Receive Pointer Register
5084 AT91C_SPI0_TNCR EQU( 0xFFFE011C );
5085 -( PDC_SPI0 ) Transmit Next Counter Register
5086 AT91C_SPI0_RNCR EQU( 0xFFFE0114 );
5087 -( PDC_SPI0 ) Receive Next Counter Register
5088 AT91C_SPI0_TNPR EQU( 0xFFFE0118 );
5089 -( PDC_SPI0 ) Transmit Next Pointer Register
5090 /* - ========== Register definition for SPI0 peripheral ========== */
5091 AT91C_SPI0_IER EQU( 0xFFFE0014 );
5092 -( SPI0 ) Interrupt Enable Register
5093 AT91C_SPI0_SR EQU( 0xFFFE0010 );
5094 -( SPI0 ) Status Register
5095 AT91C_SPI0_IDR EQU( 0xFFFE0018 );
5096 -( SPI0 ) Interrupt Disable Register
5097 AT91C_SPI0_CR EQU( 0xFFFE0000 );
5098 -( SPI0 ) Control Register
5099 AT91C_SPI0_MR EQU( 0xFFFE0004 );
5100 -( SPI0 ) Mode Register
5101 AT91C_SPI0_IMR EQU( 0xFFFE001C );
5102 -( SPI0 ) Interrupt Mask Register
5103 AT91C_SPI0_TDR EQU( 0xFFFE000C );
5104 -( SPI0 ) Transmit Data Register
5105 AT91C_SPI0_RDR EQU( 0xFFFE0008 );
5106 -( SPI0 ) Receive Data Register
5107 AT91C_SPI0_CSR EQU( 0xFFFE0030 );
5108 -( SPI0 ) Chip Select Register
5109 /* - ========== Register definition for PDC_US1 peripheral ========== */
5110 AT91C_US1_RNCR EQU( 0xFFFC4114 );
5111 -( PDC_US1 ) Receive Next Counter Register
5112 AT91C_US1_PTCR EQU( 0xFFFC4120 );
5113 -( PDC_US1 ) PDC Transfer Control Register
5114 AT91C_US1_TCR EQU( 0xFFFC410C );
5115 -( PDC_US1 ) Transmit Counter Register
5116 AT91C_US1_PTSR EQU( 0xFFFC4124 );
5117 -( PDC_US1 ) PDC Transfer Status Register
5118 AT91C_US1_TNPR EQU( 0xFFFC4118 );
5119 -( PDC_US1 ) Transmit Next Pointer Register
5120 AT91C_US1_RCR EQU( 0xFFFC4104 );
5121 -( PDC_US1 ) Receive Counter Register
5122 AT91C_US1_RNPR EQU( 0xFFFC4110 );
5123 -( PDC_US1 ) Receive Next Pointer Register
5124 AT91C_US1_RPR EQU( 0xFFFC4100 );
5125 -( PDC_US1 ) Receive Pointer Register
5126 AT91C_US1_TNCR EQU( 0xFFFC411C );
5127 -( PDC_US1 ) Transmit Next Counter Register
5128 AT91C_US1_TPR EQU( 0xFFFC4108 );
5129 -( PDC_US1 ) Transmit Pointer Register
5130 /* - ========== Register definition for US1 peripheral ========== */
5131 AT91C_US1_IF EQU( 0xFFFC404C );
5132 -( US1 ) IRDA_FILTER Register
5133 AT91C_US1_NER EQU( 0xFFFC4044 );
5134 -( US1 ) Nb Errors Register
5135 AT91C_US1_RTOR EQU( 0xFFFC4024 );
5136 -( US1 ) Receiver Time - out Register
5137 AT91C_US1_CSR EQU( 0xFFFC4014 );
5138 -( US1 ) Channel Status Register
5139 AT91C_US1_IDR EQU( 0xFFFC400C );
5140 -( US1 ) Interrupt Disable Register
5141 AT91C_US1_IER EQU( 0xFFFC4008 );
5142 -( US1 ) Interrupt Enable Register
5143 AT91C_US1_THR EQU( 0xFFFC401C );
5144 -( US1 ) Transmitter Holding Register
5145 AT91C_US1_TTGR EQU( 0xFFFC4028 );
5146 -( US1 ) Transmitter Time - guard Register
5147 AT91C_US1_RHR EQU( 0xFFFC4018 );
5148 -( US1 ) Receiver Holding Register
5149 AT91C_US1_BRGR EQU( 0xFFFC4020 );
5150 -( US1 ) Baud Rate Generator Register
5151 AT91C_US1_IMR EQU( 0xFFFC4010 );
5152 -( US1 ) Interrupt Mask Register
5153 AT91C_US1_FIDI EQU( 0xFFFC4040 );
5154 -( US1 ) FI_DI_Ratio Register
5155 AT91C_US1_CR EQU( 0xFFFC4000 );
5156 -( US1 ) Control Register
5157 AT91C_US1_MR EQU( 0xFFFC4004 );
5158 -( US1 ) Mode Register
5159 /* - ========== Register definition for PDC_US0 peripheral ========== */
5160 AT91C_US0_TNPR EQU( 0xFFFC0118 );
5161 -( PDC_US0 ) Transmit Next Pointer Register
5162 AT91C_US0_RNPR EQU( 0xFFFC0110 );
5163 -( PDC_US0 ) Receive Next Pointer Register
5164 AT91C_US0_TCR EQU( 0xFFFC010C );
5165 -( PDC_US0 ) Transmit Counter Register
5166 AT91C_US0_PTCR EQU( 0xFFFC0120 );
5167 -( PDC_US0 ) PDC Transfer Control Register
5168 AT91C_US0_PTSR EQU( 0xFFFC0124 );
5169 -( PDC_US0 ) PDC Transfer Status Register
5170 AT91C_US0_TNCR EQU( 0xFFFC011C );
5171 -( PDC_US0 ) Transmit Next Counter Register
5172 AT91C_US0_TPR EQU( 0xFFFC0108 );
5173 -( PDC_US0 ) Transmit Pointer Register
5174 AT91C_US0_RCR EQU( 0xFFFC0104 );
5175 -( PDC_US0 ) Receive Counter Register
5176 AT91C_US0_RPR EQU( 0xFFFC0100 );
5177 -( PDC_US0 ) Receive Pointer Register
5178 AT91C_US0_RNCR EQU( 0xFFFC0114 );
5179 -( PDC_US0 ) Receive Next Counter Register
5180 /* - ========== Register definition for US0 peripheral ========== */
5181 AT91C_US0_BRGR EQU( 0xFFFC0020 );
5182 -( US0 ) Baud Rate Generator Register
5183 AT91C_US0_NER EQU( 0xFFFC0044 );
5184 -( US0 ) Nb Errors Register
5185 AT91C_US0_CR EQU( 0xFFFC0000 );
5186 -( US0 ) Control Register
5187 AT91C_US0_IMR EQU( 0xFFFC0010 );
5188 -( US0 ) Interrupt Mask Register
5189 AT91C_US0_FIDI EQU( 0xFFFC0040 );
5190 -( US0 ) FI_DI_Ratio Register
5191 AT91C_US0_TTGR EQU( 0xFFFC0028 );
5192 -( US0 ) Transmitter Time - guard Register
5193 AT91C_US0_MR EQU( 0xFFFC0004 );
5194 -( US0 ) Mode Register
5195 AT91C_US0_RTOR EQU( 0xFFFC0024 );
5196 -( US0 ) Receiver Time - out Register
5197 AT91C_US0_CSR EQU( 0xFFFC0014 );
5198 -( US0 ) Channel Status Register
5199 AT91C_US0_RHR EQU( 0xFFFC0018 );
5200 -( US0 ) Receiver Holding Register
5201 AT91C_US0_IDR EQU( 0xFFFC000C );
5202 -( US0 ) Interrupt Disable Register
5203 AT91C_US0_THR EQU( 0xFFFC001C );
5204 -( US0 ) Transmitter Holding Register
5205 AT91C_US0_IF EQU( 0xFFFC004C );
5206 -( US0 ) IRDA_FILTER Register
5207 AT91C_US0_IER EQU( 0xFFFC0008 );
5208 -( US0 ) Interrupt Enable Register
5209 /* - ========== Register definition for PDC_SSC peripheral ========== */
5210 AT91C_SSC_TNCR EQU( 0xFFFD411C );
5211 -( PDC_SSC ) Transmit Next Counter Register
5212 AT91C_SSC_RPR EQU( 0xFFFD4100 );
5213 -( PDC_SSC ) Receive Pointer Register
5214 AT91C_SSC_RNCR EQU( 0xFFFD4114 );
5215 -( PDC_SSC ) Receive Next Counter Register
5216 AT91C_SSC_TPR EQU( 0xFFFD4108 );
5217 -( PDC_SSC ) Transmit Pointer Register
5218 AT91C_SSC_PTCR EQU( 0xFFFD4120 );
5219 -( PDC_SSC ) PDC Transfer Control Register
5220 AT91C_SSC_TCR EQU( 0xFFFD410C );
5221 -( PDC_SSC ) Transmit Counter Register
5222 AT91C_SSC_RCR EQU( 0xFFFD4104 );
5223 -( PDC_SSC ) Receive Counter Register
5224 AT91C_SSC_RNPR EQU( 0xFFFD4110 );
5225 -( PDC_SSC ) Receive Next Pointer Register
5226 AT91C_SSC_TNPR EQU( 0xFFFD4118 );
5227 -( PDC_SSC ) Transmit Next Pointer Register
5228 AT91C_SSC_PTSR EQU( 0xFFFD4124 );
5229 -( PDC_SSC ) PDC Transfer Status Register
5230 /* - ========== Register definition for SSC peripheral ========== */
5231 AT91C_SSC_RHR EQU( 0xFFFD4020 );
5232 -( SSC ) Receive Holding Register
5233 AT91C_SSC_RSHR EQU( 0xFFFD4030 );
5234 -( SSC ) Receive Sync Holding Register
5235 AT91C_SSC_TFMR EQU( 0xFFFD401C );
5236 -( SSC ) Transmit Frame Mode Register
5237 AT91C_SSC_IDR EQU( 0xFFFD4048 );
5238 -( SSC ) Interrupt Disable Register
5239 AT91C_SSC_THR EQU( 0xFFFD4024 );
5240 -( SSC ) Transmit Holding Register
5241 AT91C_SSC_RCMR EQU( 0xFFFD4010 );
5242 -( SSC ) Receive Clock ModeRegister
5243 AT91C_SSC_IER EQU( 0xFFFD4044 );
5244 -( SSC ) Interrupt Enable Register
5245 AT91C_SSC_TSHR EQU( 0xFFFD4034 );
5246 -( SSC ) Transmit Sync Holding Register
5247 AT91C_SSC_SR EQU( 0xFFFD4040 );
5248 -( SSC ) Status Register
5249 AT91C_SSC_CMR EQU( 0xFFFD4004 );
5250 -( SSC ) Clock Mode Register
5251 AT91C_SSC_TCMR EQU( 0xFFFD4018 );
5252 -( SSC ) Transmit Clock Mode Register
5253 AT91C_SSC_CR EQU( 0xFFFD4000 );
5254 -( SSC ) Control Register
5255 AT91C_SSC_IMR EQU( 0xFFFD404C );
5256 -( SSC ) Interrupt Mask Register
5257 AT91C_SSC_RFMR EQU( 0xFFFD4014 );
5258 -( SSC ) Receive Frame Mode Register
5259 /* - ========== Register definition for TWI peripheral ========== */
5260 AT91C_TWI_IER EQU( 0xFFFB8024 );
5261 -( TWI ) Interrupt Enable Register
5262 AT91C_TWI_CR EQU( 0xFFFB8000 );
5263 -( TWI ) Control Register
5264 AT91C_TWI_SR EQU( 0xFFFB8020 );
5265 -( TWI ) Status Register
5266 AT91C_TWI_IMR EQU( 0xFFFB802C );
5267 -( TWI ) Interrupt Mask Register
5268 AT91C_TWI_THR EQU( 0xFFFB8034 );
5269 -( TWI ) Transmit Holding Register
5270 AT91C_TWI_IDR EQU( 0xFFFB8028 );
5271 -( TWI ) Interrupt Disable Register
5272 AT91C_TWI_IADR EQU( 0xFFFB800C );
5273 -( TWI ) Internal Address Register
5274 AT91C_TWI_MMR EQU( 0xFFFB8004 );
5275 -( TWI ) Master Mode Register
5276 AT91C_TWI_CWGR EQU( 0xFFFB8010 );
5277 -( TWI ) Clock Waveform Generator Register
5278 AT91C_TWI_RHR EQU( 0xFFFB8030 );
5279 -( TWI ) Receive Holding Register
5280 /* - ========== Register definition for PWMC_CH3 peripheral ========== */
5281 AT91C_PWMC_CH3_CUPDR EQU( 0xFFFCC270 );
5282 -( PWMC_CH3 ) Channel Update Register
5283 AT91C_PWMC_CH3_Reserved EQU( 0xFFFCC274 );
5284 -( PWMC_CH3 ) Reserved
5285 AT91C_PWMC_CH3_CPRDR EQU( 0xFFFCC268 );
5286 -( PWMC_CH3 ) Channel Period Register
5287 AT91C_PWMC_CH3_CDTYR EQU( 0xFFFCC264 );
5288 -( PWMC_CH3 ) Channel Duty Cycle Register
5289 AT91C_PWMC_CH3_CCNTR EQU( 0xFFFCC26C );
5290 -( PWMC_CH3 ) Channel Counter Register
5291 AT91C_PWMC_CH3_CMR EQU( 0xFFFCC260 );
5292 -( PWMC_CH3 ) Channel Mode Register
5293 /* - ========== Register definition for PWMC_CH2 peripheral ========== */
5294 AT91C_PWMC_CH2_Reserved EQU( 0xFFFCC254 );
5295 -( PWMC_CH2 ) Reserved
5296 AT91C_PWMC_CH2_CMR EQU( 0xFFFCC240 );
5297 -( PWMC_CH2 ) Channel Mode Register
5298 AT91C_PWMC_CH2_CCNTR EQU( 0xFFFCC24C );
5299 -( PWMC_CH2 ) Channel Counter Register
5300 AT91C_PWMC_CH2_CPRDR EQU( 0xFFFCC248 );
5301 -( PWMC_CH2 ) Channel Period Register
5302 AT91C_PWMC_CH2_CUPDR EQU( 0xFFFCC250 );
5303 -( PWMC_CH2 ) Channel Update Register
5304 AT91C_PWMC_CH2_CDTYR EQU( 0xFFFCC244 );
5305 -( PWMC_CH2 ) Channel Duty Cycle Register
5306 /* - ========== Register definition for PWMC_CH1 peripheral ========== */
5307 AT91C_PWMC_CH1_Reserved EQU( 0xFFFCC234 );
5308 -( PWMC_CH1 ) Reserved
5309 AT91C_PWMC_CH1_CUPDR EQU( 0xFFFCC230 );
5310 -( PWMC_CH1 ) Channel Update Register
5311 AT91C_PWMC_CH1_CPRDR EQU( 0xFFFCC228 );
5312 -( PWMC_CH1 ) Channel Period Register
5313 AT91C_PWMC_CH1_CCNTR EQU( 0xFFFCC22C );
5314 -( PWMC_CH1 ) Channel Counter Register
5315 AT91C_PWMC_CH1_CDTYR EQU( 0xFFFCC224 );
5316 -( PWMC_CH1 ) Channel Duty Cycle Register
5317 AT91C_PWMC_CH1_CMR EQU( 0xFFFCC220 );
5318 -( PWMC_CH1 ) Channel Mode Register
5319 /* - ========== Register definition for PWMC_CH0 peripheral ========== */
5320 AT91C_PWMC_CH0_Reserved EQU( 0xFFFCC214 );
5321 -( PWMC_CH0 ) Reserved
5322 AT91C_PWMC_CH0_CPRDR EQU( 0xFFFCC208 );
5323 -( PWMC_CH0 ) Channel Period Register
5324 AT91C_PWMC_CH0_CDTYR EQU( 0xFFFCC204 );
5325 -( PWMC_CH0 ) Channel Duty Cycle Register
5326 AT91C_PWMC_CH0_CMR EQU( 0xFFFCC200 );
5327 -( PWMC_CH0 ) Channel Mode Register
5328 AT91C_PWMC_CH0_CUPDR EQU( 0xFFFCC210 );
5329 -( PWMC_CH0 ) Channel Update Register
5330 AT91C_PWMC_CH0_CCNTR EQU( 0xFFFCC20C );
5331 -( PWMC_CH0 ) Channel Counter Register
5332 /* - ========== Register definition for PWMC peripheral ========== */
5333 AT91C_PWMC_IDR EQU( 0xFFFCC014 );
5334 -( PWMC ) PWMC Interrupt Disable Register
5335 AT91C_PWMC_DIS EQU( 0xFFFCC008 );
5336 -( PWMC ) PWMC Disable Register
5337 AT91C_PWMC_IER EQU( 0xFFFCC010 );
5338 -( PWMC ) PWMC Interrupt Enable Register
5339 AT91C_PWMC_VR EQU( 0xFFFCC0FC );
5340 -( PWMC ) PWMC Version Register
5341 AT91C_PWMC_ISR EQU( 0xFFFCC01C );
5342 -( PWMC ) PWMC Interrupt Status Register
5343 AT91C_PWMC_SR EQU( 0xFFFCC00C );
5344 -( PWMC ) PWMC Status Register
5345 AT91C_PWMC_IMR EQU( 0xFFFCC018 );
5346 -( PWMC ) PWMC Interrupt Mask Register
5347 AT91C_PWMC_MR EQU( 0xFFFCC000 );
5348 -( PWMC ) PWMC Mode Register
5349 AT91C_PWMC_ENA EQU( 0xFFFCC004 );
5350 -( PWMC ) PWMC Enable Register
5351 /* - ========== Register definition for UDP peripheral ========== */
5352 AT91C_UDP_IMR EQU( 0xFFFB0018 );
5353 -( UDP ) Interrupt Mask Register
5354 AT91C_UDP_FADDR EQU( 0xFFFB0008 );
5355 -( UDP ) Function Address Register
5356 AT91C_UDP_NUM EQU( 0xFFFB0000 );
5357 -( UDP ) Frame Number Register
5358 AT91C_UDP_FDR EQU( 0xFFFB0050 );
5359 -( UDP ) Endpoint FIFO Data Register
5360 AT91C_UDP_ISR EQU( 0xFFFB001C );
5361 -( UDP ) Interrupt Status Register
5362 AT91C_UDP_CSR EQU( 0xFFFB0030 );
5363 -( UDP ) Endpoint Control and Status Register
5364 AT91C_UDP_IDR EQU( 0xFFFB0014 );
5365 -( UDP ) Interrupt Disable Register
5366 AT91C_UDP_ICR EQU( 0xFFFB0020 );
5367 -( UDP ) Interrupt Clear Register
5368 AT91C_UDP_RSTEP EQU( 0xFFFB0028 );
5369 -( UDP ) Reset Endpoint Register
5370 AT91C_UDP_TXVC EQU( 0xFFFB0074 );
5371 -( UDP ) Transceiver Control Register
5372 AT91C_UDP_GLBSTATE EQU( 0xFFFB0004 );
5373 -( UDP ) Global State Register
5374 AT91C_UDP_IER EQU( 0xFFFB0010 );
5375 -( UDP ) Interrupt Enable Register
5376 /* - ========== Register definition for TC0 peripheral ========== */
5377 AT91C_TC0_SR EQU( 0xFFFA0020 );
5378 -( TC0 ) Status Register
5379 AT91C_TC0_RC EQU( 0xFFFA001C );
5381 AT91C_TC0_RB EQU( 0xFFFA0018 );
5383 AT91C_TC0_CCR EQU( 0xFFFA0000 );
5384 -( TC0 ) Channel Control Register
5385 AT91C_TC0_CMR EQU( 0xFFFA0004 );
5386 -( TC0 ) Channel Mode Register( Capture Mode / Waveform Mode )
5387 AT91C_TC0_IER EQU( 0xFFFA0024 );
5388 -( TC0 ) Interrupt Enable Register
5389 AT91C_TC0_RA EQU( 0xFFFA0014 );
5391 AT91C_TC0_IDR EQU( 0xFFFA0028 );
5392 -( TC0 ) Interrupt Disable Register
5393 AT91C_TC0_CV EQU( 0xFFFA0010 );
5394 -( TC0 ) Counter Value
5395 AT91C_TC0_IMR EQU( 0xFFFA002C );
5396 -( TC0 ) Interrupt Mask Register
5397 /* - ========== Register definition for TC1 peripheral ========== */
5398 AT91C_TC1_RB EQU( 0xFFFA0058 );
5400 AT91C_TC1_CCR EQU( 0xFFFA0040 );
5401 -( TC1 ) Channel Control Register
5402 AT91C_TC1_IER EQU( 0xFFFA0064 );
5403 -( TC1 ) Interrupt Enable Register
5404 AT91C_TC1_IDR EQU( 0xFFFA0068 );
5405 -( TC1 ) Interrupt Disable Register
5406 AT91C_TC1_SR EQU( 0xFFFA0060 );
5407 -( TC1 ) Status Register
5408 AT91C_TC1_CMR EQU( 0xFFFA0044 );
5409 -( TC1 ) Channel Mode Register( Capture Mode / Waveform Mode )
5410 AT91C_TC1_RA EQU( 0xFFFA0054 );
5412 AT91C_TC1_RC EQU( 0xFFFA005C );
5414 AT91C_TC1_IMR EQU( 0xFFFA006C );
5415 -( TC1 ) Interrupt Mask Register
5416 AT91C_TC1_CV EQU( 0xFFFA0050 );
5417 -( TC1 ) Counter Value
5418 /* - ========== Register definition for TC2 peripheral ========== */
5419 AT91C_TC2_CMR EQU( 0xFFFA0084 );
5420 -( TC2 ) Channel Mode Register( Capture Mode / Waveform Mode )
5421 AT91C_TC2_CCR EQU( 0xFFFA0080 );
5422 -( TC2 ) Channel Control Register
5423 AT91C_TC2_CV EQU( 0xFFFA0090 );
5424 -( TC2 ) Counter Value
5425 AT91C_TC2_RA EQU( 0xFFFA0094 );
5427 AT91C_TC2_RB EQU( 0xFFFA0098 );
5429 AT91C_TC2_IDR EQU( 0xFFFA00A8 );
5430 -( TC2 ) Interrupt Disable Register
5431 AT91C_TC2_IMR EQU( 0xFFFA00AC );
5432 -( TC2 ) Interrupt Mask Register
5433 AT91C_TC2_RC EQU( 0xFFFA009C );
5435 AT91C_TC2_IER EQU( 0xFFFA00A4 );
5436 -( TC2 ) Interrupt Enable Register
5437 AT91C_TC2_SR EQU( 0xFFFA00A0 );
5438 -( TC2 ) Status Register
5439 /* - ========== Register definition for TCB peripheral ========== */
5440 AT91C_TCB_BMR EQU( 0xFFFA00C4 );
5441 -( TCB ) TC Block Mode Register
5442 AT91C_TCB_BCR EQU( 0xFFFA00C0 );
5443 -( TCB ) TC Block Control Register
5444 /* - ========== Register definition for CAN_MB0 peripheral ========== */
5445 AT91C_CAN_MB0_MDL EQU( 0xFFFD0214 );
5446 -( CAN_MB0 ) MailBox Data Low Register
5447 AT91C_CAN_MB0_MAM EQU( 0xFFFD0204 );
5448 -( CAN_MB0 ) MailBox Acceptance Mask Register
5449 AT91C_CAN_MB0_MCR EQU( 0xFFFD021C );
5450 -( CAN_MB0 ) MailBox Control Register
5451 AT91C_CAN_MB0_MID EQU( 0xFFFD0208 );
5452 -( CAN_MB0 ) MailBox ID Register
5453 AT91C_CAN_MB0_MSR EQU( 0xFFFD0210 );
5454 -( CAN_MB0 ) MailBox Status Register
5455 AT91C_CAN_MB0_MFID EQU( 0xFFFD020C );
5456 -( CAN_MB0 ) MailBox Family ID Register
5457 AT91C_CAN_MB0_MDH EQU( 0xFFFD0218 );
5458 -( CAN_MB0 ) MailBox Data High Register
5459 AT91C_CAN_MB0_MMR EQU( 0xFFFD0200 );
5460 -( CAN_MB0 ) MailBox Mode Register
5461 /* - ========== Register definition for CAN_MB1 peripheral ========== */
5462 AT91C_CAN_MB1_MDL EQU( 0xFFFD0234 );
5463 -( CAN_MB1 ) MailBox Data Low Register
5464 AT91C_CAN_MB1_MID EQU( 0xFFFD0228 );
5465 -( CAN_MB1 ) MailBox ID Register
5466 AT91C_CAN_MB1_MMR EQU( 0xFFFD0220 );
5467 -( CAN_MB1 ) MailBox Mode Register
5468 AT91C_CAN_MB1_MSR EQU( 0xFFFD0230 );
5469 -( CAN_MB1 ) MailBox Status Register
5470 AT91C_CAN_MB1_MAM EQU( 0xFFFD0224 );
5471 -( CAN_MB1 ) MailBox Acceptance Mask Register
5472 AT91C_CAN_MB1_MDH EQU( 0xFFFD0238 );
5473 -( CAN_MB1 ) MailBox Data High Register
5474 AT91C_CAN_MB1_MCR EQU( 0xFFFD023C );
5475 -( CAN_MB1 ) MailBox Control Register
5476 AT91C_CAN_MB1_MFID EQU( 0xFFFD022C );
5477 -( CAN_MB1 ) MailBox Family ID Register
5478 /* - ========== Register definition for CAN_MB2 peripheral ========== */
5479 AT91C_CAN_MB2_MCR EQU( 0xFFFD025C );
5480 -( CAN_MB2 ) MailBox Control Register
5481 AT91C_CAN_MB2_MDH EQU( 0xFFFD0258 );
5482 -( CAN_MB2 ) MailBox Data High Register
5483 AT91C_CAN_MB2_MID EQU( 0xFFFD0248 );
5484 -( CAN_MB2 ) MailBox ID Register
5485 AT91C_CAN_MB2_MDL EQU( 0xFFFD0254 );
5486 -( CAN_MB2 ) MailBox Data Low Register
5487 AT91C_CAN_MB2_MMR EQU( 0xFFFD0240 );
5488 -( CAN_MB2 ) MailBox Mode Register
5489 AT91C_CAN_MB2_MAM EQU( 0xFFFD0244 );
5490 -( CAN_MB2 ) MailBox Acceptance Mask Register
5491 AT91C_CAN_MB2_MFID EQU( 0xFFFD024C );
5492 -( CAN_MB2 ) MailBox Family ID Register
5493 AT91C_CAN_MB2_MSR EQU( 0xFFFD0250 );
5494 -( CAN_MB2 ) MailBox Status Register
5495 /* - ========== Register definition for CAN_MB3 peripheral ========== */
5496 AT91C_CAN_MB3_MFID EQU( 0xFFFD026C );
5497 -( CAN_MB3 ) MailBox Family ID Register
5498 AT91C_CAN_MB3_MAM EQU( 0xFFFD0264 );
5499 -( CAN_MB3 ) MailBox Acceptance Mask Register
5500 AT91C_CAN_MB3_MID EQU( 0xFFFD0268 );
5501 -( CAN_MB3 ) MailBox ID Register
5502 AT91C_CAN_MB3_MCR EQU( 0xFFFD027C );
5503 -( CAN_MB3 ) MailBox Control Register
5504 AT91C_CAN_MB3_MMR EQU( 0xFFFD0260 );
5505 -( CAN_MB3 ) MailBox Mode Register
5506 AT91C_CAN_MB3_MSR EQU( 0xFFFD0270 );
5507 -( CAN_MB3 ) MailBox Status Register
5508 AT91C_CAN_MB3_MDL EQU( 0xFFFD0274 );
5509 -( CAN_MB3 ) MailBox Data Low Register
5510 AT91C_CAN_MB3_MDH EQU( 0xFFFD0278 );
5511 -( CAN_MB3 ) MailBox Data High Register
5512 /* - ========== Register definition for CAN_MB4 peripheral ========== */
5513 AT91C_CAN_MB4_MID EQU( 0xFFFD0288 );
5514 -( CAN_MB4 ) MailBox ID Register
5515 AT91C_CAN_MB4_MMR EQU( 0xFFFD0280 );
5516 -( CAN_MB4 ) MailBox Mode Register
5517 AT91C_CAN_MB4_MDH EQU( 0xFFFD0298 );
5518 -( CAN_MB4 ) MailBox Data High Register
5519 AT91C_CAN_MB4_MFID EQU( 0xFFFD028C );
5520 -( CAN_MB4 ) MailBox Family ID Register
5521 AT91C_CAN_MB4_MSR EQU( 0xFFFD0290 );
5522 -( CAN_MB4 ) MailBox Status Register
5523 AT91C_CAN_MB4_MCR EQU( 0xFFFD029C );
5524 -( CAN_MB4 ) MailBox Control Register
5525 AT91C_CAN_MB4_MDL EQU( 0xFFFD0294 );
5526 -( CAN_MB4 ) MailBox Data Low Register
5527 AT91C_CAN_MB4_MAM EQU( 0xFFFD0284 );
5528 -( CAN_MB4 ) MailBox Acceptance Mask Register
5529 /* - ========== Register definition for CAN_MB5 peripheral ========== */
5530 AT91C_CAN_MB5_MSR EQU( 0xFFFD02B0 );
5531 -( CAN_MB5 ) MailBox Status Register
5532 AT91C_CAN_MB5_MCR EQU( 0xFFFD02BC );
5533 -( CAN_MB5 ) MailBox Control Register
5534 AT91C_CAN_MB5_MFID EQU( 0xFFFD02AC );
5535 -( CAN_MB5 ) MailBox Family ID Register
5536 AT91C_CAN_MB5_MDH EQU( 0xFFFD02B8 );
5537 -( CAN_MB5 ) MailBox Data High Register
5538 AT91C_CAN_MB5_MID EQU( 0xFFFD02A8 );
5539 -( CAN_MB5 ) MailBox ID Register
5540 AT91C_CAN_MB5_MMR EQU( 0xFFFD02A0 );
5541 -( CAN_MB5 ) MailBox Mode Register
5542 AT91C_CAN_MB5_MDL EQU( 0xFFFD02B4 );
5543 -( CAN_MB5 ) MailBox Data Low Register
5544 AT91C_CAN_MB5_MAM EQU( 0xFFFD02A4 );
5545 -( CAN_MB5 ) MailBox Acceptance Mask Register
5546 /* - ========== Register definition for CAN_MB6 peripheral ========== */
5547 AT91C_CAN_MB6_MFID EQU( 0xFFFD02CC );
5548 -( CAN_MB6 ) MailBox Family ID Register
5549 AT91C_CAN_MB6_MID EQU( 0xFFFD02C8 );
5550 -( CAN_MB6 ) MailBox ID Register
5551 AT91C_CAN_MB6_MAM EQU( 0xFFFD02C4 );
5552 -( CAN_MB6 ) MailBox Acceptance Mask Register
5553 AT91C_CAN_MB6_MSR EQU( 0xFFFD02D0 );
5554 -( CAN_MB6 ) MailBox Status Register
5555 AT91C_CAN_MB6_MDL EQU( 0xFFFD02D4 );
5556 -( CAN_MB6 ) MailBox Data Low Register
5557 AT91C_CAN_MB6_MCR EQU( 0xFFFD02DC );
5558 -( CAN_MB6 ) MailBox Control Register
5559 AT91C_CAN_MB6_MDH EQU( 0xFFFD02D8 );
5560 -( CAN_MB6 ) MailBox Data High Register
5561 AT91C_CAN_MB6_MMR EQU( 0xFFFD02C0 );
5562 -( CAN_MB6 ) MailBox Mode Register
5563 /* - ========== Register definition for CAN_MB7 peripheral ========== */
5564 AT91C_CAN_MB7_MCR EQU( 0xFFFD02FC );
5565 -( CAN_MB7 ) MailBox Control Register
5566 AT91C_CAN_MB7_MDH EQU( 0xFFFD02F8 );
5567 -( CAN_MB7 ) MailBox Data High Register
5568 AT91C_CAN_MB7_MFID EQU( 0xFFFD02EC );
5569 -( CAN_MB7 ) MailBox Family ID Register
5570 AT91C_CAN_MB7_MDL EQU( 0xFFFD02F4 );
5571 -( CAN_MB7 ) MailBox Data Low Register
5572 AT91C_CAN_MB7_MID EQU( 0xFFFD02E8 );
5573 -( CAN_MB7 ) MailBox ID Register
5574 AT91C_CAN_MB7_MMR EQU( 0xFFFD02E0 );
5575 -( CAN_MB7 ) MailBox Mode Register
5576 AT91C_CAN_MB7_MAM EQU( 0xFFFD02E4 );
5577 -( CAN_MB7 ) MailBox Acceptance Mask Register
5578 AT91C_CAN_MB7_MSR EQU( 0xFFFD02F0 );
5579 -( CAN_MB7 ) MailBox Status Register
5580 /* - ========== Register definition for CAN peripheral ========== */
5581 AT91C_CAN_TCR EQU( 0xFFFD0024 );
5582 -( CAN ) Transfer Command Register
5583 AT91C_CAN_IMR EQU( 0xFFFD000C );
5584 -( CAN ) Interrupt Mask Register
5585 AT91C_CAN_IER EQU( 0xFFFD0004 );
5586 -( CAN ) Interrupt Enable Register
5587 AT91C_CAN_ECR EQU( 0xFFFD0020 );
5588 -( CAN ) Error Counter Register
5589 AT91C_CAN_TIMESTP EQU( 0xFFFD001C );
5590 -( CAN ) Time Stamp Register
5591 AT91C_CAN_MR EQU( 0xFFFD0000 );
5592 -( CAN ) Mode Register
5593 AT91C_CAN_IDR EQU( 0xFFFD0008 );
5594 -( CAN ) Interrupt Disable Register
5595 AT91C_CAN_ACR EQU( 0xFFFD0028 );
5596 -( CAN ) Abort Command Register
5597 AT91C_CAN_TIM EQU( 0xFFFD0018 );
5598 -( CAN ) Timer Register
5599 AT91C_CAN_SR EQU( 0xFFFD0010 );
5600 -( CAN ) Status Register
5601 AT91C_CAN_BR EQU( 0xFFFD0014 );
5602 -( CAN ) Baudrate Register
5603 AT91C_CAN_VR EQU( 0xFFFD00FC );
5604 -( CAN ) Version Register
5605 /* - ========== Register definition for EMAC peripheral ========== */
5606 AT91C_EMAC_ISR EQU( 0xFFFDC024 );
5607 -( EMAC ) Interrupt Status Register
5608 AT91C_EMAC_SA4H EQU( 0xFFFDC0B4 );
5609 -( EMAC ) Specific Address 4 Top, Last 2 bytes
5610 AT91C_EMAC_SA1L EQU( 0xFFFDC098 );
5611 -( EMAC ) Specific Address 1 Bottom, First 4 bytes
5612 AT91C_EMAC_ELE EQU( 0xFFFDC078 );
5613 -( EMAC ) Excessive Length Errors Register
5614 AT91C_EMAC_LCOL EQU( 0xFFFDC05C );
5615 -( EMAC ) Late Collision Register
5616 AT91C_EMAC_RLE EQU( 0xFFFDC088 );
5617 -( EMAC ) Receive Length Field Mismatch Register
5618 AT91C_EMAC_WOL EQU( 0xFFFDC0C4 );
5619 -( EMAC ) Wake On LAN Register
5620 AT91C_EMAC_DTF EQU( 0xFFFDC058 );
5621 -( EMAC ) Deferred Transmission Frame Register
5622 AT91C_EMAC_TUND EQU( 0xFFFDC064 );
5623 -( EMAC ) Transmit Underrun Error Register
5624 AT91C_EMAC_NCR EQU( 0xFFFDC000 );
5625 -( EMAC ) Network Control Register
5626 AT91C_EMAC_SA4L EQU( 0xFFFDC0B0 );
5627 -( EMAC ) Specific Address 4 Bottom, First 4 bytes
5628 AT91C_EMAC_RSR EQU( 0xFFFDC020 );
5629 -( EMAC ) Receive Status Register
5630 AT91C_EMAC_SA3L EQU( 0xFFFDC0A8 );
5631 -( EMAC ) Specific Address 3 Bottom, First 4 bytes
5632 AT91C_EMAC_TSR EQU( 0xFFFDC014 );
5633 -( EMAC ) Transmit Status Register
5634 AT91C_EMAC_IDR EQU( 0xFFFDC02C );
5635 -( EMAC ) Interrupt Disable Register
5636 AT91C_EMAC_RSE EQU( 0xFFFDC074 );
5637 -( EMAC ) Receive Symbol Errors Register
5638 AT91C_EMAC_ECOL EQU( 0xFFFDC060 );
5639 -( EMAC ) Excessive Collision Register
5640 AT91C_EMAC_TID EQU( 0xFFFDC0B8 );
5641 -( EMAC ) Type ID Checking Register
5642 AT91C_EMAC_HRB EQU( 0xFFFDC090 );
5643 -( EMAC ) Hash Address Bottom[ 31 : 0 ]
5644 AT91C_EMAC_TBQP EQU( 0xFFFDC01C );
5645 -( EMAC ) Transmit Buffer Queue Pointer
5646 AT91C_EMAC_USRIO EQU( 0xFFFDC0C0 );
5647 -( EMAC ) USER Input / Output Register
5648 AT91C_EMAC_PTR EQU( 0xFFFDC038 );
5649 -( EMAC ) Pause Time Register
5650 AT91C_EMAC_SA2H EQU( 0xFFFDC0A4 );
5651 -( EMAC ) Specific Address 2 Top, Last 2 bytes
5652 AT91C_EMAC_ROV EQU( 0xFFFDC070 );
5653 -( EMAC ) Receive Overrun Errors Register
5654 AT91C_EMAC_ALE EQU( 0xFFFDC054 );
5655 -( EMAC ) Alignment Error Register
5656 AT91C_EMAC_RJA EQU( 0xFFFDC07C );
5657 -( EMAC ) Receive Jabbers Register
5658 AT91C_EMAC_RBQP EQU( 0xFFFDC018 );
5659 -( EMAC ) Receive Buffer Queue Pointer
5660 AT91C_EMAC_TPF EQU( 0xFFFDC08C );
5661 -( EMAC ) Transmitted Pause Frames Register
5662 AT91C_EMAC_NCFGR EQU( 0xFFFDC004 );
5663 -( EMAC ) Network Configuration Register
5664 AT91C_EMAC_HRT EQU( 0xFFFDC094 );
5665 -( EMAC ) Hash Address Top[ 63 : 32 ]
5666 AT91C_EMAC_USF EQU( 0xFFFDC080 );
5667 -( EMAC ) Undersize Frames Register
5668 AT91C_EMAC_FCSE EQU( 0xFFFDC050 );
5669 -( EMAC ) Frame Check Sequence Error Register
5670 AT91C_EMAC_TPQ EQU( 0xFFFDC0BC );
5671 -( EMAC ) Transmit Pause Quantum Register
5672 AT91C_EMAC_MAN EQU( 0xFFFDC034 );
5673 -( EMAC ) PHY Maintenance Register
5674 AT91C_EMAC_FTO EQU( 0xFFFDC040 );
5675 -( EMAC ) Frames Transmitted OK Register
5676 AT91C_EMAC_REV EQU( 0xFFFDC0FC );
5677 -( EMAC ) Revision Register
5678 AT91C_EMAC_IMR EQU( 0xFFFDC030 );
5679 -( EMAC ) Interrupt Mask Register
5680 AT91C_EMAC_SCF EQU( 0xFFFDC044 );
5681 -( EMAC ) Single Collision Frame Register
5682 AT91C_EMAC_PFR EQU( 0xFFFDC03C );
5683 -( EMAC ) Pause Frames received Register
5684 AT91C_EMAC_MCF EQU( 0xFFFDC048 );
5685 -( EMAC ) Multiple Collision Frame Register
5686 AT91C_EMAC_NSR EQU( 0xFFFDC008 );
5687 -( EMAC ) Network Status Register
5688 AT91C_EMAC_SA2L EQU( 0xFFFDC0A0 );
5689 -( EMAC ) Specific Address 2 Bottom, First 4 bytes
5690 AT91C_EMAC_FRO EQU( 0xFFFDC04C );
5691 -( EMAC ) Frames Received OK Register
5692 AT91C_EMAC_IER EQU( 0xFFFDC028 );
5693 -( EMAC ) Interrupt Enable Register
5694 AT91C_EMAC_SA1H EQU( 0xFFFDC09C );
5695 -( EMAC ) Specific Address 1 Top, Last 2 bytes
5696 AT91C_EMAC_CSE EQU( 0xFFFDC068 );
5697 -( EMAC ) Carrier Sense Error Register
5698 AT91C_EMAC_SA3H EQU( 0xFFFDC0AC );
5699 -( EMAC ) Specific Address 3 Top, Last 2 bytes
5700 AT91C_EMAC_RRE EQU( 0xFFFDC06C );
5701 -( EMAC ) Receive Resource Error Register
5702 AT91C_EMAC_STE EQU( 0xFFFDC084 );
5703 -( EMAC ) SQE Test Error Register
5704 /* - ========== Register definition for PDC_ADC peripheral ========== */
5705 AT91C_ADC_PTSR EQU( 0xFFFD8124 );
5706 -( PDC_ADC ) PDC Transfer Status Register
5707 AT91C_ADC_PTCR EQU( 0xFFFD8120 );
5708 -( PDC_ADC ) PDC Transfer Control Register
5709 AT91C_ADC_TNPR EQU( 0xFFFD8118 );
5710 -( PDC_ADC ) Transmit Next Pointer Register
5711 AT91C_ADC_TNCR EQU( 0xFFFD811C );
5712 -( PDC_ADC ) Transmit Next Counter Register
5713 AT91C_ADC_RNPR EQU( 0xFFFD8110 );
5714 -( PDC_ADC ) Receive Next Pointer Register
5715 AT91C_ADC_RNCR EQU( 0xFFFD8114 );
5716 -( PDC_ADC ) Receive Next Counter Register
5717 AT91C_ADC_RPR EQU( 0xFFFD8100 );
5718 -( PDC_ADC ) Receive Pointer Register
5719 AT91C_ADC_TCR EQU( 0xFFFD810C );
5720 -( PDC_ADC ) Transmit Counter Register
5721 AT91C_ADC_TPR EQU( 0xFFFD8108 );
5722 -( PDC_ADC ) Transmit Pointer Register
5723 AT91C_ADC_RCR EQU( 0xFFFD8104 );
5724 -( PDC_ADC ) Receive Counter Register
5725 /* - ========== Register definition for ADC peripheral ========== */
5726 AT91C_ADC_CDR2 EQU( 0xFFFD8038 );
5727 -( ADC ) ADC Channel Data Register 2
5728 AT91C_ADC_CDR3 EQU( 0xFFFD803C );
5729 -( ADC ) ADC Channel Data Register 3
5730 AT91C_ADC_CDR0 EQU( 0xFFFD8030 );
5731 -( ADC ) ADC Channel Data Register 0
5732 AT91C_ADC_CDR5 EQU( 0xFFFD8044 );
5733 -( ADC ) ADC Channel Data Register 5
5734 AT91C_ADC_CHDR EQU( 0xFFFD8014 );
5735 -( ADC ) ADC Channel Disable Register
5736 AT91C_ADC_SR EQU( 0xFFFD801C );
5737 -( ADC ) ADC Status Register
5738 AT91C_ADC_CDR4 EQU( 0xFFFD8040 );
5739 -( ADC ) ADC Channel Data Register 4
5740 AT91C_ADC_CDR1 EQU( 0xFFFD8034 );
5741 -( ADC ) ADC Channel Data Register 1
5742 AT91C_ADC_LCDR EQU( 0xFFFD8020 );
5743 -( ADC ) ADC Last Converted Data Register
5744 AT91C_ADC_IDR EQU( 0xFFFD8028 );
5745 -( ADC ) ADC Interrupt Disable Register
5746 AT91C_ADC_CR EQU( 0xFFFD8000 );
5747 -( ADC ) ADC Control Register
5748 AT91C_ADC_CDR7 EQU( 0xFFFD804C );
5749 -( ADC ) ADC Channel Data Register 7
5750 AT91C_ADC_CDR6 EQU( 0xFFFD8048 );
5751 -( ADC ) ADC Channel Data Register 6
5752 AT91C_ADC_IER EQU( 0xFFFD8024 );
5753 -( ADC ) ADC Interrupt Enable Register
5754 AT91C_ADC_CHER EQU( 0xFFFD8010 );
5755 -( ADC ) ADC Channel Enable Register
5756 AT91C_ADC_CHSR EQU( 0xFFFD8018 );
5757 -( ADC ) ADC Channel Status Register
5758 AT91C_ADC_MR EQU( 0xFFFD8004 );
5759 -( ADC ) ADC Mode Register
5760 AT91C_ADC_IMR EQU( 0xFFFD802C );
5761 -( ADC ) ADC Interrupt Mask Register
5762 /* - ========== Register definition for PDC_AES peripheral ========== */
5763 AT91C_AES_TPR EQU( 0xFFFA4108 );
5764 -( PDC_AES ) Transmit Pointer Register
5765 AT91C_AES_PTCR EQU( 0xFFFA4120 );
5766 -( PDC_AES ) PDC Transfer Control Register
5767 AT91C_AES_RNPR EQU( 0xFFFA4110 );
5768 -( PDC_AES ) Receive Next Pointer Register
5769 AT91C_AES_TNCR EQU( 0xFFFA411C );
5770 -( PDC_AES ) Transmit Next Counter Register
5771 AT91C_AES_TCR EQU( 0xFFFA410C );
5772 -( PDC_AES ) Transmit Counter Register
5773 AT91C_AES_RCR EQU( 0xFFFA4104 );
5774 -( PDC_AES ) Receive Counter Register
5775 AT91C_AES_RNCR EQU( 0xFFFA4114 );
5776 -( PDC_AES ) Receive Next Counter Register
5777 AT91C_AES_TNPR EQU( 0xFFFA4118 );
5778 -( PDC_AES ) Transmit Next Pointer Register
5779 AT91C_AES_RPR EQU( 0xFFFA4100 );
5780 -( PDC_AES ) Receive Pointer Register
5781 AT91C_AES_PTSR EQU( 0xFFFA4124 );
5782 -( PDC_AES ) PDC Transfer Status Register
5783 /* - ========== Register definition for AES peripheral ========== */
5784 AT91C_AES_IVxR EQU( 0xFFFA4060 );
5785 -( AES ) Initialization Vector x Register
5786 AT91C_AES_MR EQU( 0xFFFA4004 );
5787 -( AES ) Mode Register
5788 AT91C_AES_VR EQU( 0xFFFA40FC );
5789 -( AES ) AES Version Register
5790 AT91C_AES_ODATAxR EQU( 0xFFFA4050 );
5791 -( AES ) Output Data x Register
5792 AT91C_AES_IDATAxR EQU( 0xFFFA4040 );
5793 -( AES ) Input Data x Register
5794 AT91C_AES_CR EQU( 0xFFFA4000 );
5795 -( AES ) Control Register
5796 AT91C_AES_IDR EQU( 0xFFFA4014 );
5797 -( AES ) Interrupt Disable Register
5798 AT91C_AES_IMR EQU( 0xFFFA4018 );
5799 -( AES ) Interrupt Mask Register
5800 AT91C_AES_IER EQU( 0xFFFA4010 );
5801 -( AES ) Interrupt Enable Register
5802 AT91C_AES_KEYWxR EQU( 0xFFFA4020 );
5803 -( AES ) Key Word x Register
5804 AT91C_AES_ISR EQU( 0xFFFA401C );
5805 -( AES ) Interrupt Status Register
5806 /* - ========== Register definition for PDC_TDES peripheral ========== */
5807 AT91C_TDES_RNCR EQU( 0xFFFA8114 );
5808 -( PDC_TDES ) Receive Next Counter Register
5809 AT91C_TDES_TCR EQU( 0xFFFA810C );
5810 -( PDC_TDES ) Transmit Counter Register
5811 AT91C_TDES_RCR EQU( 0xFFFA8104 );
5812 -( PDC_TDES ) Receive Counter Register
5813 AT91C_TDES_TNPR EQU( 0xFFFA8118 );
5814 -( PDC_TDES ) Transmit Next Pointer Register
5815 AT91C_TDES_RNPR EQU( 0xFFFA8110 );
5816 -( PDC_TDES ) Receive Next Pointer Register
5817 AT91C_TDES_RPR EQU( 0xFFFA8100 );
5818 -( PDC_TDES ) Receive Pointer Register
5819 AT91C_TDES_TNCR EQU( 0xFFFA811C );
5820 -( PDC_TDES ) Transmit Next Counter Register
5821 AT91C_TDES_TPR EQU( 0xFFFA8108 );
5822 -( PDC_TDES ) Transmit Pointer Register
5823 AT91C_TDES_PTSR EQU( 0xFFFA8124 );
5824 -( PDC_TDES ) PDC Transfer Status Register
5825 AT91C_TDES_PTCR EQU( 0xFFFA8120 );
5826 -( PDC_TDES ) PDC Transfer Control Register
5827 /* - ========== Register definition for TDES peripheral ========== */
5828 AT91C_TDES_KEY2WxR EQU( 0xFFFA8028 );
5829 -( TDES ) Key 2 Word x Register
5830 AT91C_TDES_KEY3WxR EQU( 0xFFFA8030 );
5831 -( TDES ) Key 3 Word x Register
5832 AT91C_TDES_IDR EQU( 0xFFFA8014 );
5833 -( TDES ) Interrupt Disable Register
5834 AT91C_TDES_VR EQU( 0xFFFA80FC );
5835 -( TDES ) TDES Version Register
5836 AT91C_TDES_IVxR EQU( 0xFFFA8060 );
5837 -( TDES ) Initialization Vector x Register
5838 AT91C_TDES_ODATAxR EQU( 0xFFFA8050 );
5839 -( TDES ) Output Data x Register
5840 AT91C_TDES_IMR EQU( 0xFFFA8018 );
5841 -( TDES ) Interrupt Mask Register
5842 AT91C_TDES_MR EQU( 0xFFFA8004 );
5843 -( TDES ) Mode Register
5844 AT91C_TDES_CR EQU( 0xFFFA8000 );
5845 -( TDES ) Control Register
5846 AT91C_TDES_IER EQU( 0xFFFA8010 );
5847 -( TDES ) Interrupt Enable Register
5848 AT91C_TDES_ISR EQU( 0xFFFA801C );
5849 -( TDES ) Interrupt Status Register
5850 AT91C_TDES_IDATAxR EQU( 0xFFFA8040 );
5851 -( TDES ) Input Data x Register
5852 AT91C_TDES_KEY1WxR EQU( 0xFFFA8020 );
5853 -( TDES ) Key 1 Word x Register
5855 /* - ***************************************************************************** */
5856 /* - PIO DEFINITIONS FOR AT91SAM7X256 */
5857 /* - ***************************************************************************** */
5858 AT91C_PIO_PA0 EQU( 1 << 0 );
5859 -Pin Controlled by PA0
5860 AT91C_PA0_RXD0 EQU( AT91C_PIO_PA0 );
5861 -USART 0 Receive Data
5862 AT91C_PIO_PA1 EQU( 1 << 1 );
5863 -Pin Controlled by PA1
5864 AT91C_PA1_TXD0 EQU( AT91C_PIO_PA1 );
5865 -USART 0 Transmit Data
5866 AT91C_PIO_PA10 EQU( 1 << 10 );
5867 -Pin Controlled by PA10
5868 AT91C_PA10_TWD EQU( AT91C_PIO_PA10 );
5869 -TWI Two - wire Serial Data
5870 AT91C_PIO_PA11 EQU( 1 << 11 );
5871 -Pin Controlled by PA11
5872 AT91C_PA11_TWCK EQU( AT91C_PIO_PA11 );
5873 -TWI Two - wire Serial Clock
5874 AT91C_PIO_PA12 EQU( 1 << 12 );
5875 -Pin Controlled by PA12
5876 AT91C_PA12_NPCS00 EQU( AT91C_PIO_PA12 );
5877 -SPI 0 Peripheral Chip Select 0
5878 AT91C_PIO_PA13 EQU( 1 << 13 );
5879 -Pin Controlled by PA13
5880 AT91C_PA13_NPCS01 EQU( AT91C_PIO_PA13 );
5881 -SPI 0 Peripheral Chip Select 1
5882 AT91C_PA13_PCK1 EQU( AT91C_PIO_PA13 );
5883 -PMC Programmable Clock Output 1
5884 AT91C_PIO_PA14 EQU( 1 << 14 );
5885 -Pin Controlled by PA14
5886 AT91C_PA14_NPCS02 EQU( AT91C_PIO_PA14 );
5887 -SPI 0 Peripheral Chip Select 2
5888 AT91C_PA14_IRQ1 EQU( AT91C_PIO_PA14 );
5889 -External Interrupt 1
5890 AT91C_PIO_PA15 EQU( 1 << 15 );
5891 -Pin Controlled by PA15
5892 AT91C_PA15_NPCS03 EQU( AT91C_PIO_PA15 );
5893 -SPI 0 Peripheral Chip Select 3
5894 AT91C_PA15_TCLK2 EQU( AT91C_PIO_PA15 );
5895 -Timer Counter 2 external clock input
5896 AT91C_PIO_PA16 EQU( 1 << 16 );
5897 -Pin Controlled by PA16
5898 AT91C_PA16_MISO0 EQU( AT91C_PIO_PA16 );
5899 -SPI 0 Master In Slave
5900 AT91C_PIO_PA17 EQU( 1 << 17 );
5901 -Pin Controlled by PA17
5902 AT91C_PA17_MOSI0 EQU( AT91C_PIO_PA17 );
5903 -SPI 0 Master Out Slave
5904 AT91C_PIO_PA18 EQU( 1 << 18 );
5905 -Pin Controlled by PA18
5906 AT91C_PA18_SPCK0 EQU( AT91C_PIO_PA18 );
5908 AT91C_PIO_PA19 EQU( 1 << 19 );
5909 -Pin Controlled by PA19
5910 AT91C_PA19_CANRX EQU( AT91C_PIO_PA19 );
5912 AT91C_PIO_PA2 EQU( 1 << 2 );
5913 -Pin Controlled by PA2
5914 AT91C_PA2_SCK0 EQU( AT91C_PIO_PA2 );
5915 -USART 0 Serial Clock
5916 AT91C_PA2_NPCS11 EQU( AT91C_PIO_PA2 );
5917 -SPI 1 Peripheral Chip Select 1
5918 AT91C_PIO_PA20 EQU( 1 << 20 );
5919 -Pin Controlled by PA20
5920 AT91C_PA20_CANTX EQU( AT91C_PIO_PA20 );
5922 AT91C_PIO_PA21 EQU( 1 << 21 );
5923 -Pin Controlled by PA21
5924 AT91C_PA21_TF EQU( AT91C_PIO_PA21 );
5925 -SSC Transmit Frame Sync
5926 AT91C_PA21_NPCS10 EQU( AT91C_PIO_PA21 );
5927 -SPI 1 Peripheral Chip Select 0
5928 AT91C_PIO_PA22 EQU( 1 << 22 );
5929 -Pin Controlled by PA22
5930 AT91C_PA22_TK EQU( AT91C_PIO_PA22 );
5932 AT91C_PA22_SPCK1 EQU( AT91C_PIO_PA22 );
5934 AT91C_PIO_PA23 EQU( 1 << 23 );
5935 -Pin Controlled by PA23
5936 AT91C_PA23_TD EQU( AT91C_PIO_PA23 );
5938 AT91C_PA23_MOSI1 EQU( AT91C_PIO_PA23 );
5939 -SPI 1 Master Out Slave
5940 AT91C_PIO_PA24 EQU( 1 << 24 );
5941 -Pin Controlled by PA24
5942 AT91C_PA24_RD EQU( AT91C_PIO_PA24 );
5944 AT91C_PA24_MISO1 EQU( AT91C_PIO_PA24 );
5945 -SPI 1 Master In Slave
5946 AT91C_PIO_PA25 EQU( 1 << 25 );
5947 -Pin Controlled by PA25
5948 AT91C_PA25_RK EQU( AT91C_PIO_PA25 );
5950 AT91C_PA25_NPCS11 EQU( AT91C_PIO_PA25 );
5951 -SPI 1 Peripheral Chip Select 1
5952 AT91C_PIO_PA26 EQU( 1 << 26 );
5953 -Pin Controlled by PA26
5954 AT91C_PA26_RF EQU( AT91C_PIO_PA26 );
5955 -SSC Receive Frame Sync
5956 AT91C_PA26_NPCS12 EQU( AT91C_PIO_PA26 );
5957 -SPI 1 Peripheral Chip Select 2
5958 AT91C_PIO_PA27 EQU( 1 << 27 );
5959 -Pin Controlled by PA27
5960 AT91C_PA27_DRXD EQU( AT91C_PIO_PA27 );
5961 -DBGU Debug Receive Data
5962 AT91C_PA27_PCK3 EQU( AT91C_PIO_PA27 );
5963 -PMC Programmable Clock Output 3
5964 AT91C_PIO_PA28 EQU( 1 << 28 );
5965 -Pin Controlled by PA28
5966 AT91C_PA28_DTXD EQU( AT91C_PIO_PA28 );
5967 -DBGU Debug Transmit Data
5968 AT91C_PIO_PA29 EQU( 1 << 29 );
5969 -Pin Controlled by PA29
5970 AT91C_PA29_FIQ EQU( AT91C_PIO_PA29 );
5971 -AIC Fast Interrupt Input
5972 AT91C_PA29_NPCS13 EQU( AT91C_PIO_PA29 );
5973 -SPI 1 Peripheral Chip Select 3
5974 AT91C_PIO_PA3 EQU( 1 << 3 );
5975 -Pin Controlled by PA3
5976 AT91C_PA3_RTS0 EQU( AT91C_PIO_PA3 );
5977 -USART 0 Ready To Send
5978 AT91C_PA3_NPCS12 EQU( AT91C_PIO_PA3 );
5979 -SPI 1 Peripheral Chip Select 2
5980 AT91C_PIO_PA30 EQU( 1 << 30 );
5981 -Pin Controlled by PA30
5982 AT91C_PA30_IRQ0 EQU( AT91C_PIO_PA30 );
5983 -External Interrupt 0
5984 AT91C_PA30_PCK2 EQU( AT91C_PIO_PA30 );
5985 -PMC Programmable Clock Output 2
5986 AT91C_PIO_PA4 EQU( 1 << 4 );
5987 -Pin Controlled by PA4
5988 AT91C_PA4_CTS0 EQU( AT91C_PIO_PA4 );
5989 -USART 0 Clear To Send
5990 AT91C_PA4_NPCS13 EQU( AT91C_PIO_PA4 );
5991 -SPI 1 Peripheral Chip Select 3
5992 AT91C_PIO_PA5 EQU( 1 << 5 );
5993 -Pin Controlled by PA5
5994 AT91C_PA5_RXD1 EQU( AT91C_PIO_PA5 );
5995 -USART 1 Receive Data
5996 AT91C_PIO_PA6 EQU( 1 << 6 );
5997 -Pin Controlled by PA6
5998 AT91C_PA6_TXD1 EQU( AT91C_PIO_PA6 );
5999 -USART 1 Transmit Data
6000 AT91C_PIO_PA7 EQU( 1 << 7 );
6001 -Pin Controlled by PA7
6002 AT91C_PA7_SCK1 EQU( AT91C_PIO_PA7 );
6003 -USART 1 Serial Clock
6004 AT91C_PA7_NPCS01 EQU( AT91C_PIO_PA7 );
6005 -SPI 0 Peripheral Chip Select 1
6006 AT91C_PIO_PA8 EQU( 1 << 8 );
6007 -Pin Controlled by PA8
6008 AT91C_PA8_RTS1 EQU( AT91C_PIO_PA8 );
6009 -USART 1 Ready To Send
6010 AT91C_PA8_NPCS02 EQU( AT91C_PIO_PA8 );
6011 -SPI 0 Peripheral Chip Select 2
6012 AT91C_PIO_PA9 EQU( 1 << 9 );
6013 -Pin Controlled by PA9
6014 AT91C_PA9_CTS1 EQU( AT91C_PIO_PA9 );
6015 -USART 1 Clear To Send
6016 AT91C_PA9_NPCS03 EQU( AT91C_PIO_PA9 );
6017 -SPI 0 Peripheral Chip Select 3
6018 AT91C_PIO_PB0 EQU( 1 << 0 );
6019 -Pin Controlled by PB0
6020 AT91C_PB0_ETXCK_EREFCK EQU( AT91C_PIO_PB0 );
6021 -Ethernet MAC Transmit Clock / Reference Clock
6022 AT91C_PB0_PCK0 EQU( AT91C_PIO_PB0 );
6023 -PMC Programmable Clock Output 0
6024 AT91C_PIO_PB1 EQU( 1 << 1 );
6025 -Pin Controlled by PB1
6026 AT91C_PB1_ETXEN EQU( AT91C_PIO_PB1 );
6027 -Ethernet MAC Transmit Enable
6028 AT91C_PIO_PB10 EQU( 1 << 10 );
6029 -Pin Controlled by PB10
6030 AT91C_PB10_ETX2 EQU( AT91C_PIO_PB10 );
6031 -Ethernet MAC Transmit Data 2
6032 AT91C_PB10_NPCS11 EQU( AT91C_PIO_PB10 );
6033 -SPI 1 Peripheral Chip Select 1
6034 AT91C_PIO_PB11 EQU( 1 << 11 );
6035 -Pin Controlled by PB11
6036 AT91C_PB11_ETX3 EQU( AT91C_PIO_PB11 );
6037 -Ethernet MAC Transmit Data 3
6038 AT91C_PB11_NPCS12 EQU( AT91C_PIO_PB11 );
6039 -SPI 1 Peripheral Chip Select 2
6040 AT91C_PIO_PB12 EQU( 1 << 12 );
6041 -Pin Controlled by PB12
6042 AT91C_PB12_ETXER EQU( AT91C_PIO_PB12 );
6043 -Ethernet MAC Transmit Coding Error
6044 AT91C_PB12_TCLK0 EQU( AT91C_PIO_PB12 );
6045 -Timer Counter 0 external clock input
6046 AT91C_PIO_PB13 EQU( 1 << 13 );
6047 -Pin Controlled by PB13
6048 AT91C_PB13_ERX2 EQU( AT91C_PIO_PB13 );
6049 -Ethernet MAC Receive Data 2
6050 AT91C_PB13_NPCS01 EQU( AT91C_PIO_PB13 );
6051 -SPI 0 Peripheral Chip Select 1
6052 AT91C_PIO_PB14 EQU( 1 << 14 );
6053 -Pin Controlled by PB14
6054 AT91C_PB14_ERX3 EQU( AT91C_PIO_PB14 );
6055 -Ethernet MAC Receive Data 3
6056 AT91C_PB14_NPCS02 EQU( AT91C_PIO_PB14 );
6057 -SPI 0 Peripheral Chip Select 2
6058 AT91C_PIO_PB15 EQU( 1 << 15 );
6059 -Pin Controlled by PB15
6060 AT91C_PB15_ERXDV EQU( AT91C_PIO_PB15 );
6061 -Ethernet MAC Receive Data Valid
6062 AT91C_PIO_PB16 EQU( 1 << 16 );
6063 -Pin Controlled by PB16
6064 AT91C_PB16_ECOL EQU( AT91C_PIO_PB16 );
6065 -Ethernet MAC Collision Detected
6066 AT91C_PB16_NPCS13 EQU( AT91C_PIO_PB16 );
6067 -SPI 1 Peripheral Chip Select 3
6068 AT91C_PIO_PB17 EQU( 1 << 17 );
6069 -Pin Controlled by PB17
6070 AT91C_PB17_ERXCK EQU( AT91C_PIO_PB17 );
6071 -Ethernet MAC Receive Clock
6072 AT91C_PB17_NPCS03 EQU( AT91C_PIO_PB17 );
6073 -SPI 0 Peripheral Chip Select 3
6074 AT91C_PIO_PB18 EQU( 1 << 18 );
6075 -Pin Controlled by PB18
6076 AT91C_PB18_EF100 EQU( AT91C_PIO_PB18 );
6077 -Ethernet MAC Force 100 Mbits / sec
6078 AT91C_PB18_ADTRG EQU( AT91C_PIO_PB18 );
6079 -ADC External Trigger
6080 AT91C_PIO_PB19 EQU( 1 << 19 );
6081 -Pin Controlled by PB19
6082 AT91C_PB19_PWM0 EQU( AT91C_PIO_PB19 );
6084 AT91C_PB19_TCLK1 EQU( AT91C_PIO_PB19 );
6085 -Timer Counter 1 external clock input
6086 AT91C_PIO_PB2 EQU( 1 << 2 );
6087 -Pin Controlled by PB2
6088 AT91C_PB2_ETX0 EQU( AT91C_PIO_PB2 );
6089 -Ethernet MAC Transmit Data 0
6090 AT91C_PIO_PB20 EQU( 1 << 20 );
6091 -Pin Controlled by PB20
6092 AT91C_PB20_PWM1 EQU( AT91C_PIO_PB20 );
6094 AT91C_PB20_PCK0 EQU( AT91C_PIO_PB20 );
6095 -PMC Programmable Clock Output 0
6096 AT91C_PIO_PB21 EQU( 1 << 21 );
6097 -Pin Controlled by PB21
6098 AT91C_PB21_PWM2 EQU( AT91C_PIO_PB21 );
6100 AT91C_PB21_PCK1 EQU( AT91C_PIO_PB21 );
6101 -PMC Programmable Clock Output 1
6102 AT91C_PIO_PB22 EQU( 1 << 22 );
6103 -Pin Controlled by PB22
6104 AT91C_PB22_PWM3 EQU( AT91C_PIO_PB22 );
6106 AT91C_PB22_PCK2 EQU( AT91C_PIO_PB22 );
6107 -PMC Programmable Clock Output 2
6108 AT91C_PIO_PB23 EQU( 1 << 23 );
6109 -Pin Controlled by PB23
6110 AT91C_PB23_TIOA0 EQU( AT91C_PIO_PB23 );
6111 -Timer Counter 0 Multipurpose Timer I / O Pin A
6112 AT91C_PB23_DCD1 EQU( AT91C_PIO_PB23 );
6113 -USART 1 Data Carrier Detect
6114 AT91C_PIO_PB24 EQU( 1 << 24 );
6115 -Pin Controlled by PB24
6116 AT91C_PB24_TIOB0 EQU( AT91C_PIO_PB24 );
6117 -Timer Counter 0 Multipurpose Timer I / O Pin B
6118 AT91C_PB24_DSR1 EQU( AT91C_PIO_PB24 );
6119 -USART 1 Data Set ready
6120 AT91C_PIO_PB25 EQU( 1 << 25 );
6121 -Pin Controlled by PB25
6122 AT91C_PB25_TIOA1 EQU( AT91C_PIO_PB25 );
6123 -Timer Counter 1 Multipurpose Timer I / O Pin A
6124 AT91C_PB25_DTR1 EQU( AT91C_PIO_PB25 );
6125 -USART 1 Data Terminal ready
6126 AT91C_PIO_PB26 EQU( 1 << 26 );
6127 -Pin Controlled by PB26
6128 AT91C_PB26_TIOB1 EQU( AT91C_PIO_PB26 );
6129 -Timer Counter 1 Multipurpose Timer I / O Pin B
6130 AT91C_PB26_RI1 EQU( AT91C_PIO_PB26 );
6131 -USART 1 Ring Indicator
6132 AT91C_PIO_PB27 EQU( 1 << 27 );
6133 -Pin Controlled by PB27
6134 AT91C_PB27_TIOA2 EQU( AT91C_PIO_PB27 );
6135 -Timer Counter 2 Multipurpose Timer I / O Pin A
6136 AT91C_PB27_PWM0 EQU( AT91C_PIO_PB27 );
6138 AT91C_PIO_PB28 EQU( 1 << 28 );
6139 -Pin Controlled by PB28
6140 AT91C_PB28_TIOB2 EQU( AT91C_PIO_PB28 );
6141 -Timer Counter 2 Multipurpose Timer I / O Pin B
6142 AT91C_PB28_PWM1 EQU( AT91C_PIO_PB28 );
6144 AT91C_PIO_PB29 EQU( 1 << 29 );
6145 -Pin Controlled by PB29
6146 AT91C_PB29_PCK1 EQU( AT91C_PIO_PB29 );
6147 -PMC Programmable Clock Output 1
6148 AT91C_PB29_PWM2 EQU( AT91C_PIO_PB29 );
6150 AT91C_PIO_PB3 EQU( 1 << 3 );
6151 -Pin Controlled by PB3
6152 AT91C_PB3_ETX1 EQU( AT91C_PIO_PB3 );
6153 -Ethernet MAC Transmit Data 1
6154 AT91C_PIO_PB30 EQU( 1 << 30 );
6155 -Pin Controlled by PB30
6156 AT91C_PB30_PCK2 EQU( AT91C_PIO_PB30 );
6157 -PMC Programmable Clock Output 2
6158 AT91C_PB30_PWM3 EQU( AT91C_PIO_PB30 );
6160 AT91C_PIO_PB4 EQU( 1 << 4 );
6161 -Pin Controlled by PB4
6162 AT91C_PB4_ECRS_ECRSDV EQU( AT91C_PIO_PB4 );
6163 -Ethernet MAC Carrier Sense / Carrier Sense and Data Valid
6164 AT91C_PIO_PB5 EQU( 1 << 5 );
6165 -Pin Controlled by PB5
6166 AT91C_PB5_ERX0 EQU( AT91C_PIO_PB5 );
6167 -Ethernet MAC Receive Data 0
6168 AT91C_PIO_PB6 EQU( 1 << 6 );
6169 -Pin Controlled by PB6
6170 AT91C_PB6_ERX1 EQU( AT91C_PIO_PB6 );
6171 -Ethernet MAC Receive Data 1
6172 AT91C_PIO_PB7 EQU( 1 << 7 );
6173 -Pin Controlled by PB7
6174 AT91C_PB7_ERXER EQU( AT91C_PIO_PB7 );
6175 -Ethernet MAC Receive Error
6176 AT91C_PIO_PB8 EQU( 1 << 8 );
6177 -Pin Controlled by PB8
6178 AT91C_PB8_EMDC EQU( AT91C_PIO_PB8 );
6179 -Ethernet MAC Management Data Clock
6180 AT91C_PIO_PB9 EQU( 1 << 9 );
6181 -Pin Controlled by PB9
6182 AT91C_PB9_EMDIO EQU( AT91C_PIO_PB9 );
6183 -Ethernet MAC Management Data Input / Output
6185 /* - ***************************************************************************** */
6186 /* - PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256 */
6187 /* - ***************************************************************************** */
6188 AT91C_ID_FIQ EQU( 0 );
6189 -Advanced Interrupt Controller( FIQ )
6190 AT91C_ID_SYS EQU( 1 );
6192 AT91C_ID_PIOA EQU( 2 );
6193 -Parallel IO Controller A
6194 AT91C_ID_PIOB EQU( 3 );
6195 -Parallel IO Controller B
6196 AT91C_ID_SPI0 EQU( 4 );
6197 -Serial Peripheral Interface 0
6198 AT91C_ID_SPI1 EQU( 5 );
6199 -Serial Peripheral Interface 1
6200 AT91C_ID_US0 EQU( 6 );
6202 AT91C_ID_US1 EQU( 7 );
6204 AT91C_ID_SSC EQU( 8 );
6205 -Serial Synchronous Controller
6206 AT91C_ID_TWI EQU( 9 );
6207 -Two - Wire Interface
6208 AT91C_ID_PWMC EQU( 10 );
6210 AT91C_ID_UDP EQU( 11 );
6212 AT91C_ID_TC0 EQU( 12 );
6214 AT91C_ID_TC1 EQU( 13 );
6216 AT91C_ID_TC2 EQU( 14 );
6218 AT91C_ID_CAN EQU( 15 );
6219 -Control Area Network Controller
6220 AT91C_ID_EMAC EQU( 16 );
6222 AT91C_ID_ADC EQU( 17 );
6223 -Analog - to - Digital Converter
6224 AT91C_ID_AES EQU( 18 );
6225 -Advanced Encryption Standard 128 - bit
6226 AT91C_ID_TDES EQU( 19 );
6227 -Triple Data Encryption Standard
6228 AT91C_ID_20_Reserved EQU( 20 );
6230 AT91C_ID_21_Reserved EQU( 21 );
6232 AT91C_ID_22_Reserved EQU( 22 );
6234 AT91C_ID_23_Reserved EQU( 23 );
6236 AT91C_ID_24_Reserved EQU( 24 );
6238 AT91C_ID_25_Reserved EQU( 25 );
6240 AT91C_ID_26_Reserved EQU( 26 );
6242 AT91C_ID_27_Reserved EQU( 27 );
6244 AT91C_ID_28_Reserved EQU( 28 );
6246 AT91C_ID_29_Reserved EQU( 29 );
6248 AT91C_ID_IRQ0 EQU( 30 );
6249 -Advanced Interrupt Controller( IRQ0 )
6250 AT91C_ID_IRQ1 EQU( 31 );
6251 -Advanced Interrupt Controller( IRQ1 )
6253 /* - ***************************************************************************** */
6254 /* - BASE ADDRESS DEFINITIONS FOR AT91SAM7X256 */
6255 /* - ***************************************************************************** */
6256 AT91C_BASE_SYS EQU( 0xFFFFF000 );
6257 -( SYS ) Base Address
6258 AT91C_BASE_AIC EQU( 0xFFFFF000 );
6259 -( AIC ) Base Address
6260 AT91C_BASE_PDC_DBGU EQU( 0xFFFFF300 );
6261 -( PDC_DBGU ) Base Address
6262 AT91C_BASE_DBGU EQU( 0xFFFFF200 );
6263 -( DBGU ) Base Address
6264 AT91C_BASE_PIOA EQU( 0xFFFFF400 );
6265 -( PIOA ) Base Address
6266 AT91C_BASE_PIOB EQU( 0xFFFFF600 );
6267 -( PIOB ) Base Address
6268 AT91C_BASE_CKGR EQU( 0xFFFFFC20 );
6269 -( CKGR ) Base Address
6270 AT91C_BASE_PMC EQU( 0xFFFFFC00 );
6271 -( PMC ) Base Address
6272 AT91C_BASE_RSTC EQU( 0xFFFFFD00 );
6273 -( RSTC ) Base Address
6274 AT91C_BASE_RTTC EQU( 0xFFFFFD20 );
6275 -( RTTC ) Base Address
6276 AT91C_BASE_PITC EQU( 0xFFFFFD30 );
6277 -( PITC ) Base Address
6278 AT91C_BASE_WDTC EQU( 0xFFFFFD40 );
6279 -( WDTC ) Base Address
6280 AT91C_BASE_VREG EQU( 0xFFFFFD60 );
6281 -( VREG ) Base Address
6282 AT91C_BASE_MC EQU( 0xFFFFFF00 );
6283 -( MC ) Base Address
6284 AT91C_BASE_PDC_SPI1 EQU( 0xFFFE4100 );
6285 -( PDC_SPI1 ) Base Address
6286 AT91C_BASE_SPI1 EQU( 0xFFFE4000 );
6287 -( SPI1 ) Base Address
6288 AT91C_BASE_PDC_SPI0 EQU( 0xFFFE0100 );
6289 -( PDC_SPI0 ) Base Address
6290 AT91C_BASE_SPI0 EQU( 0xFFFE0000 );
6291 -( SPI0 ) Base Address
6292 AT91C_BASE_PDC_US1 EQU( 0xFFFC4100 );
6293 -( PDC_US1 ) Base Address
6294 AT91C_BASE_US1 EQU( 0xFFFC4000 );
6295 -( US1 ) Base Address
6296 AT91C_BASE_PDC_US0 EQU( 0xFFFC0100 );
6297 -( PDC_US0 ) Base Address
6298 AT91C_BASE_US0 EQU( 0xFFFC0000 );
6299 -( US0 ) Base Address
6300 AT91C_BASE_PDC_SSC EQU( 0xFFFD4100 );
6301 -( PDC_SSC ) Base Address
6302 AT91C_BASE_SSC EQU( 0xFFFD4000 );
6303 -( SSC ) Base Address
6304 AT91C_BASE_TWI EQU( 0xFFFB8000 );
6305 -( TWI ) Base Address
6306 AT91C_BASE_PWMC_CH3 EQU( 0xFFFCC260 );
6307 -( PWMC_CH3 ) Base Address
6308 AT91C_BASE_PWMC_CH2 EQU( 0xFFFCC240 );
6309 -( PWMC_CH2 ) Base Address
6310 AT91C_BASE_PWMC_CH1 EQU( 0xFFFCC220 );
6311 -( PWMC_CH1 ) Base Address
6312 AT91C_BASE_PWMC_CH0 EQU( 0xFFFCC200 );
6313 -( PWMC_CH0 ) Base Address
6314 AT91C_BASE_PWMC EQU( 0xFFFCC000 );
6315 -( PWMC ) Base Address
6316 AT91C_BASE_UDP EQU( 0xFFFB0000 );
6317 -( UDP ) Base Address
6318 AT91C_BASE_TC0 EQU( 0xFFFA0000 );
6319 -( TC0 ) Base Address
6320 AT91C_BASE_TC1 EQU( 0xFFFA0040 );
6321 -( TC1 ) Base Address
6322 AT91C_BASE_TC2 EQU( 0xFFFA0080 );
6323 -( TC2 ) Base Address
6324 AT91C_BASE_TCB EQU( 0xFFFA0000 );
6325 -( TCB ) Base Address
6326 AT91C_BASE_CAN_MB0 EQU( 0xFFFD0200 );
6327 -( CAN_MB0 ) Base Address
6328 AT91C_BASE_CAN_MB1 EQU( 0xFFFD0220 );
6329 -( CAN_MB1 ) Base Address
6330 AT91C_BASE_CAN_MB2 EQU( 0xFFFD0240 );
6331 -( CAN_MB2 ) Base Address
6332 AT91C_BASE_CAN_MB3 EQU( 0xFFFD0260 );
6333 -( CAN_MB3 ) Base Address
6334 AT91C_BASE_CAN_MB4 EQU( 0xFFFD0280 );
6335 -( CAN_MB4 ) Base Address
6336 AT91C_BASE_CAN_MB5 EQU( 0xFFFD02A0 );
6337 -( CAN_MB5 ) Base Address
6338 AT91C_BASE_CAN_MB6 EQU( 0xFFFD02C0 );
6339 -( CAN_MB6 ) Base Address
6340 AT91C_BASE_CAN_MB7 EQU( 0xFFFD02E0 );
6341 -( CAN_MB7 ) Base Address
6342 AT91C_BASE_CAN EQU( 0xFFFD0000 );
6343 -( CAN ) Base Address
6344 AT91C_BASE_EMAC EQU( 0xFFFDC000 );
6345 -( EMAC ) Base Address
6346 AT91C_BASE_PDC_ADC EQU( 0xFFFD8100 );
6347 -( PDC_ADC ) Base Address
6348 AT91C_BASE_ADC EQU( 0xFFFD8000 );
6349 -( ADC ) Base Address
6350 AT91C_BASE_PDC_AES EQU( 0xFFFA4100 );
6351 -( PDC_AES ) Base Address
6352 AT91C_BASE_AES EQU( 0xFFFA4000 );
6353 -( AES ) Base Address
6354 AT91C_BASE_PDC_TDES EQU( 0xFFFA8100 );
6355 -( PDC_TDES ) Base Address
6356 AT91C_BASE_TDES EQU( 0xFFFA8000 );
6357 -( TDES ) Base Address
6359 /* - ***************************************************************************** */
6360 /* - MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256 */
6361 /* - ***************************************************************************** */
6362 AT91C_ISRAM EQU( 0x00200000 );
6363 -Internal SRAM base address
6364 AT91C_ISRAM_SIZE EQU( 0x00010000 );
6365 -Internal SRAM size in byte( 64 Kbyte )
6366 AT91C_IFLASH EQU( 0x00100000 );
6367 -Internal ROM base address
6368 AT91C_IFLASH_SIZE EQU( 0x00040000 );
6369 -Internal ROM size in byte( 256 Kbyte )
6373 #endif /* AT91SAM7X256_H */
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