begriffs open source - cmsis-freertos/blob - Demo/ARM7_STR71x_IAR/71x

2 ;* File Name : 71x_init.s

3 ;* Author : MCD Application Team

4 ;* Date First Issued : 06/23/2004

5 ;* Description : This is the first code executed after RESET.

6 ;* This code used to initialize system stacks

7 ;* and critical peripherals before entering the C code.

8 ;*******************************************************************************

9 ;* History:

10 ;* 13/01/2006 : V3.1

11 ;* 24/05/2005 : V3.0

12 ;* 30/11/2004 : V2.0

13 ;* 14/07/2004 : V1.3

14 ;* 01/01/2004 : V1.2

15 ;*******************************************************************************

16 ; THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH

17 ; CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.

18 ; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT

19 ; OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT

20 ; OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION

21 ; CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

22 ;*******************************************************************************/

23

24

25 ; --- Standard definitions of mode bits and interrupt (I & F) flags in PSRs

26

27 Mode_USR EQU 0x10

28 Mode_FIQ EQU 0x11

29 Mode_IRQ EQU 0x12

30 Mode_SVC EQU 0x13

31 Mode_ABT EQU 0x17

32 Mode_UNDEF EQU 0x1B

33 Mode_SYS EQU 0x1F ; available on ARM Arch 4 and later

34

35 I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled

36 F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled

37

38

39

40 EIC_Base_addr EQU 0xFFFFF800; EIC base address

41 ICR_off_addr EQU 0x00 ; Interrupt Control register offset

42 CIPR_off_addr EQU 0x08 ; Current Interrupt Priority Register offset

43 IVR_off_addr EQU 0x18 ; Interrupt Vector Register offset

44 FIR_off_addr EQU 0x1C ; Fast Interrupt Register offset

45 IER_off_addr EQU 0x20 ; Interrupt Enable Register offset

46 IPR_off_addr EQU 0x40 ; Interrupt Pending Bit Register offset

47 SIR0_off_addr EQU 0x60 ; Source Interrupt Register 0

48

49 EMI_Base_addr EQU 0x6C000000; EMI base address

50 BCON0_off_addr EQU 0x00 ; Bank 0 configuration register offset

51 BCON1_off_addr EQU 0x04 ; Bank 1 configuration register offset

52 BCON2_off_addr EQU 0x08 ; Bank 2 configuration register offset

53 BCON3_off_addr EQU 0x0C ; Bank 3 configuration register offset

54

55 EMI_ENABLE EQU 0x8000

56 EMI_SIZE_16 EQU 0x0001

57

58 GPIO2_Base_addr EQU 0xE0005000; GPIO2 base address

59 PC0_off_addr EQU 0x00 ; Port Configuration Register 0 offset

60 PC1_off_addr EQU 0x04 ; Port Configuration Register 1 offset

61 PC2_off_addr EQU 0x08 ; Port Configuration Register 2 offset

62 PD_off_addr EQU 0x0C ; Port Data Register offset

63

64 CPM_Base_addr EQU 0xA0000040; CPM Base Address

65 BOOTCR_off_addr EQU 0x10 ; CPM - Boot Configuration Register

66 FLASH_mask EQU 0x0000 ; to remap FLASH at 0x0

67 RAM_mask EQU 0x0002 ; to remap RAM at 0x0

68

69 ;|----------------------------------------------------------------------------------|

70 ;| - APB Bridge (System Peripheral) |

71 ;|----------------------------------------------------------------------------------|

72 APB1_base_addr EQU 0xC0000000 ; APB Bridge1 Base Address

73 APB2_base_addr EQU 0xE0000000 ; APB Bridge2 Base Address

74 CKDIS_off_addr EQU 0x10 ; APB Bridge1 - Clock Disable Register

75 SWRES_off_addr EQU 0x14 ; APB Bridge1 - Software Reset Register

76 CKDIS1_config_all EQU 0x27FB ; To enable/disable clock of all APB1's peripherals

77 SWRES1_config_all EQU 0x27FB ; To reset all APB1's peripherals

78 CKDIS2_config_all EQU 0x7FDD ; To enable/disable clock of all APB2's peripherals

79 SWRES2_config_all EQU 0x7FDD ; To reset all APB2's peripherals

80

81

82

83 ;---------------------------------------------------------------

84 ; ?program_start

85 ;---------------------------------------------------------------

86 MODULE ?program_start

87 SECTION IRQ_STACK:DATA:NOROOT(3)

88 SECTION FIQ_STACK:DATA:NOROOT(3)

89 SECTION UND_STACK:DATA:NOROOT(3)

90 SECTION ABT_STACK:DATA:NOROOT(3)

91 SECTION SVC_STACK:DATA:NOROOT(3)

92 SECTION CSTACK:DATA:NOROOT(3)

93 SECTION .text:CODE(2)

94 PUBLIC __iar_program_start

95 EXTERN ?main

96 EXTERN ?main

97 CODE32

98

99

100 ;*******************************************************************************

101 ;******* -- MACROS -- *******

102 ;*******************************************************************************

103 ;*******************************************************************************

104 ;* Macro Name : EMI_INIT

105 ;* Description : This macro Initialize EMI bank 1: 16-bit 7 wait state

106 ;* Input : None.

107 ;* Output : None.

108 ;*******************************************************************************

109 EMI_INIT MACRO

110 LDR r0, =GPIO2_Base_addr ; Configure P2.0 -> 3 in AF_PP mode

111 LDR r2, [r0, #PC0_off_addr]

112 ORR r2, r2,#0x0000000F

113 STR r2, [r0, #PC0_off_addr]

114 LDR r2, [r0, #PC1_off_addr]

115 ORR r2, r2,#0x0000000F

116 STR r2, [r0, #PC1_off_addr]

117 LDR r2, [r0, #PC2_off_addr]

118 ORR r2, r2,#0x0000000F

119 STR r2, [r0, #PC2_off_addr]

120 LDR r0, =EMI_Base_addr

121 LDR r1, =0x18|EMI_ENABLE|EMI_SIZE_16

122 STR r1, [r0, #BCON1_off_addr] ; Enable bank 1 16-bit 7 wait state

123 ENDM

124 ;*******************************************************************************

125 ;* Macro Name : EIC_INIT

126 ;* Description : This macro Initialize the EIC as following :

127 ; - IRQ disabled

128 ; - FIQ disabled

129 ; - IVR contain the load PC opcode (0xE59FFXXX)

130 ; - Current priority level equal to 0

131 ; - All channels are disabled

132 ; - All channels priority equal to 0

133 ; - All SIR registers contain offset to the related IRQ

134 ; table entry

135 ;* Input : None.

136 ;* Output : None.

137 ;*******************************************************************************

138 EIC_INIT MACRO

139

140 LDR r3, =EIC_Base_addr

141 LDR r4, =0xE59F0000

142 STR r4, [r3, #IVR_off_addr]; Write the LDR pc,[pc,#offset]

143 ; instruction code in IVR[31:16]

144 LDR r2, =32 ; 32 Channel to initialize

145 LDR r0, =T0TIMI_Addr ; Read the address of the IRQs

146 ; address table

147 LDR r1, =0x00000FFF

148 AND r0,r0,r1

149 LDR r5, =SIR0_off_addr ; Read SIR0 address

150 SUB r4,r0,#8 ; subtract 8 for prefetch

151 LDR r1, =0xF7E8 ; Add the offset from IVR to 0x00000000

152 ; address(IVR address + 7E8 = 0x00000000)

153 ; 0xF7E8 used to complete the

154 ; LDR pc,[pc,#offset] opcode (0xE59FFXXX)

155 ADD r1,r4,r1 ; Compute the jump offset from IVR to the

156 ; IRQ table entry.

157 EIC_INI MOV r4, r1, LSL #16 ; Left shift the result

158 STR r4, [r3, r5] ; Store the result in SIRx register

159 ADD r1, r1, #4 ; Next IRQ address

160 ADD r5, r5, #4 ; Next SIR

161 SUBS r2, r2, #1 ; Decrement the number of SIR registers

162 ; to initialize

163 BNE EIC_INI ; If more then continue

164 ENDM

165 ;*******************************************************************************

166 ;* Macro Name : PERIPHERAL_INIT

167 ;* Description : This macro reset all device peripherals.

168 ;* Input : None.

169 ;* Output : None.

170 ;*******************************************************************************

171 PERIPHERAL_INIT MACRO

172

173 LDR r1, =APB1_base_addr ; r0= APB1 base address

174 LDR r2, =APB2_base_addr ; r0= APB2 base address

175 LDR r0, =CKDIS1_config_all

176 STRH r0, [r1, #CKDIS_off_addr]; Clock Disabling for all APB1 peripherals

177 LDR r0, =CKDIS2_config_all

178 STRH r0, [r2, #CKDIS_off_addr]; Clock Disabling for all APB2 peripherals

179 LDR r0, =SWRES1_config_all

180 STRH r0, [r1, #SWRES_off_addr]; Keep all APB1 peripherals under reset

181 LDR r0, =SWRES2_config_all

182 STRH r0, [r2, #SWRES_off_addr]; Keep all APB2 peripherals under reset

183 MOV r7, #10 ; Wait that the selected macrocells exit from reset

184 loop1 SUBS r7, r7, #1

185 BNE loop1

186 MOV r0, #0

187 STRH r0, [r1, #SWRES_off_addr]; Enable all all APB1 peripherals

188 STRH r0, [r2, #SWRES_off_addr]; Enable all all APB2 peripherals

189 STRH r0, [r1, #CKDIS_off_addr]; Clock Enabling for all APB1 peripherals

190 STRH r0, [r2, #CKDIS_off_addr]; Clock Enabling for all APB2 peripherals

191 MOV r7, #10 ; Wait that the selected macrocells exit from reset

192 loop2 SUBS r7, r7, #1

193 BNE loop2

194 ENDM

195 ;********************************************************************************************

196

197 ; define remapping

198 ; If you need to remap memory before entring the main program

199 ; uncomment next ligne

200 ; #define remapping

201

202 ; Then define which memory to remap to address 0x00000000

203 ; Uncomment next line if you want to remap RAM

204 ; #define remap_ram

205

206 ; Uncomment next line if you want to remap FLASH

207 ; #define remap_flash

208

209

210 IMPORT T0TIMI_Addr

211 __iar_program_start

212 LDR pc, =NextInst

213 NextInst

214 NOP ; Wait for OSC stabilization

215 NOP

216 NOP

217 NOP

218 NOP

219 NOP

220 NOP

221 NOP

222 NOP

223

224 MSR CPSR_c, #Mode_ABT|F_Bit|I_Bit

225 ldr sp,=SFE(ABT_STACK) ; End of ABT_STACK

226

227 MSR CPSR_c, #Mode_UNDEF|F_Bit|I_Bit

228 ldr sp,=SFE(UND_STACK) ; End of UNDEF_STACK

229

230 MSR CPSR_c, #Mode_SVC|F_Bit|I_Bit

231 ldr sp,=SFE(SVC_STACK) ; End of SVC_STACK

232

233

234

235 ; Uncomment next ligne if you need to reset all device pripherals

236 ; PERIPHERAL_INIT ; Reset all device peripherals

237

238 ; Uncomment next ligne if you need to enable the EMI Bank 1

239 ; EMI_INIT ; Initialize EIM Bank 1

240

241 ;Uncomment next ligne if you need to initialize the EIC

242 EIC_INIT ; Initialize EIC

243

244 ;******************************************************************************

245 ;REMAPPING

246 ;Description : Remapping memory whether RAM,FLASH

247 ; at Address 0x0 after the application has started executing.

248 ; Remapping is generally done to allow RAM to replace FLASH

249 ; at 0x0.

250 ; the remapping of RAM allow copying of vector table into RAM

251 ; To enable the memory remapping uncomment: (see above)

252 ; #define remapping to enable memory remapping

253 ; AND

254 ; #define remap_ram to remap RAM

255 ; OR

256 ; #define remap_flash to remap FLASH

257 ;******************************************************************************

258 #ifdef remapping

259 #ifdef remap_flash

260 MOV r0, #FLASH_mask

261 #endif

262 #ifdef remap_ram

263 MOV r0, #RAM_mask

264 #endif

265

266 LDR r1, =CPM_Base_addr

267 LDRH r2, [r1, #BOOTCR_off_addr]; Read BOOTCR Register

268 BIC r2, r2, #0x03 ; Reset the two LSB bits of BOOTCR

269 ORR r2, r2, r0 ; change the two LSB bits of BOOTCR

270 STRH r2, [r1, #BOOTCR_off_addr]; Write BOOTCR Register

271 #endif

272

273 MSR CPSR_c, #Mode_FIQ|I_Bit; Change to FIQ mode

274 ldr sp,=SFE(FIQ_STACK) ; End of FIQ_STACK

275

276 MSR CPSR_c, #Mode_IRQ|I_Bit; Change to IRQ mode

277 ldr sp,=SFE(IRQ_STACK) ; End of IRQ_STACK

278

279 MSR CPSR_c, #Mode_SYS ; Change to system mode, Enable IRQ and FIQ

280 ldr sp,=SFE(CSTACK) ; End of CSTACK(user)

281

282

283

284 ; --- Now branches to a C lib function that copies RO data from their

285 ; load region to their execute region, create the RW and ZI regions

286 ; then jumps to user C main program.

287

288 ; main() must be called from Supervisor mode

289 MSR CPSR_c, #Mode_SVC|F_Bit|I_Bit

290

291 b ?main ; Note : use B not BL, because an application will

292 ; never return this way

293

294 LTORG

295

296 END