begriffs open source - cmsis-freertos/blob - Demo/CORTEX_STM32F107_GCC

1 /*

2 * FreeRTOS Kernel V10.1.1

4 *

5 * Permission is hereby granted, free of charge, to any person obtaining a copy of

6 * this software and associated documentation files (the "Software"), to deal in

7 * the Software without restriction, including without limitation the rights to

8 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of

9 * the Software, and to permit persons to whom the Software is furnished to do so,

10 * subject to the following conditions:

11 *

12 * The above copyright notice and this permission notice shall be included in all

13 * copies or substantial portions of the Software.

14 *

15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS

17 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR

18 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER

19 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN

20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.

21 *

22 * http://www.FreeRTOS.org

23 * http://aws.amazon.com/freertos

24 *

25 * 1 tab == 4 spaces!

26 */

27

28 /* FreeRTOS includes. */

29 #include "FreeRTOS.h"

30 #include "semphr.h"

31 #include "task.h"

32 #include "emac.h"

33

34 /* Library includes. */

35 #include "stm32fxxx_eth.h"

36 #include "stm32f10x_gpio.h"

37 #include "stm32f10x_rcc.h"

38 #include "stm32f10x_nvic.h"

39

40 /*-----------------------------------------------------------*/

41

42 /* Hardware specifics. */

43 #define uipRCC_MAC_CLOCK ( 1UL << 14UL )

44 #define uipRCC_MAC_TX_CLOCK ( 1UL << 15UL )

45 #define uipRCC_MAC_RX_CLOCK ( 1UL << 16UL )

46 #define uipPHY_ADDRESS ( 1 )

47 #define uipENET_IRQ_NUM ( 61 )

48 #define uipMODE_MII ( 1UL << 23UL )

49 #define uipREMAP_MAC_IO ( 1UL << 21UL )

50

51 /* The number of descriptors to chain together for use by the Rx DMA. */

52 #define uipNUM_RX_DESCRIPTORS 4

53

54 /* The total number of buffers to be available. At most (?) there should be

55 one available for each Rx descriptor, one for current use, and one that is

56 in the process of being transmitted. */

57 #define uipNUM_BUFFERS ( uipNUM_RX_DESCRIPTORS + 2 )

58

59 /* Each buffer is sized to fit an entire Ethernet packet. This is for

60 simplicity and speed, but could waste RAM. */

61 #define uipMAX_PACKET_SIZE 1520

62

63 /* The field in the descriptor that is unused by this configuration is used to

64 hold the send count. This is just #defined to a meaningful name. */

65 #define SendCount Buffer2NextDescAddr

66

67 /* If no buffers are available, then wait this long before looking again.... */

68 #define uipBUFFER_WAIT_DELAY ( 3 / portTICK_RATE_MS )

69

70 /* ...and don't look more than this many times. */

71 #define uipBUFFER_WAIT_ATTEMPTS ( 30 )

72

73 /* Let the DMA know that a new descriptor has been made available to it. */

74 #define prvRxDescriptorAvailable() ETH_DMA->DMARPDR = 0

75

76 /*-----------------------------------------------------------*/

77

78 /*

79 * Configure the IO for Ethernet use.

80 */

81 static void prvSetupEthGPIO( void );

82

83 /*

84 * Return a pointer to an unused buffer, marking the returned buffer as now

85 * in use.

86 */

87 static unsigned char *prvGetNextBuffer( void );

88

89 /*-----------------------------------------------------------*/

90

91 /* Allocate the Rx descriptors used by the DMA. */

92 static ETH_DMADESCTypeDef xRxDescriptors[ uipNUM_RX_DESCRIPTORS ] __attribute__((aligned(4)));

93

94 /* Allocate the descriptor used for transmitting. It might be that better

95 performance could be achieved by having more than one Tx descriptor, but

96 in this simple case only one is used. */

97 static volatile ETH_DMADESCTypeDef xTxDescriptor __attribute__((aligned(4)));

98

99 /* Buffers used for receiving and transmitting data. */

100 static unsigned char ucMACBuffers[ uipNUM_BUFFERS ][ uipMAX_PACKET_SIZE ] __attribute__((aligned(4)));

101

102 /* Each ucBufferInUse index corresponds to a position in the same index in the

103 ucMACBuffers array. If the index contains a 1 then the buffer within

104 ucMACBuffers is in use, if it contains a 0 then the buffer is free. */

105 static unsigned char ucBufferInUse[ uipNUM_BUFFERS ] = { 0 };

106

107 /* Index to the Rx descriptor to inspect next when looking for a received

108 packet. */

109 static unsigned long ulNextDescriptor;

110

111 /* The uip_buffer is not a fixed array, but instead gets pointed to the buffers

112 allocated within this file. */

113 extern unsigned char * uip_buf;

114

115 /*-----------------------------------------------------------*/

116

117 portBASE_TYPE xEthInitialise( void )

118 {

119 static ETH_InitTypeDef xEthInit; /* Static so as not to take up too much stack space. */

120 NVIC_InitTypeDef xNVICInit;

121 const unsigned char ucMACAddress[] = { configMAC_ADDR0, configMAC_ADDR1, configMAC_ADDR2, configMAC_ADDR3, configMAC_ADDR4, configMAC_ADDR5 };

122 portBASE_TYPE xReturn;

123 unsigned long ul;

124

125 /* Start with things in a safe known state. */

126 ETH_DeInit();

127 for( ul = 0; ul < uipNUM_RX_DESCRIPTORS; ul++ )

128 {

129 ETH_DMARxDescReceiveITConfig( &( xRxDescriptors[ ul ] ), DISABLE );

130 }

131

132 /* Route clock to the peripheral. */

133 RCC->AHBENR |= ( uipRCC_MAC_CLOCK | uipRCC_MAC_TX_CLOCK | uipRCC_MAC_RX_CLOCK );

134

135 /* Set the MAC address. */

136 ETH_MACAddressConfig( ETH_MAC_Address0, ( unsigned char * ) ucMACAddress );

137

138 /* Use MII mode. */

139 AFIO->MAPR &= ~( uipMODE_MII );

140

141 /* Configure all the GPIO as required for MAC/PHY interfacing. */

142 prvSetupEthGPIO();

143

144 /* Reset the peripheral. */

145 ETH_SoftwareReset();

146 while( ETH_GetSoftwareResetStatus() == SET );

147

148 /* Initialise using the whopping big structure. Code space could be saved

149 by making this a const struct, however that would mean changes to the

150 structure within the library header files could break the code, so for now

151 just set everything manually at run time. */

152 xEthInit.ETH_AutoNegotiation = ETH_AutoNegotiation_Enable;

153 xEthInit.ETH_Watchdog = ETH_Watchdog_Disable;

154 xEthInit.ETH_Jabber = ETH_Jabber_Disable;

155 xEthInit.ETH_JumboFrame = ETH_JumboFrame_Disable;

156 xEthInit.ETH_InterFrameGap = ETH_InterFrameGap_96Bit;

157 xEthInit.ETH_CarrierSense = ETH_CarrierSense_Enable;

158 xEthInit.ETH_Speed = ETH_Speed_10M;

159 xEthInit.ETH_ReceiveOwn = ETH_ReceiveOwn_Disable;

160 xEthInit.ETH_LoopbackMode = ETH_LoopbackMode_Disable;

161 xEthInit.ETH_Mode = ETH_Mode_HalfDuplex;

162 xEthInit.ETH_ChecksumOffload = ETH_ChecksumOffload_Disable;

163 xEthInit.ETH_RetryTransmission = ETH_RetryTransmission_Disable;

164 xEthInit.ETH_AutomaticPadCRCStrip = ETH_AutomaticPadCRCStrip_Disable;

165 xEthInit.ETH_BackOffLimit = ETH_BackOffLimit_10;

166 xEthInit.ETH_DeferralCheck = ETH_DeferralCheck_Disable;

167 xEthInit.ETH_ReceiveAll = ETH_ReceiveAll_Enable;

168 xEthInit.ETH_SourceAddrFilter = ETH_SourceAddrFilter_Disable;

169 xEthInit.ETH_PassControlFrames = ETH_PassControlFrames_ForwardPassedAddrFilter;

170 xEthInit.ETH_BroadcastFramesReception = ETH_BroadcastFramesReception_Disable;

171 xEthInit.ETH_DestinationAddrFilter = ETH_DestinationAddrFilter_Normal;

172 xEthInit.ETH_PromiscuousMode = ETH_PromiscuousMode_Disable;

173 xEthInit.ETH_MulticastFramesFilter = ETH_MulticastFramesFilter_Perfect;

174 xEthInit.ETH_UnicastFramesFilter = ETH_UnicastFramesFilter_Perfect;

175 xEthInit.ETH_HashTableHigh = 0x0;

176 xEthInit.ETH_HashTableLow = 0x0;

177 xEthInit.ETH_PauseTime = 0x0;

178 xEthInit.ETH_ZeroQuantaPause = ETH_ZeroQuantaPause_Disable;

179 xEthInit.ETH_PauseLowThreshold = ETH_PauseLowThreshold_Minus4;

180 xEthInit.ETH_UnicastPauseFrameDetect = ETH_UnicastPauseFrameDetect_Disable;

181 xEthInit.ETH_ReceiveFlowControl = ETH_ReceiveFlowControl_Disable;

182 xEthInit.ETH_TransmitFlowControl = ETH_TransmitFlowControl_Disable;

183 xEthInit.ETH_VLANTagComparison = ETH_VLANTagComparison_16Bit;

184 xEthInit.ETH_VLANTagIdentifier = 0x0;

185 xEthInit.ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Disable;

186 xEthInit.ETH_ReceiveStoreForward = ETH_ReceiveStoreForward_Enable;

187 xEthInit.ETH_FlushReceivedFrame = ETH_FlushReceivedFrame_Disable;

188 xEthInit.ETH_TransmitStoreForward = ETH_TransmitStoreForward_Enable;

189 xEthInit.ETH_TransmitThresholdControl = ETH_TransmitThresholdControl_64Bytes;

190 xEthInit.ETH_ForwardErrorFrames = ETH_ForwardErrorFrames_Disable;

191 xEthInit.ETH_ForwardUndersizedGoodFrames = ETH_ForwardUndersizedGoodFrames_Disable;

192 xEthInit.ETH_ReceiveThresholdControl = ETH_ReceiveThresholdControl_64Bytes;

193 xEthInit.ETH_SecondFrameOperate = ETH_SecondFrameOperate_Disable;

194 xEthInit.ETH_AddressAlignedBeats = ETH_AddressAlignedBeats_Enable;

195 xEthInit.ETH_FixedBurst = ETH_FixedBurst_Disable;

196 xEthInit.ETH_RxDMABurstLength = ETH_RxDMABurstLength_1Beat;

197 xEthInit.ETH_TxDMABurstLength = ETH_TxDMABurstLength_1Beat;

198 xEthInit.ETH_DescriptorSkipLength = 0x0;

199 xEthInit.ETH_DMAArbitration = ETH_DMAArbitration_RoundRobin_RxTx_1_1;

200

201 xReturn = ETH_Init( &xEthInit, uipPHY_ADDRESS );

202

203 /* Check a link was established. */

204 if( xReturn != pdFAIL )

205 {

206 /* Rx and Tx interrupts are used. */

207 ETH_DMAITConfig( ETH_DMA_IT_NIS | ETH_DMA_IT_R | ETH_DMA_IT_T, ENABLE );

208

209 /* Only a single Tx descriptor is used. For now it is set to use an Rx

210 buffer, but will get updated to point to where ever uip_buf is

211 pointing prior to its use. */

212 ETH_DMATxDescChainInit( ( void * ) &xTxDescriptor, ( void * ) ucMACBuffers, 1 );

213 ETH_DMARxDescChainInit( xRxDescriptors, ( void * ) ucMACBuffers, uipNUM_RX_DESCRIPTORS );

214 for( ul = 0; ul < uipNUM_RX_DESCRIPTORS; ul++ )

215 {

216 /* Ensure received data generates an interrupt. */

217 ETH_DMARxDescReceiveITConfig( &( xRxDescriptors[ ul ] ), ENABLE );

218

219 /* Fix up the addresses used by the descriptors.

220 The way ETH_DMARxDescChainInit() is not compatible with the buffer

221 declarations in this file. */

222 xRxDescriptors[ ul ].Buffer1Addr = ( unsigned long ) &( ucMACBuffers[ ul ][ 0 ] );

223

224 /* Mark the buffer used by this descriptor as in use. */

225 ucBufferInUse[ ul ] = pdTRUE;

226 }

227

228 /* When receiving data, start at the first descriptor. */

229 ulNextDescriptor = 0;

230

231 /* Initialise uip_buf to ensure it points somewhere valid. */

232 uip_buf = prvGetNextBuffer();

233

234 /* SendCount must be initialised to 2 to ensure the Tx descriptor looks

235 as if its available (as if it has already been sent twice. */

236 xTxDescriptor.SendCount = 2;

237

238 /* Switch on the interrupts in the NVIC. */

239 xNVICInit.NVIC_IRQChannel = uipENET_IRQ_NUM;

240 xNVICInit.NVIC_IRQChannelPreemptionPriority = configLIBRARY_KERNEL_INTERRUPT_PRIORITY;

241 xNVICInit.NVIC_IRQChannelSubPriority = 0;

242 xNVICInit.NVIC_IRQChannelCmd = ENABLE;

243 NVIC_Init( &xNVICInit );

244

245 /* Buffers and descriptors are all set up, now enable the MAC. */

246 ETH_Start();

247

248 /* Let the DMA know there are Rx descriptors available. */

249 prvRxDescriptorAvailable();

250 }

251

252 return xReturn;

253 }

254 /*-----------------------------------------------------------*/

255

256 static unsigned char *prvGetNextBuffer( void )

257 {

258 portBASE_TYPE x;

259 unsigned char *ucReturn = NULL;

260 unsigned long ulAttempts = 0;

261

262 while( ucReturn == NULL )

263 {

264 /* Look through the buffers to find one that is not in use by

265 anything else. */

266 for( x = 0; x < uipNUM_BUFFERS; x++ )

267 {

268 if( ucBufferInUse[ x ] == pdFALSE )

269 {

270 ucBufferInUse[ x ] = pdTRUE;

271 ucReturn = &( ucMACBuffers[ x ][ 0 ] );

272 break;

273 }

274 }

275

276 /* Was a buffer found? */

277 if( ucReturn == NULL )

278 {

279 ulAttempts++;

280

281 if( ulAttempts >= uipBUFFER_WAIT_ATTEMPTS )

282 {

283 break;

284 }

285

286 /* Wait then look again. */

287 vTaskDelay( uipBUFFER_WAIT_DELAY );

288 }

289 }

290

291 return ucReturn;

292 }

293 /*-----------------------------------------------------------*/

294

295 unsigned short usGetMACRxData( void )

296 {

297 unsigned short usReturn;

298

299 if( ( xRxDescriptors[ ulNextDescriptor ].Status & ETH_DMARxDesc_ES ) != 0 )

300 {

301 /* Error in Rx. Discard the frame and give it back to the DMA. */

302 xRxDescriptors[ ulNextDescriptor ].Status = ETH_DMARxDesc_OWN;

303 prvRxDescriptorAvailable();

304

305 /* No data to return. */

306 usReturn = 0UL;

307

308 /* Start from the next descriptor the next time this function is called. */

309 ulNextDescriptor++;

310 if( ulNextDescriptor >= uipNUM_RX_DESCRIPTORS )

311 {

312 ulNextDescriptor = 0UL;

313 }

314 }

315 else if( ( xRxDescriptors[ ulNextDescriptor ].Status & ETH_DMARxDesc_OWN ) == 0 )

316 {

317 /* Mark the current buffer as free as uip_buf is going to be set to

318 the buffer that contains the received data. */

319 vReturnBuffer( uip_buf );

320

321 /* Get the received data length from the top 2 bytes of the Status

322 word and the data itself. */

323 usReturn = ( unsigned short ) ( ( xRxDescriptors[ ulNextDescriptor ].Status & ETH_DMARxDesc_FL ) >> 16UL );

324 uip_buf = ( unsigned char * ) ( xRxDescriptors[ ulNextDescriptor ].Buffer1Addr );

325

326 /* Allocate a new buffer to the descriptor. */

327 xRxDescriptors[ ulNextDescriptor ].Buffer1Addr = ( unsigned long ) prvGetNextBuffer();

328

329 /* Give the descriptor back to the DMA. */

330 xRxDescriptors[ ulNextDescriptor ].Status = ETH_DMARxDesc_OWN;

331 prvRxDescriptorAvailable();

332

333 /* Start from the next descriptor the next time this function is called. */

334 ulNextDescriptor++;

335 if( ulNextDescriptor >= uipNUM_RX_DESCRIPTORS )

336 {

337 ulNextDescriptor = 0UL;

338 }

339 }

340 else

341 {

342 /* No received data at all. */

343 usReturn = 0UL;

344 }

345

346 return usReturn;

347 }

348 /*-----------------------------------------------------------*/

349

350 void vSendMACData( unsigned short usDataLen )

351 {

352 unsigned long ulAttempts = 0UL;

353

354 /* Check to see if the Tx descriptor is free. The check against <2 is to

355 ensure the buffer has been sent twice and in so doing preventing a race

356 condition with the DMA on the ETH_DMATxDesc_OWN bit. */

357 while( ( xTxDescriptor.SendCount < 2 ) && ( xTxDescriptor.Status & ETH_DMATxDesc_OWN ) == ETH_DMATxDesc_OWN )

358 {

359 /* Wait for the Tx descriptor to become available. */

360 vTaskDelay( uipBUFFER_WAIT_DELAY );

361

362 ulAttempts++;

363 if( ulAttempts > uipBUFFER_WAIT_ATTEMPTS )

364 {

365 /* Something has gone wrong as the Tx descriptor is still in use.

366 Clear it down manually, the data it was sending will probably be

367 lost. */

368 xTxDescriptor.Status &= ~ETH_DMATxDesc_OWN;

369 vReturnBuffer( ( unsigned char * ) xTxDescriptor.Buffer1Addr );

370 break;

371 }

372 }

373

374 /* Setup the Tx descriptor for transmission. */

375 xTxDescriptor.SendCount = 0;

376 xTxDescriptor.Buffer1Addr = ( unsigned long ) uip_buf;

377 xTxDescriptor.ControlBufferSize = ( unsigned long ) usDataLen;

379 ETH_DMA->DMASR = ETH_DMASR_TBUS;

380 ETH_DMA->DMATPDR = 0;

381

382 /* uip_buf is being sent by the Tx descriptor. Allocate a new buffer. */

383 uip_buf = prvGetNextBuffer();

384 }

385 /*-----------------------------------------------------------*/

386

387 static void prvSetupEthGPIO( void )

388 {

389 GPIO_InitTypeDef xEthInit;

390

391 /* Remap MAC IO. */

392 AFIO->MAPR |= ( uipREMAP_MAC_IO );

393

394 /* Set PA2, PA8, PB5, PB8, PB11, PB12, PB13, PC1 and PC2 for Ethernet

395 interfacing. */

396 xEthInit.GPIO_Pin = GPIO_Pin_2;/* | GPIO_Pin_8; This should be set when the 25MHz is generated by MCO. */

397 xEthInit.GPIO_Speed = GPIO_Speed_50MHz;

398 xEthInit.GPIO_Mode = GPIO_Mode_AF_PP;

399 GPIO_Init( GPIOA, &xEthInit );

400

401 xEthInit.GPIO_Pin = GPIO_Pin_5 | GPIO_Pin_8 | GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13; /*5*/

402 GPIO_Init( GPIOB, &xEthInit );

403

404 xEthInit.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_2;

405 GPIO_Init( GPIOC, &xEthInit );

406

407

408 /* Configure PA0, PA1, PA3, PB10, PC3, PD8, PD9, PD10, PD11 and PD12 as

409 inputs. */

410 xEthInit.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_3;

411 xEthInit.GPIO_Mode = GPIO_Mode_IN_FLOATING;

412 GPIO_Init( GPIOA, &xEthInit );

413

414 xEthInit.GPIO_Pin = GPIO_Pin_10;

415 GPIO_Init( GPIOB, &xEthInit );

416

417 xEthInit.GPIO_Pin = GPIO_Pin_3;

418 GPIO_Init( GPIOC, &xEthInit );

419

420 xEthInit.GPIO_Pin = GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_11 | GPIO_Pin_12;

421 GPIO_Init( GPIOD, &xEthInit );

422 }

423 /*-----------------------------------------------------------*/

424

425 void vReturnBuffer( unsigned char *pucBuffer )

426 {

427 unsigned long ul;

428

429 /* Mark a buffer as free for use. */

430 for( ul = 0; ul < uipNUM_BUFFERS; ul++ )

431 {

432 if( ucMACBuffers[ ul ] == pucBuffer )

433 {

434 ucBufferInUse[ ul ] = pdFALSE;

435 break;

436 }

437 }

438 }

439 /*-----------------------------------------------------------*/

440

441 void vMAC_ISR( void )

442 {

443 unsigned long ulStatus;

444 extern xSemaphoreHandle xEMACSemaphore;

445 long xHigherPriorityTaskWoken = pdFALSE;

446

447 /* What caused the interrupt? */

448 ulStatus = ETH_DMA->DMASR;

449

450 /* Clear everything before leaving. */

451 ETH_DMA->DMASR = ulStatus;

452

453 if( ulStatus & ETH_DMA_IT_R )

454 {

455 /* Data was received. Ensure the uIP task is not blocked as data has

456 arrived. */

457 xSemaphoreGiveFromISR( xEMACSemaphore, &xHigherPriorityTaskWoken );

458 }

459

460 if( ulStatus & ETH_DMA_IT_T )

461 {

462 /* Data was transmitted. */

463 if( xTxDescriptor.SendCount == 0 )

464 {

465 /* Send again! */

466 ( xTxDescriptor.SendCount )++;

467

469 ETH_DMA->DMASR = ETH_DMASR_TBUS;

470 ETH_DMA->DMATPDR = 0;

471 }

472 else

473 {

474 /* The Tx buffer is no longer required. */

475 vReturnBuffer( ( unsigned char * ) xTxDescriptor.Buffer1Addr );

476 }

477 }

478

479 /* If xSemaphoreGiveFromISR() unblocked a task, and the unblocked task has

480 a higher priority than the currently executing task, then

481 xHigherPriorityTaskWoken will have been set to pdTRUE and this ISR should

482 return directly to the higher priority unblocked task. */

483 portEND_SWITCHING_ISR( xHigherPriorityTaskWoken );

484 }

485