begriffs open source - cmsis-freertos/blob - Demo/WizNET_DEMO_TERN

1 // 186.cfg

2 // You must select RAM, ROM for your controller 04-26-2000

3 // Your TERN controller is installed with SRAM and ROM with different sizes.

4 // For debug, 128K or 512K SRAM can be selected

5 // For build a ROM, you need to select the ROM size.

6 // How to select ?

7 // 1) commend out the unwanted #define RAM size line with "//"

8 // 2) delete the "//" preceding the wanted #define RAM size line

9 //

10

11 // #define RAM 32 // 32KB SRAM installed

12 #define RAM 128 // 128KB SRAM installed

13 // #define RAM 512 // 512KB SRAM installed

14

15 // #define ROM 32 // Use 32KB ROM chip 27C256-70

16 #define ROM 64 // Use 64KB ROM chip 27C512-70

17 // #define ROM 128 // Use 128KB ROM chip 27C010-70

18 // #define ROM 256 // Use 256KB ROM chip 27C020-70

19 // #define ROM 512 // Use 512KB ROM chip 27C040-70, Change Jumper on board

20

21

22 cputype Am186ES // AMD188/6 based controllers

23

24 #if defined(__PDREMOTE__)

25

26 #if RAM == 32

27 map 0x00000 to 0x00fff as reserved // interrupt vector table

28 map 0x01000 to 0x03fff as rdwr // System RAM area (60KB RAM)

29 map 0x04000 to 0x07fff as rdonly // Simulated EPROM area (64KB RAM)

30 map 0x08000 to 0xfffff as reserved // No access allowed

31 #define CODE_START 0x0400 // Start of application code, STEP2 !

32

33 #elif RAM == 128

34 map 0x00000 to 0x00fff as reserved // interrupt vector table

35 map 0x01000 to 0x07fff as rdwr // System RAM area (60KB RAM)

36 map 0x08000 to 0x1ffff as rdonly // Simulated EPROM area (64KB RAM)

37 map 0x20000 to 0xfffff as reserved // No access allowed

38 #define CODE_START 0x0800 // Start of application code

39

40 #elif RAM == 512

41 map 0x00000 to 0x00fff as reserved // interrupt vector table

42 map 0x01000 to 0x07fff as rdwr // System RAM area (60KB RAM)

43 map 0x08000 to 0x7ffff as rdonly // Simulated EPROM area(480KB RAM)

44 map 0x80000 to 0xfffff as reserved // No access allowed

45 #define CODE_START 0x0800 // Start of application code

46 #endif

47

48 #define DATA_START 0x0100 // Start of application data

49 #define BOOT_START 0x1fc0 // Start of initialization code

50

51 #else

52 #if ROM == 32

53 map 0x00000 to 0x1ffff as rdwr // 128KB RAM address space

54 map 0x20000 to 0xf7fff as reserved // No access

55 map 0xF8000 to 0xfffff as rdonly // 32KB EPROM address space

56 #define CODE_START 0xF800 // Start of application code

57 #elif ROM == 64

58 map 0x00000 to 0x1ffff as rdwr // 128KB RAM address space

59 map 0x20000 to 0xEffff as reserved // No access

60 map 0xF0000 to 0xfffff as rdonly // 64KB EPROM address space

61 #define CODE_START 0xF000 // Start of application code

62 #elif ROM == 128

63 map 0x00000 to 0x1ffff as rdwr // 128KB RAM address space

64 map 0x20000 to 0xDffff as reserved // No access

65 map 0xE0000 to 0xfffff as rdonly // 128KB EPROM address space

66 #define CODE_START 0xE000 // Start of application code

67 #elif ROM == 256

68 map 0x00000 to 0x1ffff as rdwr // 128KB RAM address space

69 map 0x20000 to 0xBffff as reserved // No access

70 map 0xC0000 to 0xfffff as rdonly // 256KB EPROM address space

71 #define CODE_START 0xC000 // Start of application code

72 #elif ROM == 512

73 map 0x00000 to 0x1ffff as rdwr // 128KB RAM address space

74 map 0x20000 to 0x7ffff as reserved // No access

75 map 0x80000 to 0xfffff as rdonly // 512KB EPROM address space

76 #define CODE_START 0x8000 // Start of application code

77 #endif

78

79 #define DATA_START 0x0040 // Start of application data

80 #define BOOT_START 0xffc0 // Start of initialization code

81

82 initcode reset \ // Reset vector to program entry point

83 umcs = 0x80bf \ // 512K ROM, 3 wait states

84 lmcs = 0x7fbf \ // 512K RAM, 3 wait states

85 mpcs = 0xa0bf \

86 mmcs = 0x81ff \

87 pacs = 0x007f

88

89 class ??LOCATE = BOOT_START // Chip select initialization

90 output ??LOCATE

91

92 #if ROM == 32 // 27C256-90 EPROM or FLASH

93 hexfile binary offset=0xf8000 size=32 // for 27C256, bin file

94 #elif ROM == 64 // 27C512-90 EPROM or FLASH

95 hexfile binary offset=0xF0000 size=64 // for 27C512

96 #elif ROM == 128 // 27C010-90 EPROM or FLASH

97 hexfile binary offset=0xE0000 size=128 // for 27C010

98 #elif ROM == 256 // 27C020-90 EPROM or FLASH

99 hexfile binary offset=0xC0000 size=256 // for 27C020

100 #elif ROM == 512 // 27C040-90 EPROM or FLASH

101 hexfile Intel86 offset=0x80000 size=512 // for 27C040, output .HEX file

102 #endif

103

104 #endif

105

106

107 //

108 // Start of common configuration file settings.

109 //

110

111 absfile axe86 // Paradigm C++ debugging output

112 listfile segments // Absolute segment map

113

114 dup DATA ROMDATA // Make a copy of initialized data

115 dup FAR_DATA ROMFARDATA // Make a copy of far initialized data

116

117 #if defined(__COMPFARDATA__) // Compress and display results

118 compress ROMFARDATA

119 display compression

120 #endif

121

122 class CODE = CODE_START // Application code

123 class DATA = DATA_START // Application data

124

125 order DATA \ // RAM class organization

126 BSS \

127 NVRAM \

128 EDATA \

129 STACK \

130 FAR_DATA ENDFAR_DATA \

131 FAR_BSS ENDFAR_BSS \

132 FAR_HEAP ENDFAR_HEAP

133

134 order CODE \ // EPROM class organization

135 INITDATA EXITDATA \

136 FAR_CONST ENDFAR_CONST \

137 ROMDATA ENDROMDATA \

138 ROMFARDATA ENDROMFARDATA

139

140 output CODE \ // Classes in the output file(s)

141 INITDATA EXITDATA \

142 FAR_CONST ENDFAR_CONST \

143 ROMDATA ENDROMDATA \

144 ROMFARDATA ENDROMFARDATA

145 \1a