begriffs open source - cmsis-freertos/blob - Demo/ARM7_AT91SAM7S64

1 ;* ----------------------------------------------------------------------------

2 ;* ATMEL Microcontroller Software Support - ROUSSET -

3 ;* ----------------------------------------------------------------------------

5 ;

7 ;*

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31 ;* ----------------------------------------------------------------------------

32

33 ;------------------------------------------------------------------------------

34 ; Include your AT91 Library files

35 ;------------------------------------------------------------------------------

36 #include "AT91SAM7X256_inc.h"

37 ;------------------------------------------------------------------------------

38

39 #define TOP_OF_MEMORY (AT91C_ISRAM + AT91C_ISRAM_SIZE)

40 #define IRQ_STACK_SIZE 200

41 ; 3 words to be saved per interrupt priority level

42

43 ; Mode, correspords to bits 0-5 in CPSR

44 MODE_BITS DEFINE 0x1F ; Bit mask for mode bits in CPSR

45 USR_MODE DEFINE 0x10 ; User mode

46 FIQ_MODE DEFINE 0x11 ; Fast Interrupt Request mode

47 IRQ_MODE DEFINE 0x12 ; Interrupt Request mode

48 SVC_MODE DEFINE 0x13 ; Supervisor mode

49 ABT_MODE DEFINE 0x17 ; Abort mode

50 UND_MODE DEFINE 0x1B ; Undefined Instruction mode

51 SYS_MODE DEFINE 0x1F ; System mode

52

53 I_BIT DEFINE 0x80

54 F_BIT DEFINE 0x40

55

56 ;------------------------------------------------------------------------------

57 ; ?RESET

58 ; Reset Vector.

59 ; Normally, segment INTVEC is linked at address 0.

60 ; For debugging purposes, INTVEC may be placed at other addresses.

61 ; A debugger that honors the entry point will start the

62 ; program in a normal way even if INTVEC is not at address 0.

63 ;------------------------------------------------------------------------------

64 SECTION .intvec:CODE:NOROOT(2)

65 PUBLIC __vector

66 PUBLIC __iar_program_start

67 EXTERN vPortYieldProcessor

68

69 ARM

70 __vector:

71 ldr pc,[pc,#+24] ;; Reset

72 __und_handler:

73 ldr pc,[pc,#+24] ;; Undefined instructions

74 __swi_handler:

75 ldr pc,[pc,#+24] ;; Software interrupt (SWI/SVC)

76 __prefetch_handler:

77 ldr pc,[pc,#+24] ;; Prefetch abort

78 __data_handler:

79 ldr pc,[pc,#+24] ;; Data abort

80 DC32 0xFFFFFFFF ;; RESERVED

81 __irq_handler:

82 LDR PC, [PC, #-0xF20]

83 __fiq_handler:

84 ldr pc,[pc,#+24] ;; FIQ

85

86 DC32 __iar_program_start

87 DC32 __und_handler

88 DC32 vPortYieldProcessor

89 DC32 __prefetch_handler

90 DC32 __data_handler

91 B .

92 DC32 IRQ_Handler_Entry

93 DC32 FIQ_Handler_Entry

94

95 ;------------------------------------------------------------------------------

96 ;- Manage exception: The exception must be ensure in ARM mode

97 ;------------------------------------------------------------------------------

98 SECTION text:CODE:NOROOT(2)

99 ARM

100 ;------------------------------------------------------------------------------

101 ;- Function : FIQ_Handler_Entry

102 ;- Treatments : FIQ Controller Interrupt Handler.

103 ;- R8 is initialize in Cstartup

104 ;- Called Functions : None only by FIQ

105 ;------------------------------------------------------------------------------

106 FIQ_Handler_Entry:

107

108 ;- Switch in SVC/User Mode to allow User Stack access for C code

109 ; because the FIQ is not yet acknowledged

110

111 ;- Save and r0 in FIQ_Register

112 mov r9,r0

113 ldr r0 , [r8, #AIC_FVR]

114 msr CPSR_c,#I_BIT | F_BIT | SVC_MODE

115 ;- Save scratch/used registers and LR in User Stack

116 stmfd sp!, { r1-r3, r12, lr}

117

118 ;- Branch to the routine pointed by the AIC_FVR

119 mov r14, pc

120 bx r0

121

122 ;- Restore scratch/used registers and LR from User Stack

123 ldmia sp!, { r1-r3, r12, lr}

124

125 ;- Leave Interrupts disabled and switch back in FIQ mode

126 msr CPSR_c, #I_BIT | F_BIT | FIQ_MODE

127

128 ;- Restore the R0 ARM_MODE_SVC register

129 mov r0,r9

130

131 ;- Restore the Program Counter using the LR_fiq directly in the PC

132 subs pc,lr,#4

133 ;------------------------------------------------------------------------------

134 ;- Function : IRQ_Handler_Entry

135 ;- Treatments : IRQ Controller Interrupt Handler.

136 ;- Called Functions : AIC_IVR[interrupt]

137 ;------------------------------------------------------------------------------

138 IRQ_Handler_Entry:

139 ;-------------------------

140 ;- Manage Exception Entry

141 ;-------------------------

142 ;- Adjust and save LR_irq in IRQ stack

143 sub lr, lr, #4

144 stmfd sp!, {lr}

145

146 ;- Save r0 and SPSR (need to be saved for nested interrupt)

147 mrs r14, SPSR

148 stmfd sp!, {r0,r14}

149

150 ;- Write in the IVR to support Protect Mode

151 ;- No effect in Normal Mode

152 ;- De-assert the NIRQ and clear the source in Protect Mode

153 ldr r14, =AT91C_BASE_AIC

154 ldr r0 , [r14, #AIC_IVR]

155 str r14, [r14, #AIC_IVR]

156

157 ;- Enable Interrupt and Switch in Supervisor Mode

158 msr CPSR_c, #SVC_MODE

159

160 ;- Save scratch/used registers and LR in User Stack

161 stmfd sp!, { r1-r3, r12, r14}

162

163 ;----------------------------------------------

164 ;- Branch to the routine pointed by the AIC_IVR

165 ;----------------------------------------------

166 mov r14, pc

167 bx r0

168

169 ;----------------------------------------------

170 ;- Manage Exception Exit

171 ;----------------------------------------------

172 ;- Restore scratch/used registers and LR from User Stack

173 ldmia sp!, { r1-r3, r12, r14}

174

175 ;- Disable Interrupt and switch back in IRQ mode

176 msr CPSR_c, #I_BIT | IRQ_MODE

177

178 ;- Mark the End of Interrupt on the AIC

179 ldr r14, =AT91C_BASE_AIC

180 str r14, [r14, #AIC_EOICR]

181

182 ;- Restore SPSR_irq and r0 from IRQ stack

183 ldmia sp!, {r0,r14}

184 msr SPSR_cxsf, r14

185

186 ;- Restore adjusted LR_irq from IRQ stack directly in the PC

187 ldmia sp!, {pc}^

188

189 ;------------------------------------------------------------------------------

190 ;- Exception Vectors

191 ;------------------------------------------------------------------------------

192 PUBLIC AT91F_Default_FIQ_handler

193 PUBLIC AT91F_Default_IRQ_handler

194 PUBLIC AT91F_Spurious_handler

195

196 ARM ; Always ARM mode after exeption

197

198 AT91F_Default_FIQ_handler

199 b AT91F_Default_FIQ_handler

200

201 AT91F_Default_IRQ_handler

202 b AT91F_Default_IRQ_handler

203

204 AT91F_Spurious_handler

205 b AT91F_Spurious_handler

206

207

208 ;------------------------------------------------------------------------------

209 ; ?INIT

210 ; Program entry.

211 ;------------------------------------------------------------------------------

212

213 SECTION FIQ_STACK:DATA:NOROOT(3)

214 SECTION IRQ_STACK:DATA:NOROOT(3)

215 SECTION SVC_STACK:DATA:NOROOT(3)

216 SECTION ABT_STACK:DATA:NOROOT(3)

217 SECTION UND_STACK:DATA:NOROOT(3)

218 SECTION CSTACK:DATA:NOROOT(3)

219 SECTION text:CODE:NOROOT(2)

220 REQUIRE __vector

221 EXTERN ?main

222 PUBLIC __iar_program_start

223 EXTERN AT91F_LowLevelInit

224

225

226 __iar_program_start:

227

228 ;------------------------------------------------------------------------------

229 ;- Low level Init is performed in a C function: AT91F_LowLevelInit

230 ;- Init Stack Pointer to a valid memory area before calling AT91F_LowLevelInit

231 ;------------------------------------------------------------------------------

232

233 ;- Retrieve end of RAM address

234

235 ldr r13,=TOP_OF_MEMORY ;- Temporary stack in internal RAM for Low Level Init execution

236 ldr r0,=AT91F_LowLevelInit

237 mov lr, pc

238 bx r0 ;- Branch on C function (with interworking)

239

240 ; Initialize the stack pointers.

241 ; The pattern below can be used for any of the exception stacks:

242 ; FIQ, IRQ, SVC, ABT, UND, SYS.

243 ; The USR mode uses the same stack as SYS.

244 ; The stack segments must be defined in the linker command file,

245 ; and be declared above.

246

247 mrs r0,cpsr ; Original PSR value

248 bic r0,r0,#MODE_BITS ; Clear the mode bits

249 orr r0,r0,#SVC_MODE ; Set SVC mode bits

250 msr cpsr_c,r0 ; Change the mode

251 ldr sp,=SFE(SVC_STACK) ; End of SVC_STACK

252

253 bic r0,r0,#MODE_BITS ; Clear the mode bits

254 orr r0,r0,#UND_MODE ; Set UND mode bits

255 msr cpsr_c,r0 ; Change the mode

256 ldr sp,=SFE(UND_STACK) ; End of UND_STACK

257

258 bic r0,r0,#MODE_BITS ; Clear the mode bits

259 orr r0,r0,#ABT_MODE ; Set ABT mode bits

260 msr cpsr_c,r0 ; Change the mode

261 ldr sp,=SFE(ABT_STACK) ; End of ABT_STACK

262

263 bic r0,r0,#MODE_BITS ; Clear the mode bits

264 orr r0,r0,#FIQ_MODE ; Set FIQ mode bits

265 msr cpsr_c,r0 ; Change the mode

266 ldr sp,=SFE(FIQ_STACK) ; End of FIQ_STACK

267 ;- Init the FIQ register

268 ldr r8, =AT91C_BASE_AIC

269

270 bic r0,r0,#MODE_BITS ; Clear the mode bits

271 orr r0,r0,#IRQ_MODE ; Set IRQ mode bits

272 msr cpsr_c,r0 ; Change the mode

273 ldr sp,=SFE(IRQ_STACK) ; End of IRQ_STACK

274

275 bic r0,r0,#MODE_BITS ; Clear the mode bits

276 orr r0,r0,#SYS_MODE ; Set System mode bits

277 msr cpsr_c,r0 ; Change the mode

278 ldr sp,=SFE(CSTACK) ; End of CSTACK

279

280

281 #ifdef __ARMVFP__

282 ; Enable the VFP coprocessor.

283 mov r0, #0x40000000 ; Set EN bit in VFP

284 fmxr fpexc, r0 ; FPEXC, clear others.

285

286 ; Disable underflow exceptions by setting flush to zero mode.

287 ; For full IEEE 754 underflow compliance this code should be removed

288 ; and the appropriate exception handler installed.

289 mov r0, #0x01000000 ; Set FZ bit in VFP

290 fmxr fpscr, r0 ; FPSCR, clear others.

291 #endif

292

293 ; Add more initialization here

294 msr CPSR_c,#I_BIT | F_BIT | SVC_MODE

295

296

297 ; Continue to ?main for more IAR specific system startup

298

299 ldr r0,=?main

300 bx r0

301

302 END ;- Terminates the assembly of the last module in a file