begriffs open source - cmsis-freertos/blob - Demo/ARM7_STR71x

2 * File Name : rccu.c

3 * Author : MCD Application Team

4 * Date First Issued : 07/28/2003

5 * Description : This file provides all the RCCU software functions

6 ********************************************************************************

7 * History:

8 * 30/11/2004 : V2.0

9 * 14/07/2004 : V1.3

10 * 01/01/2004 : V1.2

11 *******************************************************************************

12 THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH

13 CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.

14 AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT

15 OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT

16 OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION

17 CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

18 *******************************************************************************/

19 #include "rccu.h"

20

21 /*******************************************************************************

22 * Function Name : RCCU_PLL1Config

23 * Description : Configures the PLL1 div & mul factors.

24 * Input : New_Mul ( RCCU_PLL1_Mul_12, RCCU_PLL1_Mul_16, RCCU_PLL1_Mul_20,

25 * RCCU_PLL1_Mul_24 )

26 * : New_Div ( RCCU_Div_1, RCCU_Div_2, RCCU_Div_3, RCCU_Div_4,

27 * RCCU_Div_5, RCCU_Div_6, RCCU_Div_7)

28 * Return : None

29 *******************************************************************************/

30 void RCCU_PLL1Config ( RCCU_PLL1_Mul New_Mul, RCCU_PLL_Div New_Div )

31 {

32 u32 Tmp = ( RCCU->PLL1CR & ~RCCU_MX_Mask ) | ( New_Mul << RCCU_MX_Index );

33 RCCU->PLL1CR = ( Tmp & ~RCCU_DX_Mask ) | New_Div | 0x40;

34 }

35

36 /*******************************************************************************

37 * Function Name : RCCU_PLL2Config

38 * Description : Configures the PLL2 div & mul factors.

39 * Input : New_Mul ( RCCU_PLL2_Mul_12, RCCU_PLL2_Mul_16, RCCU_PLL2_Mul_20,

40 * RCCU_Mul_PLL2_28 )

41 * : New_Div ( RCCU_Div_1, RCCU_Div_2, RCCU_Div_3, RCCU_Div_4,

42 * RCCU_Div_5, RCCU_Div_6, RCCU_Div_7)

43 * Return : None

44 *******************************************************************************/

45 void RCCU_PLL2Config ( RCCU_PLL2_Mul New_Mul, RCCU_PLL_Div New_Div )

46 {

47 u32 Tmp = ( PCU->PLL2CR & ~RCCU_MX_Mask ) | ( New_Mul << RCCU_MX_Index );

48 PCU->PLL2CR = ( Tmp & ~RCCU_DX_Mask ) | ( New_Div | RCCU_FREEN_Mask );

49 }

50

51 /*******************************************************************************

52 * Function Name : RCCU_RCLKSourceConfig

53 * Description : Selects the RCLK source clock

54 * Input : New_Clock ( RCCU_PLL1_Output, RCCU_CLOCK2_16, RCCU_CLOCK2 )

55 * Return : None

56 *******************************************************************************/

57 void RCCU_RCLKSourceConfig ( RCCU_RCLK_Clocks New_Clock )

58 {

59 switch ( New_Clock )

60 {

61 case RCCU_CLOCK2 :{// Resets the CSU_Cksel bit in clk_flag

62 RCCU->CFR &= ~RCCU_CSU_CKSEL_Mask;

63 // Set the CK2_16 Bit in the CFR

64 RCCU->CFR |= RCCU_CK2_16_Mask;

65 // Deselect The CKAF

66 RCCU->CCR &= ~RCCU_CKAF_SEL_Mask;

67 // switch off the PLL1

68 RCCU->PLL1CR=((RCCU->PLL1CR & ~RCCU_DX_Mask)\

69 |0x00000003) & ~RCCU_FREEN_Mask;

70 break;}

71 case RCCU_CLOCK2_16 :{// ReSet the CK2_16 Bit in the CFR

72 RCCU->CFR &= ~RCCU_CK2_16_Mask;

73 // Deselect The CKAF

74 RCCU->CCR &= ~RCCU_CKAF_SEL_Mask;

75 // switch off the PLL1

76 RCCU->PLL1CR=((RCCU->PLL1CR & ~RCCU_DX_Mask)\

77 |0x00000003) & ~RCCU_FREEN_Mask;

78 break;}

79 case RCCU_PLL1_Output:{// Set the CK2_16 Bit in the CFR

80 RCCU->CFR = RCCU->CFR | RCCU_CK2_16_Mask;

81 // Waits the PLL1 to lock if DX bits are different from '111'

82 // If all DX bit are set the PLL lock flag in meaningless

83 if (( RCCU->PLL1CR & 0x0007 ) != 7)

84 while(!(RCCU->CFR & RCCU_LOCK_Mask));

85 // Deselect The CKAF

86 RCCU->CCR &= ~RCCU_CKAF_SEL_Mask;

87 // Select The CSU_CKSEL

88 RCCU->CFR |= RCCU_CSU_CKSEL_Mask;

89 break;}

90 case RCCU_RTC_CLOCK : {RCCU->CCR |= 0x04;

91 break;}

92 }

93 }

94

95 /*******************************************************************************

96 * Function Name : RCCU_RCLKClockSource

97 * Description : Returns the current RCLK source clock

98 * Input : None

99 * Return : RCCU_PLL1_Output, RCCU_CLOCK2_16, RCCU_CLOCK2, RCCU_RTC_CLOCK

100 *******************************************************************************/

101 RCCU_RCLK_Clocks RCCU_RCLKClockSource ( void )

102 {

103 if ((RCCU->CCR & 0x04)==0x04)

104 return RCCU_RTC_CLOCK;

105

106 else if ((RCCU->CFR & RCCU_CK2_16_Mask)==0)

107 return RCCU_CLOCK2_16;

108

109 else if (RCCU->CFR & RCCU_CSU_CKSEL_Mask)

110 return RCCU_PLL1_Output;

111

112 else

113 return RCCU_CLOCK2;

114 }

115

116 /*******************************************************************************

117 * Function Name : RCCU_USBClockSource

118 * Description : Gets the RCLK source clock

119 * Input : None

120 * Return : RCCU_USB_Clocks ( RCCU_PLL2_Output, RCCU_USBCK )

121 *******************************************************************************/

122 RCCU_USB_Clocks RCCU_USBClockSource ( void )

123 {

124 if ((PCU->PLL2CR & RCCU_USBEN_Mask ) >> RCCU_USBEN_Index == 1 )

125 return RCCU_PLL2_Output;

126 else return RCCU_USBCK;

127 }

128

129 /*******************************************************************************

130 * Function Name : RCCU_FrequencyValue

131 * Description : Calculates & Returns any internal RCCU clock frequency

132 * passed in parametres

133 * Input : RCCU_Clocks ( RCCU_CLK2, RCCU_RCLK, RCCU_MCLK, RCCU_PCLK, RCCU_FCLK )

134 * Return : u32

135 *******************************************************************************/

136 u32 RCCU_FrequencyValue ( RCCU_Clocks Internal_Clk )

137 {

138 u32 Tmp;

139 u8 Div, Mul;

140 RCCU_RCLK_Clocks CurrentRCLK;

141

142 Tmp = ( RCCU_Div2Status() == SET )? RCCU_Main_Osc / 2 : RCCU_Main_Osc;

143

144 if ( Internal_Clk == RCCU_CLK2 )

145 {

146 Div = 1;

147 Mul = 1;

148 }

149 else

150 { CurrentRCLK = RCCU_RCLKClockSource ();

151 switch ( CurrentRCLK ){

152 case RCCU_CLOCK2_16 : Div = 16;

153 Mul = 1;

154 break;

155 case RCCU_CLOCK2 : Div = 1;

156 Mul = 1;

157 break;

158 case RCCU_PLL1_Output :{Mul=(RCCU->PLL1CR & RCCU_MX_Mask ) >> RCCU_MX_Index;

159 switch ( Mul )

160 {case 0: Mul = 20; break;

161 case 1: Mul = 12; break;

162 case 2: Mul = 28; break;

163 case 3: Mul = 16; break;

164 }

165 Div = ( RCCU->PLL1CR & RCCU_DX_Mask ) + 1;

166 break;}

167 case RCCU_RTC_CLOCK : Mul = 1;

168 Div = 1;

169 Tmp = RCCU_RTC_Osc;

170 break;}}

171

172 switch ( Internal_Clk ){

173 case RCCU_MCLK :{Div <<= PCU->MDIVR & RCCU_FACT_Mask;

174 break;}

175 case RCCU_PCLK :{Div <<=(PCU->PDIVR & RCCU_FACT2_Mask ) >> RCCU_FACT2_Index;

176 break;}

177 case RCCU_FCLK :{Div <<= PCU->PDIVR & 0x3;

178 break;}}

179

180 return (Tmp * Mul) / Div;

181 }

182