begriffs open source - cmsis-freertos/blob - Demo/ARM9_STR91X_IAR/91x

2 ;* File Name : 91x_init.s

3 ;* Author : MCD Application Team

4 ;* Date First Issued : 05/18/2006 : Version 1.0

5 ;* Description : This module performs:

6 ;* - FLASH/RAM initialization,

7 ;* - Stack pointer initialization for each mode ,

8 ;* - Branches to ?main in the C library (which eventually

9 ;* calls main()).

10 ;*

11 ;* On reset, the ARM core starts up in Supervisor (SVC) mode,

12 ;* in ARM state,with IRQ and FIQ disabled.

13 ;*******************************************************************************

14 ;* History:

15 ;* 05/22/2007 : Version 1.2

16 ;* 05/24/2006 : Version 1.1

17 ;* 05/18/2006 : Version 1.0

18 ;*******************************************************************************

19 ;* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH

20 ;* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS

21 ;* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT

22 ;* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT

23 ;* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION

24 ;* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

25 ;******************************************************************************/

26

27 ; At power up, the CPU defaults to run on the oscillator clock, so Depending

28 ; of your Application, Disable or Enable the following Define

29

30 #define PLL_Clock ; Use PLL as the default clock source @ 96 MHz only with

31 ; Bank 0 @ 0x0 and Bank 1 @ 0x80000

32 ; #define RTC_Clock ; Use RTC as the default clock source

33 ; #define OSC_Clock ; Use OSC as the default clock source

34

35

36 ; --- Standard definitions of mode bits and interrupt (I & F) flags in PSRs

37

38 Mode_USR EQU 0x10

39 Mode_FIQ EQU 0x11

40 Mode_IRQ EQU 0x12

41 Mode_SVC EQU 0x13

42 Mode_ABT EQU 0x17

43 Mode_UND EQU 0x1B

44 Mode_SYS EQU 0x1F ; available on ARM Arch 4 and later

45

46 I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled

47 F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled

48

49

50

51 ; --- STR9X SCU specific definitions

52

53 SCU_BASE_Address EQU 0x5C002000 ; SCU Base Address

54 SCU_CLKCNTR_OFST EQU 0x00000000 ; Clock Control register Offset

55 SCU_PLLCONF_OFST EQU 0x00000004 ; PLL Configuration register Offset

56 SCU_SYSSTATUS_OFST EQU 0x00000008 ; System Status Register Offset

57 SCU_SCR0_OFST EQU 0x00000034 ; System Configuration Register 0 Offset

58

59 ; --- STR9X FMI specific definitions

60

61 FMI_BASE_Address EQU 0x54000000 ; FMI Base Address

62 FMI_BBSR_OFST EQU 0x00000000 ; Boot Bank Size Register

63 FMI_NBBSR_OFST EQU 0x00000004 ; Non-boot Bank Size Register

64 FMI_BBADR_OFST EQU 0x0000000C ; Boot Bank Base Address Register

65 FMI_NBBADR_OFST EQU 0x00000010 ; Non-boot Bank Base Address Register

66 FMI_CR_OFST EQU 0x00000018 ; Control Register

67

68 ;---------------------------------------------------------------

69 ; ?program_start

70 ;---------------------------------------------------------------

71 MODULE ?program_start

72

73 SECTION IRQ_STACK:DATA:NOROOT(3)

74 SECTION FIQ_STACK:DATA:NOROOT(3)

75 SECTION UND_STACK:DATA:NOROOT(3)

76 SECTION ABT_STACK:DATA:NOROOT(3)

77 SECTION SVC_STACK:DATA:NOROOT(3)

78 SECTION CSTACK:DATA:NOROOT(3)

79 SECTION .icode:CODE:NOROOT(2)

80 PUBLIC __iar_program_start

81 EXTERN ?main

82 CODE32

83

84 __iar_program_start:

85 LDR pc, =NextInst

88 NextInst

91 NOP ; execute some instructions to access CPU registers after wake

92 NOP ; up from Reset, while waiting for OSC stabilization

93 NOP

94 NOP

95 NOP

96 NOP

97 NOP

98 NOP

99 NOP

100

101

102 ; BUFFERED_Mode

103 ; ------------------------------------------------------------------------------

104 ; Description : Enable the Buffered mode.

105 ; Just enable the buffered define on the 91x_conf.h

106 ; http://www.arm.com/pdfs/DDI0164A_966E_S.pdf

107 ; ------------------------------------------------------------------------------

108

109 MRC p15, 0, r0, c1, c0, 0 ; Read CP15 register 1 into r0

110 ORR r0, r0, #0x8 ; Enable Write Buffer on AHB

111 MCR p15, 0, r0, c1, c0, 0 ; Write CP15 register 1

112

113

114

115 ; --- Remap Flash Bank 0 at address 0x0 and Bank 1 at address 0x80000,

116 ; when the bank 0 is the boot bank, then enable the Bank 1.

117

118 LDR R6, =FMI_BASE_Address

119

120 LDR R7, = 0x4 ; BOOT BANK Size = 512KB

121 STR R7, [R6, #FMI_BBSR_OFST] ; (2^4) * 32 = 512KB

122

123 LDR R7, = 0x2 ; NON BOOT BANK Size = 32KB

124 STR R7, [R6, #FMI_NBBSR_OFST] ; (2^2) * 8 = 32KB

125

126 LDR R7, = 0x0 ; BOOT BANK Address = 0x0

127 STR R7, [R6, #FMI_BBADR_OFST]

128

129 LDR R7, = 0x20000 ; NON BOOT BANK Address = 0x80000

130 STR R7, [R6, #FMI_NBBADR_OFST] ; need to put 0x20000 because FMI

131 ; bus on A[25:2] of CPU bus

132

133 LDR R7, = 0x18 ; Enable CS on both banks

134 STR R7, [R6, #FMI_CR_OFST] ; LDR R7, = 0x19 ;in RevD

135 ; to enable 8 words PFQ deepth

136

137 ; --- Enable 96K RAM, PFQBC enabled, DTCM & AHB wait-states disabled

138 LDR R0, = SCU_BASE_Address

139 LDR R1, = 0x0191

140 STR R1, [R0, #SCU_SCR0_OFST]

141

142 ; ------------------------------------------------------------------------------

143 ; --- System clock configuration

144 ; ------------------------------------------------------------------------------

145

146 #ifdef PLL_Clock ; Use 96 MHZ PLL clock as the default frequency

147

148 ; --- wait states Flash confguration

149

150 LDR R6, = 0x00080000 ;Write a Write Flash Configuration

151 LDR R7, =0x60 ;Register command (60h) to any word

152 STRH R7, [R6] ;address in Bank 1.

153

154 LDR R6, = 0x00083040 ;Write a Write Flash Configuration

155 LDR R7, = 0x3 ;Register Confirm command (03h)

156 STRH R7, [R6] ;2Wstaites in read,PWD,LVD enabled,

157 ;High BUSCFG.

158 ; --- PLL configuration

159 LDR R1, = 0x00020002 ;Set OSC as clock source

160 STR R1, [R0, #SCU_CLKCNTR_OFST ]

161

162

163 NOP ; Wait for OSC stabilization

164 NOP

165 NOP

166 NOP

167 NOP

168 NOP

169 NOP

170 NOP

171 NOP

172 NOP

173 NOP

174 NOP

175

176

177

178

179 LDR R1, = 0x000ac019 ;Set PLL ENABLE, to 96Mhz

180 STR R1, [R0, #SCU_PLLCONF_OFST]

181

182 Wait_Loop

183 LDR R1,[R0, #SCU_SYSSTATUS_OFST] ;Wait until PLL is Locked

184 ANDS R1, R1, #0x01

185 BEQ Wait_Loop

186

187 LDR R1, = 0x00020080 ;Set PLL as clock source after pll

188 STR R1, [R0, #SCU_CLKCNTR_OFST ] ;is locked and FMICLK=RCLK,

189 ;PCLK=RCLK/2

190 #endif

191

192 #ifdef RTC_Clock ;Use RTC as the default clock source

193 LDR R1, = 0x00020001 ;Set RTC as clock source and

194 STR R1, [R0, #SCU_CLKCNTR_OFST ] ;FMICLK=RCLK, PCLK=RCLK

195 #endif

196

197 #ifdef OSC_Clock ;Use Osc as the default clock source

198 LDR R1, = 0x00020002 ;Set OSC as clock source and

199 STR R1, [R0, #SCU_CLKCNTR_OFST ] ;FMICLK=RCLK, PCLK=RCLK

200 #endif

201

202

203 ; --- Initialize Stack pointer registers

204

205 ; Enter each mode in turn and set up the stack pointer

206

207 MSR CPSR_c, #Mode_FIQ|I_Bit|F_Bit ; No interrupts

208 LDR SP, =SFE(FIQ_STACK)

209

210 MSR CPSR_c, #Mode_IRQ|I_Bit|F_Bit ; No interrupts

211 LDR SP, = SFE(IRQ_STACK)

212

213 MSR CPSR_c, #Mode_ABT|I_Bit|F_Bit ; No interrupts

214 LDR SP, = SFE(ABT_STACK)

215

216 MSR CPSR_c, #Mode_UND|I_Bit|F_Bit ; No interrupts

217 LDR SP, = SFE(UND_STACK)

218

219 MSR CPSR_c, #Mode_SYS ; IRQs & FIQs are now enabled

220 LDR SP, = SFE(CSTACK)

221

222 MSR CPSR_c, #Mode_SVC|I_Bit|F_Bit ; No interrupts

223 LDR SP, = SFE(SVC_STACK)

224

225 ; --- Set bits 17-18(DTCM/ITCM order bits)of the Core Configuration Control

226 ; Register

227 MOV r0, #0x60000

228 MCR p15,0x1,r0,c15,c1,0

229

230 ; --- Now enter the C code

231 B ?main ; Note : use B not BL, because an application will

232 ; never return this way

234 LTORG

237 END