begriffs open source - cmsis-freertos/blob - Demo/CORTEX_LPC1768

1 #ifndef __LPC17xx_H

2 #define __LPC17xx_H

4 /* System Control Block (SCB) includes:

5 Flash Accelerator Module, Clocking and Power Control, External Interrupts,

6 Reset, System Control and Status

7 */

8 #define SCB_BASE_ADDR 0x400FC000

10 #define PCONP_PCTIM0 0x00000002

11 #define PCONP_PCTIM1 0x00000004

12 #define PCONP_PCUART0 0x00000008

13 #define PCONP_PCUART1 0x00000010

14 #define PCONP_PCPWM1 0x00000040

15 #define PCONP_PCI2C0 0x00000080

16 #define PCONP_PCSPI 0x00000100

17 #define PCONP_PCRTC 0x00000200

18 #define PCONP_PCSSP1 0x00000400

19 #define PCONP_PCAD 0x00001000

20 #define PCONP_PCCAN1 0x00002000

21 #define PCONP_PCCAN2 0x00004000

22 #define PCONP_PCGPIO 0x00008000

23 #define PCONP_PCRIT 0x00010000

24 #define PCONP_PCMCPWM 0x00020000

25 #define PCONP_PCQEI 0x00040000

26 #define PCONP_PCI2C1 0x00080000

27 #define PCONP_PCSSP0 0x00200000

28 #define PCONP_PCTIM2 0x00400000

29 #define PCONP_PCTIM3 0x00800000

30 #define PCONP_PCUART2 0x01000000

31 #define PCONP_PCUART3 0x02000000

32 #define PCONP_PCI2C2 0x04000000

33 #define PCONP_PCI2S 0x08000000

34 #define PCONP_PCGPDMA 0x20000000

35 #define PCONP_PCENET 0x40000000

36 #define PCONP_PCUSB 0x80000000

38 #define PLLCON_PLLE 0x00000001

39 #define PLLCON_PLLC 0x00000002

40 #define PLLCON_MASK 0x00000003

42 #define PLLCFG_MUL1 0x00000000

43 #define PLLCFG_MUL2 0x00000001

44 #define PLLCFG_MUL3 0x00000002

45 #define PLLCFG_MUL4 0x00000003

46 #define PLLCFG_MUL5 0x00000004

47 #define PLLCFG_MUL6 0x00000005

48 #define PLLCFG_MUL7 0x00000006

49 #define PLLCFG_MUL8 0x00000007

50 #define PLLCFG_MUL9 0x00000008

51 #define PLLCFG_MUL10 0x00000009

52 #define PLLCFG_MUL11 0x0000000A

53 #define PLLCFG_MUL12 0x0000000B

54 #define PLLCFG_MUL13 0x0000000C

55 #define PLLCFG_MUL14 0x0000000D

56 #define PLLCFG_MUL15 0x0000000E

57 #define PLLCFG_MUL16 0x0000000F

58 #define PLLCFG_MUL17 0x00000010

59 #define PLLCFG_MUL18 0x00000011

60 #define PLLCFG_MUL19 0x00000012

61 #define PLLCFG_MUL20 0x00000013

62 #define PLLCFG_MUL21 0x00000014

63 #define PLLCFG_MUL22 0x00000015

64 #define PLLCFG_MUL23 0x00000016

65 #define PLLCFG_MUL24 0x00000017

66 #define PLLCFG_MUL25 0x00000018

67 #define PLLCFG_MUL26 0x00000019

68 #define PLLCFG_MUL27 0x0000001A

69 #define PLLCFG_MUL28 0x0000001B

70 #define PLLCFG_MUL29 0x0000001C

71 #define PLLCFG_MUL30 0x0000001D

72 #define PLLCFG_MUL31 0x0000001E

73 #define PLLCFG_MUL32 0x0000001F

74 #define PLLCFG_MUL33 0x00000020

75 #define PLLCFG_MUL34 0x00000021

76 #define PLLCFG_MUL35 0x00000022

77 #define PLLCFG_MUL36 0x00000023

79 #define PLLCFG_DIV1 0x00000000

80 #define PLLCFG_DIV2 0x00010000

81 #define PLLCFG_DIV3 0x00020000

82 #define PLLCFG_DIV4 0x00030000

83 #define PLLCFG_DIV5 0x00040000

84 #define PLLCFG_DIV6 0x00050000

85 #define PLLCFG_DIV7 0x00060000

86 #define PLLCFG_DIV8 0x00070000

87 #define PLLCFG_DIV9 0x00080000

88 #define PLLCFG_DIV10 0x00090000

89 #define PLLCFG_MASK 0x00FF7FFF

91 #define PLLSTAT_MSEL_MASK 0x00007FFF

92 #define PLLSTAT_NSEL_MASK 0x00FF0000

94 #define PLLSTAT_PLLE (1 << 24)

95 #define PLLSTAT_PLLC (1 << 25)

96 #define PLLSTAT_PLOCK (1 << 26)

98 #define PLLFEED_FEED1 0x000000AA

99 #define PLLFEED_FEED2 0x00000055

100

101 #define NVIC_IRQ_WDT 0u // IRQ0, exception number 16

102 #define NVIC_IRQ_TIMER0 1u // IRQ1, exception number 17

103 #define NVIC_IRQ_TIMER1 2u // IRQ2, exception number 18

104 #define NVIC_IRQ_TIMER2 3u // IRQ3, exception number 19

105 #define NVIC_IRQ_TIMER3 4u // IRQ4, exception number 20

106 #define NVIC_IRQ_UART0 5u // IRQ5, exception number 21

107 #define NVIC_IRQ_UART1 6u // IRQ6, exception number 22

108 #define NVIC_IRQ_UART2 7u // IRQ7, exception number 23

109 #define NVIC_IRQ_UART3 8u // IRQ8, exception number 24

110 #define NVIC_IRQ_PWM1 9u // IRQ9, exception number 25

111 #define NVIC_IRQ_I2C0 10u // IRQ10, exception number 26

112 #define NVIC_IRQ_I2C1 11u // IRQ11, exception number 27

113 #define NVIC_IRQ_I2C2 12u // IRQ12, exception number 28

114 #define NVIC_IRQ_SPI 13u // IRQ13, exception number 29

115 #define NVIC_IRQ_SSP0 14u // IRQ14, exception number 30

116 #define NVIC_IRQ_SSP1 15u // IRQ15, exception number 31

117 #define NVIC_IRQ_PLL0 16u // IRQ16, exception number 32

118 #define NVIC_IRQ_RTC 17u // IRQ17, exception number 33

119 #define NVIC_IRQ_EINT0 18u // IRQ18, exception number 34

120 #define NVIC_IRQ_EINT1 19u // IRQ19, exception number 35

121 #define NVIC_IRQ_EINT2 20u // IRQ20, exception number 36

122 #define NVIC_IRQ_EINT3 21u // IRQ21, exception number 37

123 #define NVIC_IRQ_ADC 22u // IRQ22, exception number 38

124 #define NVIC_IRQ_BOD 23u // IRQ23, exception number 39

125 #define NVIC_IRQ_USB 24u // IRQ24, exception number 40

126 #define NVIC_IRQ_CAN 25u // IRQ25, exception number 41

127 #define NVIC_IRQ_GPDMA 26u // IRQ26, exception number 42

128 #define NVIC_IRQ_I2S 27u // IRQ27, exception number 43

129 #define NVIC_IRQ_ETHERNET 28u // IRQ28, exception number 44

130 #define NVIC_IRQ_RIT 29u // IRQ29, exception number 45

131 #define NVIC_IRQ_MCPWM 30u // IRQ30, exception number 46

132 #define NVIC_IRQ_QE 31u // IRQ31, exception number 47

133 #define NVIC_IRQ_PLL1 32u // IRQ32, exception number 48

134 #define NVIC_IRQ_USB_ACT 33u // IRQ33, exception number 49

135 #define NVIC_IRQ_CAN_ACT 34u // IRQ34, exception number 50

136

137

138 #endif // __LPC17xx_H

139

140

141 #ifndef CMSIS_17xx_H

142 #define CMSIS_17xx_H

143

144 /******************************************************************************

145 * @file: LPC17xx.h

146 * @purpose: CMSIS Cortex-M3 Core Peripheral Access Layer Header File for

147 * NXP LPC17xx Device Series

148 * @version: V1.1

149 * @date: 14th May 2009

150 *----------------------------------------------------------------------------

151 *

153 *

154 * ARM Limited (ARM) is supplying this software for use with Cortex-M3

155 * processor based microcontrollers. This file can be freely distributed

156 * within development tools that are supporting such ARM based processors.

157 *

158 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED

159 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF

160 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.

161 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR

162 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.

163 *

164 ******************************************************************************/

165

166

167 #ifndef __LPC17xx_H__

168 #define __LPC17xx_H__

169

170 /*

171 * ==========================================================================

172 * ---------- Interrupt Number Definition -----------------------------------

173 * ==========================================================================

174 */

175

176 typedef enum IRQn

177 {

178 /****** Cortex-M3 Processor Exceptions Numbers ***************************************************/

179 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */

180 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */

181 BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */

182 UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */

183 SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */

184 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */

185 PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */

186 SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */

187

188 /****** LPC17xx Specific Interrupt Numbers *******************************************************/

189 WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */

190 TIMER0_IRQn = 1, /*!< Timer0 Interrupt */

191 TIMER1_IRQn = 2, /*!< Timer1 Interrupt */

192 TIMER2_IRQn = 3, /*!< Timer2 Interrupt */

193 TIMER3_IRQn = 4, /*!< Timer3 Interrupt */

194 UART0_IRQn = 5, /*!< UART0 Interrupt */

195 UART1_IRQn = 6, /*!< UART1 Interrupt */

196 UART2_IRQn = 7, /*!< UART2 Interrupt */

197 UART3_IRQn = 8, /*!< UART3 Interrupt */

198 PWM1_IRQn = 9, /*!< PWM1 Interrupt */

199 I2C0_IRQn = 10, /*!< I2C0 Interrupt */

200 I2C1_IRQn = 11, /*!< I2C1 Interrupt */

201 I2C2_IRQn = 12, /*!< I2C2 Interrupt */

202 SPI_IRQn = 13, /*!< SPI Interrupt */

203 SSP0_IRQn = 14, /*!< SSP0 Interrupt */

204 SSP1_IRQn = 15, /*!< SSP1 Interrupt */

205 PLL0_IRQn = 16, /*!< PLL0 Lock (Main PLL) Interrupt */

206 RTC_IRQn = 17, /*!< Real Time Clock Interrupt */

207 EINT0_IRQn = 18, /*!< External Interrupt 0 Interrupt */

208 EINT1_IRQn = 19, /*!< External Interrupt 1 Interrupt */

209 EINT2_IRQn = 20, /*!< External Interrupt 2 Interrupt */

210 EINT3_IRQn = 21, /*!< External Interrupt 3 Interrupt */

211 ADC_IRQn = 22, /*!< A/D Converter Interrupt */

212 BOD_IRQn = 23, /*!< Brown-Out Detect Interrupt */

213 USB_IRQn = 24, /*!< USB Interrupt */

214 CAN_IRQn = 25, /*!< CAN Interrupt */

215 DMA_IRQn = 26, /*!< General Purpose DMA Interrupt */

216 I2S_IRQn = 27, /*!< I2S Interrupt */

217 ENET_IRQn = 28, /*!< Ethernet Interrupt */

218 RIT_IRQn = 29, /*!< Repetitive Interrupt Timer Interrupt */

219 MCPWM_IRQn = 30, /*!< Motor Control PWM Interrupt */

220 QEI_IRQn = 31, /*!< Quadrature Encoder Interface Interrupt */

221 PLL1_IRQn = 32, /*!< PLL1 Lock (USB PLL) Interrupt */

222 } IRQn_Type;

223

224

225 /*

226 * ==========================================================================

227 * ----------- Processor and Core Peripheral Section ------------------------

228 * ==========================================================================

229 */

230

231 /* Configuration of the Cortex-M3 Processor and Core Peripherals */

232 #define __MPU_PRESENT 1 /*!< MPU present or not */

233 #define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */

234 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */

235

236

237 //#include "..\core_cm3.h" /* Cortex-M3 processor and core peripherals */

238 #include "core_cm3.h"

239 #include "system_LPC17xx.h" /* System Header */

240

241

242

243 /**

244 * Initialize the system clock

245 *

246 * @param none

247 * @return none

248 *

249 * @brief Setup the microcontroller system.

250 * Initialize the System and update the SystemFrequency variable.

251 */

252 extern void SystemInit (void);

253

254

255 /******************************************************************************/

256 /* Device Specific Peripheral registers structures */

257 /******************************************************************************/

258

259 /*------------- System Control (SC) ------------------------------------------*/

260 typedef struct

261 {

262 __IO uint32_t FLASHCFG; /* Flash Accelerator Module */

263 uint32_t RESERVED0[31];

264 __IO uint32_t PLL0CON; /* Clocking and Power Control */

265 __IO uint32_t PLL0CFG;

266 __I uint32_t PLL0STAT;

267 __O uint32_t PLL0FEED;

268 uint32_t RESERVED1[4];

269 __IO uint32_t PLL1CON;

270 __IO uint32_t PLL1CFG;

271 __I uint32_t PLL1STAT;

272 __O uint32_t PLL1FEED;

273 uint32_t RESERVED2[4];

274 __IO uint32_t PCON;

275 __IO uint32_t PCONP;

276 uint32_t RESERVED3[15];

277 __IO uint32_t CCLKCFG;

278 __IO uint32_t USBCLKCFG;

279 __IO uint32_t CLKSRCSEL;

280 uint32_t RESERVED4[12];

281 __IO uint32_t EXTINT; /* External Interrupts */

282 uint32_t RESERVED5;

283 __IO uint32_t EXTMODE;

284 __IO uint32_t EXTPOLAR;

285 uint32_t RESERVED6[12];

286 __IO uint32_t RSID; /* Reset */

287 uint32_t RESERVED7[7];

288 __IO uint32_t SCS; /* Syscon Miscellaneous Registers */

289 __IO uint32_t IRCTRIM; /* Clock Dividers */

290 __IO uint32_t PCLKSEL0;

291 __IO uint32_t PCLKSEL1;

292 uint32_t RESERVED8[4];

293 __IO uint32_t USBIntSt; /* USB Device/OTG Interrupt Register */

294 uint32_t RESERVED9;

295 __IO uint32_t CLKOUTCFG; /* Clock Output Configuration */

296 } SC_TypeDef;

297

298 /*------------- Pin Connect Block (PINCON) -----------------------------------*/

299 typedef struct

300 {

301 __IO uint32_t PINSEL0;

302 __IO uint32_t PINSEL1;

303 __IO uint32_t PINSEL2;

304 __IO uint32_t PINSEL3;

305 __IO uint32_t PINSEL4;

306 __IO uint32_t PINSEL5;

307 __IO uint32_t PINSEL6;

308 __IO uint32_t PINSEL7;

309 __IO uint32_t PINSEL8;

310 __IO uint32_t PINSEL9;

311 __IO uint32_t PINSEL10;

312 uint32_t RESERVED0[5];

313 __IO uint32_t PINMODE0;

314 __IO uint32_t PINMODE1;

315 __IO uint32_t PINMODE2;

316 __IO uint32_t PINMODE3;

317 __IO uint32_t PINMODE4;

318 __IO uint32_t PINMODE5;

319 __IO uint32_t PINMODE6;

320 __IO uint32_t PINMODE7;

321 __IO uint32_t PINMODE8;

322 __IO uint32_t PINMODE9;

323 __IO uint32_t PINMODE_OD0;

324 __IO uint32_t PINMODE_OD1;

325 __IO uint32_t PINMODE_OD2;

326 __IO uint32_t PINMODE_OD3;

327 __IO uint32_t PINMODE_OD4;

328 } PINCON_TypeDef;

329

330 /*------------- General Purpose Input/Output (GPIO) --------------------------*/

331 typedef struct

332 {

333 __IO uint32_t FIODIR;

334 uint32_t RESERVED0[3];

335 __IO uint32_t FIOMASK;

336 __IO uint32_t FIOPIN;

337 __IO uint32_t FIOSET;

338 __O uint32_t FIOCLR;

339 } GPIO_TypeDef;

340

341 typedef struct

342 {

343 __I uint32_t IntStatus;

344 __I uint32_t IO0IntStatR;

345 __I uint32_t IO0IntStatF;

346 __O uint32_t IO0IntClr;

347 __IO uint32_t IO0IntEnR;

348 __IO uint32_t IO0IntEnF;

349 uint32_t RESERVED0[3];

350 __I uint32_t IO2IntStatR;

351 __I uint32_t IO2IntStatF;

352 __O uint32_t IO2IntClr;

353 __IO uint32_t IO2IntEnR;

354 __IO uint32_t IO2IntEnF;

355 } GPIOINT_TypeDef;

356

357 /*------------- Timer (TIM) --------------------------------------------------*/

358 typedef struct

359 {

360 __IO uint32_t IR;

361 __IO uint32_t TCR;

362 __IO uint32_t TC;

363 __IO uint32_t PR;

364 __IO uint32_t PC;

365 __IO uint32_t MCR;

366 __IO uint32_t MR0;

367 __IO uint32_t MR1;

368 __IO uint32_t MR2;

369 __IO uint32_t MR3;

370 __IO uint32_t CCR;

371 __I uint32_t CR0;

372 __I uint32_t CR1;

373 uint32_t RESERVED0[2];

374 __IO uint32_t EMR;

375 uint32_t RESERVED1[24];

376 __IO uint32_t CTCR;

377 } TIM_TypeDef;

378

379 /*------------- Pulse-Width Modulation (PWM) ---------------------------------*/

380 typedef struct

381 {

382 __IO uint32_t IR;

383 __IO uint32_t TCR;

384 __IO uint32_t TC;

385 __IO uint32_t PR;

386 __IO uint32_t PC;

387 __IO uint32_t MCR;

388 __IO uint32_t MR0;

389 __IO uint32_t MR1;

390 __IO uint32_t MR2;

391 __IO uint32_t MR3;

392 __IO uint32_t CCR;

393 __I uint32_t CR0;

394 __I uint32_t CR1;

395 __I uint32_t CR2;

396 __I uint32_t CR3;

397 __IO uint32_t MR4;

398 __IO uint32_t MR5;

399 __IO uint32_t MR6;

400 __IO uint32_t PCR;

401 __IO uint32_t LER;

402 uint32_t RESERVED0[7];

403 __IO uint32_t CTCR;

404 } PWM_TypeDef;

405

406 /*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/

407 typedef struct

408 {

409 union {

410 __I uint8_t RBR;

411 __O uint8_t THR;

412 __IO uint8_t DLL;

413 uint32_t RESERVED0;

414 };

415 union {

416 __IO uint8_t DLM;

417 __IO uint32_t IER;

418 };

419 union {

420 __I uint32_t IIR;

421 __O uint8_t FCR;

422 };

423 __IO uint8_t LCR;

424 uint8_t RESERVED1[7];

425 __IO uint8_t LSR;

426 uint8_t RESERVED2[7];

427 __IO uint8_t SCR;

428 uint8_t RESERVED3[3];

429 __IO uint32_t ACR;

430 __IO uint8_t ICR;

431 uint8_t RESERVED4[3];

432 __IO uint8_t FDR;

433 uint8_t RESERVED5[7];

434 __IO uint8_t TER;

435 uint8_t RESERVED6[27];

436 __IO uint8_t RS485CTRL;

437 uint8_t RESERVED7[3];

438 __IO uint8_t ADRMATCH;

439 } UART_TypeDef;

440

441 typedef struct

442 {

443 union {

444 __I uint8_t RBR;

445 __O uint8_t THR;

446 __IO uint8_t DLL;

447 uint32_t RESERVED0;

448 };

449 union {

450 __IO uint8_t DLM;

451 __IO uint32_t IER;

452 };

453 union {

454 __I uint32_t IIR;

455 __O uint8_t FCR;

456 };

457 __IO uint8_t LCR;

458 uint8_t RESERVED1[3];

459 __IO uint8_t MCR;

460 uint8_t RESERVED2[3];

461 __IO uint8_t LSR;

462 uint8_t RESERVED3[3];

463 __IO uint8_t MSR;

464 uint8_t RESERVED4[3];

465 __IO uint8_t SCR;

466 uint8_t RESERVED5[3];

467 __IO uint32_t ACR;

468 uint32_t RESERVED6;

469 __IO uint32_t FDR;

470 uint32_t RESERVED7;

471 __IO uint8_t TER;

472 uint8_t RESERVED8[27];

473 __IO uint8_t RS485CTRL;

474 uint8_t RESERVED9[3];

475 __IO uint8_t ADRMATCH;

476 uint8_t RESERVED10[3];

477 __IO uint8_t RS485DLY;

478 } UART1_TypeDef;

479

480 /*------------- Serial Peripheral Interface (SPI) ----------------------------*/

481 typedef struct

482 {

483 __IO uint32_t SPCR;

484 __I uint32_t SPSR;

485 __IO uint32_t SPDR;

486 __IO uint32_t SPCCR;

487 uint32_t RESERVED0[3];

488 __IO uint32_t SPINT;

489 } SPI_TypeDef;

490

491 /*------------- Synchronous Serial Communication (SSP) -----------------------*/

492 typedef struct

493 {

494 __IO uint32_t CR0;

495 __IO uint32_t CR1;

496 __IO uint32_t DR;

497 __I uint32_t SR;

498 __IO uint32_t CPSR;

499 __IO uint32_t IMSC;

500 __IO uint32_t RIS;

501 __IO uint32_t MIS;

502 __IO uint32_t ICR;

503 __IO uint32_t DMACR;

504 } SSP_TypeDef;

505

506 /*------------- Inter-Integrated Circuit (I2C) -------------------------------*/

507 typedef struct

508 {

509 __IO uint32_t I2CONSET;

510 __I uint32_t I2STAT;

511 __IO uint32_t I2DAT;

512 __IO uint32_t I2ADR0;

513 __IO uint32_t I2SCLH;

514 __IO uint32_t I2SCLL;

515 __O uint32_t I2CONCLR;

516 __IO uint32_t MMCTRL;

517 __IO uint32_t I2ADR1;

518 __IO uint32_t I2ADR2;

519 __IO uint32_t I2ADR3;

520 __I uint32_t I2DATA_BUFFER;

521 __IO uint32_t I2MASK0;

522 __IO uint32_t I2MASK1;

523 __IO uint32_t I2MASK2;

524 __IO uint32_t I2MASK3;

525 } I2C_TypeDef;

526

527 /*------------- Inter IC Sound (I2S) -----------------------------------------*/

528 typedef struct

529 {

530 __IO uint32_t I2SDAO;

531 __IO uint32_t I2SDAI;

532 __O uint32_t I2STXFIFO;

533 __I uint32_t I2SRXFIFO;

534 __I uint32_t I2SSTATE;

535 __IO uint32_t I2SDMA1;

536 __IO uint32_t I2SDMA2;

537 __IO uint32_t I2SIRQ;

538 __IO uint32_t I2STXRATE;

539 __IO uint32_t I2SRXRATE;

540 __IO uint32_t I2STXBITRATE;

541 __IO uint32_t I2SRXBITRATE;

542 __IO uint32_t I2STXMODE;

543 __IO uint32_t I2SRXMODE;

544 } I2S_TypeDef;

545

546 /*------------- Repetitive Interrupt Timer (RIT) -----------------------------*/

547 typedef struct

548 {

549 __IO uint32_t RICOMPVAL;

550 __IO uint32_t RIMASK;

551 __IO uint8_t RICTRL;

552 uint8_t RESERVED0[3];

553 __IO uint32_t RICOUNTER;

554 } RIT_TypeDef;

555

556 /*------------- Real-Time Clock (RTC) ----------------------------------------*/

557 typedef struct

558 {

559 __IO uint8_t ILR;

560 uint8_t RESERVED0[3];

561 __IO uint8_t CCR;

562 uint8_t RESERVED1[3];

563 __IO uint8_t CIIR;

564 uint8_t RESERVED2[3];

565 __IO uint8_t AMR;

566 uint8_t RESERVED3[3];

567 __I uint32_t CTIME0;

568 __I uint32_t CTIME1;

569 __I uint32_t CTIME2;

570 __IO uint8_t SEC;

571 uint8_t RESERVED4[3];

572 __IO uint8_t MIN;

573 uint8_t RESERVED5[3];

574 __IO uint8_t HOUR;

575 uint8_t RESERVED6[3];

576 __IO uint8_t DOM;

577 uint8_t RESERVED7[3];

578 __IO uint8_t DOW;

579 uint8_t RESERVED8[3];

580 __IO uint16_t DOY;

581 uint16_t RESERVED9;

582 __IO uint8_t MONTH;

583 uint8_t RESERVED10[3];

584 __IO uint16_t YEAR;

585 uint16_t RESERVED11;

586 __IO uint32_t CALIBRATION;

587 __IO uint32_t GPREG0;

588 __IO uint32_t GPREG1;

589 __IO uint32_t GPREG2;

590 __IO uint32_t GPREG3;

591 __IO uint32_t GPREG4;

592 __IO uint8_t WAKEUPDIS;

593 uint8_t RESERVED12[3];

594 __IO uint8_t PWRCTRL;

595 uint8_t RESERVED13[3];

596 __IO uint8_t ALSEC;

597 uint8_t RESERVED14[3];

598 __IO uint8_t ALMIN;

599 uint8_t RESERVED15[3];

600 __IO uint8_t ALHOUR;

601 uint8_t RESERVED16[3];

602 __IO uint8_t ALDOM;

603 uint8_t RESERVED17[3];

604 __IO uint8_t ALDOW;

605 uint8_t RESERVED18[3];

606 __IO uint16_t ALDOY;

607 uint16_t RESERVED19;

608 __IO uint8_t ALMON;

609 uint8_t RESERVED20[3];

610 __IO uint16_t ALYEAR;

611 uint16_t RESERVED21;

612 } RTC_TypeDef;

613

614 /*------------- Watchdog Timer (WDT) -----------------------------------------*/

615 typedef struct

616 {

617 __IO uint8_t WDMOD;

618 uint8_t RESERVED0[3];

619 __IO uint32_t WDTC;

620 __O uint8_t WDFEED;

621 uint8_t RESERVED1[3];

622 __I uint32_t WDTV;

623 __IO uint32_t WDCLKSEL;

624 } WDT_TypeDef;

625

626 /*------------- Analog-to-Digital Converter (ADC) ----------------------------*/

627 typedef struct

628 {

629 __IO uint32_t ADCR;

630 __IO uint32_t ADGDR;

631 uint32_t RESERVED0;

632 __IO uint32_t ADINTEN;

633 __I uint32_t ADDR0;

634 __I uint32_t ADDR1;

635 __I uint32_t ADDR2;

636 __I uint32_t ADDR3;

637 __I uint32_t ADDR4;

638 __I uint32_t ADDR5;

639 __I uint32_t ADDR6;

640 __I uint32_t ADDR7;

641 __I uint32_t ADSTAT;

642 __IO uint32_t ADTRM;

643 } ADC_TypeDef;

644

645 /*------------- Digital-to-Analog Converter (DAC) ----------------------------*/

646 typedef struct

647 {

648 __IO uint32_t DACR;

649 __IO uint32_t DACCTRL;

650 __IO uint16_t DACCNTVAL;

651 } DAC_TypeDef;

652

653 /*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/

654 typedef struct

655 {

656 __I uint32_t MCCON;

657 __O uint32_t MCCON_SET;

658 __O uint32_t MCCON_CLR;

659 __I uint32_t MCCAPCON;

660 __O uint32_t MCCAPCON_SET;

661 __O uint32_t MCCAPCON_CLR;

662 __IO uint32_t MCTIM0;

663 __IO uint32_t MCTIM1;

664 __IO uint32_t MCTIM2;

665 __IO uint32_t MCPER0;

666 __IO uint32_t MCPER1;

667 __IO uint32_t MCPER2;

668 __IO uint32_t MCPW0;

669 __IO uint32_t MCPW1;

670 __IO uint32_t MCPW2;

671 __IO uint32_t MCDEADTIME;

672 __IO uint32_t MCCCP;

673 __IO uint32_t MCCR0;

674 __IO uint32_t MCCR1;

675 __IO uint32_t MCCR2;

676 __I uint32_t MCINTEN;

677 __O uint32_t MCINTEN_SET;

678 __O uint32_t MCINTEN_CLR;

679 __I uint32_t MCCNTCON;

680 __O uint32_t MCCNTCON_SET;

681 __O uint32_t MCCNTCON_CLR;

682 __I uint32_t MCINTFLAG;

683 __O uint32_t MCINTFLAG_SET;

684 __O uint32_t MCINTFLAG_CLR;

685 __O uint32_t MCCAP_CLR;

686 } MCPWM_TypeDef;

687

688 /*------------- Quadrature Encoder Interface (QEI) ---------------------------*/

689 typedef struct

690 {

691 __O uint32_t QEICON;

692 __I uint32_t QEISTAT;

693 __IO uint32_t QEICONF;

694 __I uint32_t QEIPOS;

695 __IO uint32_t QEIMAXPOS;

696 __IO uint32_t CMPOS0;

697 __IO uint32_t CMPOS1;

698 __IO uint32_t CMPOS2;

699 __I uint32_t INXCNT;

700 __IO uint32_t INXCMP;

701 __IO uint32_t QEILOAD;

702 __I uint32_t QEITIME;

703 __I uint32_t QEIVEL;

704 __I uint32_t QEICAP;

705 __IO uint32_t VELCOMP;

706 __IO uint32_t FILTER;

707 uint32_t RESERVED0[998];

708 __O uint32_t QEIIEC;

709 __O uint32_t QEIIES;

710 __I uint32_t QEIINTSTAT;

711 __I uint32_t QEIIE;

712 __O uint32_t QEICLR;

713 __O uint32_t QEISET;

714 } QEI_TypeDef;

715

716 /*------------- Controller Area Network (CAN) --------------------------------*/

717 typedef struct

718 {

719 __IO uint32_t mask[512]; /* ID Masks */

720 } CANAF_RAM_TypeDef;

721

722 typedef struct /* Acceptance Filter Registers */

723 {

724 __IO uint32_t AFMR;

725 __IO uint32_t SFF_sa;

726 __IO uint32_t SFF_GRP_sa;

727 __IO uint32_t EFF_sa;

728 __IO uint32_t EFF_GRP_sa;

729 __IO uint32_t ENDofTable;

730 __I uint32_t LUTerrAd;

731 __I uint32_t LUTerr;

732 } CANAF_TypeDef;

733

734 typedef struct /* Central Registers */

735 {

736 __I uint32_t CANTxSR;

737 __I uint32_t CANRxSR;

738 __I uint32_t CANMSR;

739 } CANCR_TypeDef;

740

741 typedef struct /* Controller Registers */

742 {

743 __IO uint32_t MOD;

744 __O uint32_t CMR;

745 __IO uint32_t GSR;

746 __I uint32_t ICR;

747 __IO uint32_t IER;

748 __IO uint32_t BTR;

749 __IO uint32_t EWL;

750 __I uint32_t SR;

751 __IO uint32_t RFS;

752 __IO uint32_t RID;

753 __IO uint32_t RDA;

754 __IO uint32_t RDB;

755 __IO uint32_t TFI1;

756 __IO uint32_t TID1;

757 __IO uint32_t TDA1;

758 __IO uint32_t TDB1;

759 __IO uint32_t TFI2;

760 __IO uint32_t TID2;

761 __IO uint32_t TDA2;

762 __IO uint32_t TDB2;

763 __IO uint32_t TFI3;

764 __IO uint32_t TID3;

765 __IO uint32_t TDA3;

766 __IO uint32_t TDB3;

767 } CAN_TypeDef;

768

769 /*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/

770 typedef struct /* Common Registers */

771 {

772 __I uint32_t DMACIntStat;

773 __I uint32_t DMACIntTCStat;

774 __O uint32_t DMACIntTCClear;

775 __I uint32_t DMACIntErrStat;

776 __O uint32_t DMACIntErrClr;

777 __I uint32_t DMACRawIntTCStat;

778 __I uint32_t DMACRawIntErrStat;

779 __I uint32_t DMACEnbldChns;

780 __IO uint32_t DMACSoftBReq;

781 __IO uint32_t DMACSoftSReq;

782 __IO uint32_t DMACSoftLBReq;

783 __IO uint32_t DMACSoftLSReq;

784 __IO uint32_t DMACConfig;

785 __IO uint32_t DMACSync;

786 } GPDMA_TypeDef;

787

788 typedef struct /* Channel Registers */

789 {

790 __IO uint32_t DMACCSrcAddr;

791 __IO uint32_t DMACCDestAddr;

792 __IO uint32_t DMACCLLI;

793 __IO uint32_t DMACCControl;

794 __IO uint32_t DMACCConfig;

795 } GPDMACH_TypeDef;

796

797 /*------------- Universal Serial Bus (USB) -----------------------------------*/

798 typedef struct

799 {

800 __I uint32_t HcRevision; /* USB Host Registers */

801 __IO uint32_t HcControl;

802 __IO uint32_t HcCommandStatus;

803 __IO uint32_t HcInterruptStatus;

804 __IO uint32_t HcInterruptEnable;

805 __IO uint32_t HcInterruptDisable;

806 __IO uint32_t HcHCCA;

807 __I uint32_t HcPeriodCurrentED;

808 __IO uint32_t HcControlHeadED;

809 __IO uint32_t HcControlCurrentED;

810 __IO uint32_t HcBulkHeadED;

811 __IO uint32_t HcBulkCurrentED;

812 __I uint32_t HcDoneHead;

813 __IO uint32_t HcFmInterval;

814 __I uint32_t HcFmRemaining;

815 __I uint32_t HcFmNumber;

816 __IO uint32_t HcPeriodicStart;

817 __IO uint32_t HcLSTreshold;

818 __IO uint32_t HcRhDescriptorA;

819 __IO uint32_t HcRhDescriptorB;

820 __IO uint32_t HcRhStatus;

821 __IO uint32_t HcRhPortStatus1;

822 __IO uint32_t HcRhPortStatus2;

823 uint32_t RESERVED0[40];

824 __I uint32_t Module_ID;

825

826 __I uint32_t OTGIntSt; /* USB On-The-Go Registers */

827 __IO uint32_t OTGIntEn;

828 __O uint32_t OTGIntSet;

829 __O uint32_t OTGIntClr;

830 __IO uint32_t OTGStCtrl;

831 __IO uint32_t OTGTmr;

832 uint32_t RESERVED1[58];

833

834 __I uint32_t USBDevIntSt; /* USB Device Interrupt Registers */

835 __IO uint32_t USBDevIntEn;

836 __O uint32_t USBDevIntClr;

837 __O uint32_t USBDevIntSet;

838

839 __O uint32_t USBCmdCode; /* USB Device SIE Command Registers */

840 __I uint32_t USBCmdData;

841

842 __I uint32_t USBRxData; /* USB Device Transfer Registers */

843 __O uint32_t USBTxData;

844 __I uint32_t USBRxPLen;

845 __O uint32_t USBTxPLen;

846 __IO uint32_t USBCtrl;

847 __O uint32_t USBDevIntPri;

848

849 __I uint32_t USBEpIntSt; /* USB Device Endpoint Interrupt Regs */

850 __IO uint32_t USBEpIntEn;

851 __O uint32_t USBEpIntClr;

852 __O uint32_t USBEpIntSet;

853 __O uint32_t USBEpIntPri;

854

855 __IO uint32_t USBReEp; /* USB Device Endpoint Realization Reg*/

856 __O uint32_t USBEpInd;

857 __IO uint32_t USBMaxPSize;

858

859 __I uint32_t USBDMARSt; /* USB Device DMA Registers */

860 __O uint32_t USBDMARClr;

861 __O uint32_t USBDMARSet;

862 uint32_t RESERVED2[9];

863 __IO uint32_t USBUDCAH;

864 __I uint32_t USBEpDMASt;

865 __O uint32_t USBEpDMAEn;

866 __O uint32_t USBEpDMADis;

867 __I uint32_t USBDMAIntSt;

868 __IO uint32_t USBDMAIntEn;

869 uint32_t RESERVED3[2];

870 __I uint32_t USBEoTIntSt;

871 __O uint32_t USBEoTIntClr;

872 __O uint32_t USBEoTIntSet;

873 __I uint32_t USBNDDRIntSt;

874 __O uint32_t USBNDDRIntClr;

875 __O uint32_t USBNDDRIntSet;

876 __I uint32_t USBSysErrIntSt;

877 __O uint32_t USBSysErrIntClr;

878 __O uint32_t USBSysErrIntSet;

879 uint32_t RESERVED4[15];

880

881 __I uint32_t I2C_RX; /* USB OTG I2C Registers */

882 __O uint32_t I2C_WO;

883 __I uint32_t I2C_STS;

884 __IO uint32_t I2C_CTL;

885 __IO uint32_t I2C_CLKHI;

886 __O uint32_t I2C_CLKLO;

887 uint32_t RESERVED5[823];

888

889 union {

890 __IO uint32_t USBClkCtrl; /* USB Clock Control Registers */

891 __IO uint32_t OTGClkCtrl;

892 } ;

893 union {

894 __I uint32_t USBClkSt;

895 __I uint32_t OTGClkSt;

896 };

897 } USB_TypeDef;

898

899 /*------------- Ethernet Media Access Controller (EMAC) ----------------------*/

900 typedef struct

901 {

902 __IO uint32_t MAC1; /* MAC Registers */

903 __IO uint32_t MAC2;

904 __IO uint32_t IPGT;

905 __IO uint32_t IPGR;

906 __IO uint32_t CLRT;

907 __IO uint32_t MAXF;

908 __IO uint32_t SUPP;

909 __IO uint32_t TEST;

910 __IO uint32_t MCFG;

911 __IO uint32_t MCMD;

912 __IO uint32_t MADR;

913 __O uint32_t MWTD;

914 __I uint32_t MRDD;

915 __I uint32_t MIND;

916 uint32_t RESERVED0[2];

917 __IO uint32_t SA0;

918 __IO uint32_t SA1;

919 __IO uint32_t SA2;

920 uint32_t RESERVED1[45];

921 __IO uint32_t Command; /* Control Registers */

922 __I uint32_t Status;

923 __IO uint32_t RxDescriptor;

924 __IO uint32_t RxStatus;

925 __IO uint32_t RxDescriptorNumber;

926 __I uint32_t RxProduceIndex;

927 __IO uint32_t RxConsumeIndex;

928 __IO uint32_t TxDescriptor;

929 __IO uint32_t TxStatus;

930 __IO uint32_t TxDescriptorNumber;

931 __IO uint32_t TxProduceIndex;

932 __I uint32_t TxConsumeIndex;

933 uint32_t RESERVED2[10];

934 __I uint32_t TSV0;

935 __I uint32_t TSV1;

936 __I uint32_t RSV;

937 uint32_t RESERVED3[3];

938 __IO uint32_t FlowControlCounter;

939 __I uint32_t FlowControlStatus;

940 uint32_t RESERVED4[34];

941 __IO uint32_t RxFilterCtrl; /* Rx Filter Registers */

942 __IO uint32_t RxFilterWoLStatus;

943 __IO uint32_t RxFilterWoLClear;

944 uint32_t RESERVED5;

945 __IO uint32_t HashFilterL;

946 __IO uint32_t HashFilterH;

947 uint32_t RESERVED6[882];

948 __I uint32_t IntStatus; /* Module Control Registers */

949 __IO uint32_t IntEnable;

950 __O uint32_t IntClear;

951 __O uint32_t IntSet;

952 uint32_t RESERVED7;

953 __IO uint32_t PowerDown;

954 uint32_t RESERVED8;

955 __IO uint32_t Module_ID;

956 } EMAC_TypeDef;

957

958

959 /******************************************************************************/

960 /* Peripheral memory map */

961 /******************************************************************************/

962 /* Base addresses */

963 #define FLASH_BASE (0x00000000UL)

964 #define RAM_BASE (0x10000000UL)

965 #define GPIO_BASE (0x2009C000UL)

966 #define APB0_BASE (0x40000000UL)

967 #define APB1_BASE (0x40080000UL)

968 #define AHB_BASE (0x50000000UL)

969 #define CM3_BASE (0xE0000000UL)

970

971 /* APB0 peripherals */

972 #define WDT_BASE (APB0_BASE + 0x00000)

973 #define TIM0_BASE (APB0_BASE + 0x04000)

974 #define TIM1_BASE (APB0_BASE + 0x08000)

975 #define UART0_BASE (APB0_BASE + 0x0C000)

976 #define UART1_BASE (APB0_BASE + 0x10000)

977 #define PWM1_BASE (APB0_BASE + 0x18000)

978 #define I2C0_BASE (APB0_BASE + 0x1C000)

979 #define SPI_BASE (APB0_BASE + 0x20000)

980 #define RTC_BASE (APB0_BASE + 0x24000)

981 #define GPIOINT_BASE (APB0_BASE + 0x28080)

982 #define PINCON_BASE (APB0_BASE + 0x2C000)

983 #define SSP1_BASE (APB0_BASE + 0x30000)

984 #define ADC_BASE (APB0_BASE + 0x34000)

985 #define CANAF_RAM_BASE (APB0_BASE + 0x38000)

986 #define CANAF_BASE (APB0_BASE + 0x3C000)

987 #define CANCR_BASE (APB0_BASE + 0x40000)

988 #define CAN1_BASE (APB0_BASE + 0x44000)

989 #define CAN2_BASE (APB0_BASE + 0x48000)

990 #define I2C1_BASE (APB0_BASE + 0x5C000)

991

992 /* APB1 peripherals */

993 #define SSP0_BASE (APB1_BASE + 0x08000)

994 #define DAC_BASE (APB1_BASE + 0x0C000)

995 #define TIM2_BASE (APB1_BASE + 0x10000)

996 #define TIM3_BASE (APB1_BASE + 0x14000)

997 #define UART2_BASE (APB1_BASE + 0x18000)

998 #define UART3_BASE (APB1_BASE + 0x1C000)

999 #define I2C2_BASE (APB1_BASE + 0x20000)

1000 #define I2S_BASE (APB1_BASE + 0x28000)

1001 #define RIT_BASE (APB1_BASE + 0x30000)

1002 #define MCPWM_BASE (APB1_BASE + 0x38000)

1003 #define QEI_BASE (APB1_BASE + 0x3C000)

1004 #define SC_BASE (APB1_BASE + 0x7C000)

1005

1006 /* AHB peripherals */

1007 #define EMAC_BASE (AHB_BASE + 0x00000)

1008 #define GPDMA_BASE (AHB_BASE + 0x04000)

1009 #define GPDMACH0_BASE (AHB_BASE + 0x04100)

1010 #define GPDMACH1_BASE (AHB_BASE + 0x04120)

1011 #define GPDMACH2_BASE (AHB_BASE + 0x04140)

1012 #define GPDMACH3_BASE (AHB_BASE + 0x04160)

1013 #define GPDMACH4_BASE (AHB_BASE + 0x04180)

1014 #define GPDMACH5_BASE (AHB_BASE + 0x041A0)

1015 #define GPDMACH6_BASE (AHB_BASE + 0x041C0)

1016 #define GPDMACH7_BASE (AHB_BASE + 0x041E0)

1017 #define USB_BASE (AHB_BASE + 0x0C000)

1018

1019 /* GPIOs */

1020 #define GPIO0_BASE (GPIO_BASE + 0x00000)

1021 #define GPIO1_BASE (GPIO_BASE + 0x00020)

1022 #define GPIO2_BASE (GPIO_BASE + 0x00040)

1023 #define GPIO3_BASE (GPIO_BASE + 0x00060)

1024 #define GPIO4_BASE (GPIO_BASE + 0x00080)

1025

1026

1027 /******************************************************************************/

1028 /* Peripheral declaration */

1029 /******************************************************************************/

1030 #define SC (( SC_TypeDef *) SC_BASE)

1031 #define GPIO0 (( GPIO_TypeDef *) GPIO0_BASE)

1032 #define GPIO1 (( GPIO_TypeDef *) GPIO1_BASE)

1033 #define GPIO2 (( GPIO_TypeDef *) GPIO2_BASE)

1034 #define GPIO3 (( GPIO_TypeDef *) GPIO3_BASE)

1035 #define GPIO4 (( GPIO_TypeDef *) GPIO4_BASE)

1036 #define WDT (( WDT_TypeDef *) WDT_BASE)

1037 #define TIM0 (( TIM_TypeDef *) TIM0_BASE)

1038 #define TIM1 (( TIM_TypeDef *) TIM1_BASE)

1039 #define TIM2 (( TIM_TypeDef *) TIM2_BASE)

1040 #define TIM3 (( TIM_TypeDef *) TIM3_BASE)

1041 #define RIT (( RIT_TypeDef *) RIT_BASE)

1042 #define UART0 (( UART_TypeDef *) UART0_BASE)

1043 #define UART1 (( UART1_TypeDef *) UART1_BASE)

1044 #define UART2 (( UART_TypeDef *) UART2_BASE)

1045 #define UART3 (( UART_TypeDef *) UART3_BASE)

1046 #define PWM1 (( PWM_TypeDef *) PWM1_BASE)

1047 #define I2C0 (( I2C_TypeDef *) I2C0_BASE)

1048 #define I2C1 (( I2C_TypeDef *) I2C1_BASE)

1049 #define I2C2 (( I2C_TypeDef *) I2C2_BASE)

1050 #define I2S (( I2S_TypeDef *) I2S_BASE)

1051 #define SPI (( SPI_TypeDef *) SPI_BASE)

1052 #define RTC (( RTC_TypeDef *) RTC_BASE)

1053 #define GPIOINT (( GPIOINT_TypeDef *) GPIOINT_BASE)

1054 #define PINCON (( PINCON_TypeDef *) PINCON_BASE)

1055 #define SSP0 (( SSP_TypeDef *) SSP0_BASE)

1056 #define SSP1 (( SSP_TypeDef *) SSP1_BASE)

1057 #define ADC (( ADC_TypeDef *) ADC_BASE)

1058 #define DAC (( DAC_TypeDef *) DAC_BASE)

1059 #define CANAF_RAM ((CANAF_RAM_TypeDef *) CANAF_RAM_BASE)

1060 #define CANAF (( CANAF_TypeDef *) CANAF_BASE)

1061 #define CANCR (( CANCR_TypeDef *) CANCR_BASE)

1062 #define CAN1 (( CAN_TypeDef *) CAN1_BASE)

1063 #define CAN2 (( CAN_TypeDef *) CAN2_BASE)

1064 #define MCPWM (( MCPWM_TypeDef *) MCPWM_BASE)

1065 #define QEI (( QEI_TypeDef *) QEI_BASE)

1066 #define EMAC (( EMAC_TypeDef *) EMAC_BASE)

1067 #define GPDMA (( GPDMA_TypeDef *) GPDMA_BASE)

1068 #define GPDMACH0 (( GPDMACH_TypeDef *) GPDMACH0_BASE)

1069 #define GPDMACH1 (( GPDMACH_TypeDef *) GPDMACH1_BASE)

1070 #define GPDMACH2 (( GPDMACH_TypeDef *) GPDMACH2_BASE)

1071 #define GPDMACH3 (( GPDMACH_TypeDef *) GPDMACH3_BASE)

1072 #define GPDMACH4 (( GPDMACH_TypeDef *) GPDMACH4_BASE)

1073 #define GPDMACH5 (( GPDMACH_TypeDef *) GPDMACH5_BASE)

1074 #define GPDMACH6 (( GPDMACH_TypeDef *) GPDMACH6_BASE)

1075 #define GPDMACH7 (( GPDMACH_TypeDef *) GPDMACH7_BASE)

1076 #define USB (( USB_TypeDef *) USB_BASE)

1077

1078 #endif // __LPC17xx_H__

1079

1080

1081 #endif