begriffs open source - cmsis-freertos/blob - Demo/ColdFire_MCF52221_CodeWarrior/headers/MCF52221

1 /* Coldfire C Header File

2 * Copyright Freescale Semiconductor Inc

4 *

5 * 2008/05/23 Revision: 0.95

6 *

7 * (c) Copyright UNIS, a.s. 1997-2008

8 * UNIS, a.s.

9 * Jundrovska 33

10 * 624 00 Brno

11 * Czech Republic

12 * http : www.processorexpert.com

13 * mail : info@processorexpert.com

14 */

15

16 #ifndef __MCF52221_SCM_H__

17 #define __MCF52221_SCM_H__

18

19

20 /*********************************************************************

21 *

22 * System Control Module (SCM)

23 *

24 *********************************************************************/

25

26 /* Register read/write macros */

27 #define MCF_SCM_RAMBAR (*(vuint32*)(0x40000008))

28 #define MCF_SCM_PPMRH (*(vuint32*)(0x4000000C))

29 #define MCF_SCM_CRSR (*(vuint8 *)(0x40000010))

30 #define MCF_SCM_CWCR (*(vuint8 *)(0x40000011))

31 #define MCF_SCM_CWSR (*(vuint8 *)(0x40000013))

32 #define MCF_SCM_DMAREQC (*(vuint32*)(0x40000014))

33 #define MCF_SCM_PPMRL (*(vuint32*)(0x40000018))

34 #define MCF_SCM_MPARK (*(vuint32*)(0x4000001C))

35 #define MCF_SCM_MPR (*(vuint8 *)(0x40000020))

36 #define MCF_SCM_PPMRS (*(vuint8 *)(0x40000021))

37 #define MCF_SCM_PPMRC (*(vuint8 *)(0x40000022))

38 #define MCF_SCM_IPSBMT (*(vuint8 *)(0x40000023))

39 #define MCF_SCM_PACR0 (*(vuint8 *)(0x40000024))

40 #define MCF_SCM_PACR1 (*(vuint8 *)(0x40000025))

41 #define MCF_SCM_PACR2 (*(vuint8 *)(0x40000026))

42 #define MCF_SCM_PACR3 (*(vuint8 *)(0x40000027))

43 #define MCF_SCM_PACR4 (*(vuint8 *)(0x40000028))

44 #define MCF_SCM_PACR5 (*(vuint8 *)(0x40000029))

45 #define MCF_SCM_PACR6 (*(vuint8 *)(0x4000002A))

46 #define MCF_SCM_PACR7 (*(vuint8 *)(0x4000002B))

47 #define MCF_SCM_PACR8 (*(vuint8 *)(0x4000002C))

48 #define MCF_SCM_GPACR0 (*(vuint8 *)(0x40000030))

49 #define MCF_SCM_GPACR1 (*(vuint8 *)(0x40000031))

50 #define MCF_SCM_PACR(x) (*(vuint8 *)(0x40000024 + ((x)*0x1)))

51 #define MCF_SCM_GPACR(x) (*(vuint8 *)(0x40000030 + ((x)*0x1)))

52

53 /* Other macros */

54 #define MCF_SCM_IPSBAR (*(vuint32*)(0x40000000))

55 #define MCF_SCM_IPSBAR_V (0x1)

56 #define MCF_SCM_IPSBAR_BA(x) ((x)&0xC0000000)

57

58

59 /* Bit definitions and macros for MCF_SCM_RAMBAR */

60 #define MCF_SCM_RAMBAR_BDE (0x200)

61 #define MCF_SCM_RAMBAR_BA(x) ((x)&0xFFFF0000)

62

63 /* Bit definitions and macros for MCF_SCM_PPMRH */

64 #define MCF_SCM_PPMRH_CDPORTS (0x1)

65 #define MCF_SCM_PPMRH_CDEPORT (0x2)

66 #define MCF_SCM_PPMRH_CDPIT0 (0x8)

67 #define MCF_SCM_PPMRH_CDPIT1 (0x10)

68 #define MCF_SCM_PPMRH_CDADC (0x80)

69 #define MCF_SCM_PPMRH_CDGPT (0x100)

70 #define MCF_SCM_PPMRH_CDPWM (0x200)

71 #define MCF_SCM_PPMRH_CDFCAN (0x400)

72 #define MCF_SCM_PPMRH_CDCFM (0x800)

73

74 /* Bit definitions and macros for MCF_SCM_CRSR */

75 #define MCF_SCM_CRSR_EXT (0x80)

76

77 /* Bit definitions and macros for MCF_SCM_CWCR */

78 #define MCF_SCM_CWCR_CWTIF (0x1)

79 #define MCF_SCM_CWCR_CWTAVAL (0x2)

80 #define MCF_SCM_CWCR_CWTA (0x4)

81 #define MCF_SCM_CWCR_CWT(x) (((x)&0x7)<<0x3)

82 #define MCF_SCM_CWCR_CWT_2_9 (0)

83 #define MCF_SCM_CWCR_CWT_2_11 (0x8)

84 #define MCF_SCM_CWCR_CWT_2_13 (0x10)

85 #define MCF_SCM_CWCR_CWT_2_15 (0x18)

86 #define MCF_SCM_CWCR_CWT_2_19 (0x20)

87 #define MCF_SCM_CWCR_CWT_2_23 (0x28)

88 #define MCF_SCM_CWCR_CWT_2_27 (0x30)

89 #define MCF_SCM_CWCR_CWT_2_31 (0x38)

90 #define MCF_SCM_CWCR_CWRI (0x40)

91 #define MCF_SCM_CWCR_CWE (0x80)

92

93 /* Bit definitions and macros for MCF_SCM_CWSR */

94 #define MCF_SCM_CWSR_CWSR(x) (((x)&0xFF)<<0)

95

96 /* Bit definitions and macros for MCF_SCM_DMAREQC */

97 #define MCF_SCM_DMAREQC_DMAC0(x) (((x)&0xF)<<0)

98 #define MCF_SCM_DMAREQC_DMAC1(x) (((x)&0xF)<<0x4)

99 #define MCF_SCM_DMAREQC_DMAC2(x) (((x)&0xF)<<0x8)

100 #define MCF_SCM_DMAREQC_DMAC3(x) (((x)&0xF)<<0xC)

101

102 /* Bit definitions and macros for MCF_SCM_PPMRL */

103 #define MCF_SCM_PPMRL_CDG (0x2)

104 #define MCF_SCM_PPMRL_CDDMA (0x10)

105 #define MCF_SCM_PPMRL_CDUART0 (0x20)

106 #define MCF_SCM_PPMRL_CDUART1 (0x40)

107 #define MCF_SCM_PPMRL_CDUART2 (0x80)

108 #define MCF_SCM_PPMRL_CDI2C (0x200)

109 #define MCF_SCM_PPMRL_CDQSPI (0x400)

110 #define MCF_SCM_PPMRL_CDTMR0 (0x2000)

111 #define MCF_SCM_PPMRL_CDTMR1 (0x4000)

112 #define MCF_SCM_PPMRL_CDTMR2 (0x8000)

113 #define MCF_SCM_PPMRL_CDTMR3 (0x10000)

114 #define MCF_SCM_PPMRL_CDINTC0 (0x20000)

115

116 /* Bit definitions and macros for MCF_SCM_MPARK */

117 #define MCF_SCM_MPARK_LCKOUT_TIME(x) (((x)&0xF)<<0x8)

118 #define MCF_SCM_MPARK_PRKLAST (0x1000)

119 #define MCF_SCM_MPARK_TIMEOUT (0x2000)

120 #define MCF_SCM_MPARK_FIXED (0x4000)

121 #define MCF_SCM_MPARK_M0_PRTY(x) (((x)&0x3)<<0x12)

122 #define MCF_SCM_MPARK_M2_PRTY(x) (((x)&0x3)<<0x14)

123 #define MCF_SCM_MPARK_BCR24BIT (0x1000000)

124 #define MCF_SCM_MPARK_M2_P_EN (0x2000000)

125

126 /* Bit definitions and macros for MCF_SCM_MPR */

127 #define MCF_SCM_MPR_MPR(x) (((x)&0xF)<<0)

128

129 /* Bit definitions and macros for MCF_SCM_PPMRS */

130 #define MCF_SCM_PPMRS_PPMRS(x) (((x)&0x7F)<<0)

131 #define MCF_SCM_PPMRS_DISABLE_ALL (0x40)

132 #define MCF_SCM_PPMRS_DISABLE_CFM (0x2B)

133 #define MCF_SCM_PPMRS_DISABLE_CAN (0x2A)

134 #define MCF_SCM_PPMRS_DISABLE_PWM (0x29)

135 #define MCF_SCM_PPMRS_DISABLE_GPT (0x28)

136 #define MCF_SCM_PPMRS_DISABLE_ADC (0x27)

137 #define MCF_SCM_PPMRS_DISABLE_PIT1 (0x24)

138 #define MCF_SCM_PPMRS_DISABLE_PIT0 (0x23)

139 #define MCF_SCM_PPMRS_DISABLE_EPORT (0x21)

140 #define MCF_SCM_PPMRS_DISABLE_PORTS (0x20)

141 #define MCF_SCM_PPMRS_DISABLE_INTC (0x11)

142 #define MCF_SCM_PPMRS_DISABLE_DTIM3 (0x10)

143 #define MCF_SCM_PPMRS_DISABLE_DTIM2 (0xF)

144 #define MCF_SCM_PPMRS_DISABLE_DTIM1 (0xE)

145 #define MCF_SCM_PPMRS_DISABLE_DTIM0 (0xD)

146 #define MCF_SCM_PPMRS_DISABLE_QSPI (0xA)

147 #define MCF_SCM_PPMRS_DISABLE_I2C (0x9)

148 #define MCF_SCM_PPMRS_DISABLE_UART2 (0x7)

149 #define MCF_SCM_PPMRS_DISABLE_UART1 (0x6)

150 #define MCF_SCM_PPMRS_DISABLE_UART0 (0x5)

151 #define MCF_SCM_PPMRS_DISABLE_DMA (0x4)

152 #define MCF_SCM_PPMRS_SET_CDG (0x1)

153

154 /* Bit definitions and macros for MCF_SCM_PPMRC */

155 #define MCF_SCM_PPMRC_PPMRC(x) (((x)&0x7F)<<0)

156 #define MCF_SCM_PPMRC_ENABLE_ALL (0x40)

157 #define MCF_SCM_PPMRC_ENABLE_CFM (0x2B)

158 #define MCF_SCM_PPMRC_ENABLE_CAN (0x2A)

159 #define MCF_SCM_PPMRC_ENABLE_PWM (0x29)

160 #define MCF_SCM_PPMRC_ENABLE_GPT (0x28)

161 #define MCF_SCM_PPMRC_ENABLE_ADC (0x27)

162 #define MCF_SCM_PPMRC_ENABLE_PIT1 (0x24)

163 #define MCF_SCM_PPMRC_ENABLE_PIT0 (0x23)

164 #define MCF_SCM_PPMRC_ENABLE_EPORT (0x21)

165 #define MCF_SCM_PPMRC_ENABLE_PORTS (0x20)

166 #define MCF_SCM_PPMRC_ENABLE_INTC (0x11)

167 #define MCF_SCM_PPMRC_ENABLE_DTIM3 (0x10)

168 #define MCF_SCM_PPMRC_ENABLE_DTIM2 (0xF)

169 #define MCF_SCM_PPMRC_ENABLE_DTIM1 (0xE)

170 #define MCF_SCM_PPMRC_ENABLE_DTIM0 (0xD)

171 #define MCF_SCM_PPMRC_ENABLE_QSPI (0xA)

172 #define MCF_SCM_PPMRC_ENABLE_I2C (0x9)

173 #define MCF_SCM_PPMRC_ENABLE_UART2 (0x7)

174 #define MCF_SCM_PPMRC_ENABLE_UART1 (0x6)

175 #define MCF_SCM_PPMRC_ENABLE_UART0 (0x5)

176 #define MCF_SCM_PPMRC_ENABLE_DMA (0x4)

177 #define MCF_SCM_PPMRC_CLEAR_CDG (0x1)

178

179 /* Bit definitions and macros for MCF_SCM_IPSBMT */

180 #define MCF_SCM_IPSBMT_BMT(x) (((x)&0x7)<<0)

181 #define MCF_SCM_IPSBMT_BMT_CYCLES_1024 (0)

182 #define MCF_SCM_IPSBMT_BMT_CYCLES_512 (0x1)

183 #define MCF_SCM_IPSBMT_BMT_CYCLES_256 (0x2)

184 #define MCF_SCM_IPSBMT_BMT_CYCLES_128 (0x3)

185 #define MCF_SCM_IPSBMT_BMT_CYCLES_64 (0x4)

186 #define MCF_SCM_IPSBMT_BMT_CYCLES_32 (0x5)

187 #define MCF_SCM_IPSBMT_BMT_CYCLES_16 (0x6)

188 #define MCF_SCM_IPSBMT_BMT_CYCLES_8 (0x7)

189 #define MCF_SCM_IPSBMT_BME (0x8)

190

191 /* Bit definitions and macros for MCF_SCM_PACR */

192 #define MCF_SCM_PACR_ACCESS_CTRL0(x) (((x)&0x7)<<0)

193 #define MCF_SCM_PACR_LOCK0 (0x8)

194 #define MCF_SCM_PACR_ACCESS_CTRL1(x) (((x)&0x7)<<0x4)

195 #define MCF_SCM_PACR_LOCK1 (0x80)

196

197 /* Bit definitions and macros for MCF_SCM_GPACR */

198 #define MCF_SCM_GPACR_ACCESS_CTRL(x) (((x)&0xF)<<0)

199 #define MCF_SCM_GPACR_LOCK (0x80)

200

201

202 #endif /* __MCF52221_SCM_H__ */