begriffs open source - cmsis-freertos/blob - Demo/ColdFire_MCF52259_CodeWarrior/cpu/mcf5225x

1 /*

2 * File: mcf5225x_lo.s

3 * Purpose: Low-level routines for the MCF5225x.

4 *

5 * Notes:

6 *

7 * License: All software covered by license agreement in -

8 * docs/Freescale_Software_License.pdf

9 */

11 #define mcf5225x_init _mcf5225x_init

12 #define common_startup _common_startup

13 #define cpu_startup _cpu_startup

14 #define main _main

15 #define __IPSBAR ___IPSBAR

16 #define __SRAM ___SRAM

17 #define __FLASH ___FLASH

18 #define __SP_INIT ___SP_INIT

20 .extern __IPSBAR

21 .extern __SRAM

22 .extern __FLASH

23 .extern __SP_INIT

24 .extern mcf5225x_init

25 .extern common_startup

26 .extern cpu_startup

27 .extern main

29 .global asm_startmeup

30 .global _asm_startmeup

31 .global d0_reset

32 .global _d0_reset

33 .global d1_reset

34 .global _d1_reset

36 .data

38 d0_reset:

39 _d0_reset: .long 0

40 d1_reset:

41 _d1_reset: .long 0

43 .text

45 /********************************************************************

46 *

47 * This is the main entry point upon hard reset. The memory map is

48 * setup based on linker file definitions, then the higher level

49 * system initialization routine is called. Finally, we jump to the

50 * "main" process.

51 */

52 asm_startmeup:

53 _asm_startmeup:

55 move.w #0x2700,sr

57 /* Save off reset values of D0 and D1 */

58 move.l d0,d6

59 move.l d1,d7

61 /* Initialize RAMBAR1: locate SRAM and validate it */

62 move.l #__SRAM,d0

63 andi.l #0xFFFF0000,d0

64 add.l #0x21,d0

65 movec d0,RAMBAR1

67 /* Locate Stack Pointer */

68 move.l #__SP_INIT,sp

70 /* Initialize IPSBAR */

71 move.l #__IPSBAR,d0

72 add.l #0x1,d0

73 move.l d0,0x40000000

75 /* Initialize FLASHBAR */

76 move.l #__FLASH,d0

77 cmp.l #0x00000000,d0

78 bne change_flashbar

79 add.l #0x61,d0

80 movec d0,RAMBAR0

82 _continue_startup:

84 /* Locate Stack Pointer */

85 move.l #__SP_INIT,sp

87 /* Initialize the system */

88 jsr mcf5225x_init

90 /* Common startup code */

91 //jsr common_startup

93 /* Save off intial D0 and D1 to RAM */

94 move.l d6,d0_reset

95 move.l d7,d1_reset

97 /* CPU specific startup code */

98 //jsr cpu_startup

100 /* Jump to the main process */

101 jsr main

102

103 bra .

104 nop

105 nop

106 halt

107

108 change_flashbar:

109 /*

110 * The following sequence is used to set FLASHBAR. Since we may

111 * be executing from Flash, we must put the routine into SRAM for

112 * execution and then jump back to Flash using the new address.

113 *

114 * The following instructions are coded into the SRAM:

115 *

116 * move.l #(__FLASH + 0x21),d0

117 * movec d0, RAMBAR0

118 * jmp _continue_startup

119 *

120 * An arbitrary SRAM address is chosen until the real address

121 * can be loaded.

122 *

123 * This routine is not necessary if the default Flash address

124 * (0x00000000) is used.

125 *

126 * If running in SRAM, change_flashbar should not be executed

127 */

128

129 move.l #__SRAM,a0

130

131 /* Code "move.l #(__FLASH + 0x21),d0" into SRAM */

132 move.w #0x203C,d0

133 move.w d0,(a0)+

134 move.l #__FLASH,d0

135 add.l #0x21,d0

136 move.l d0,(a0)+

137

138 /* Code "movec d0,FLASHBAR" into SRAM */

139 move.l #0x4e7b0C04,d0

140 move.l d0,(a0)+

141

142 /* Code "jmp _continue_startup" into SRAM */

143 move.w #0x4EF9,d0

144 move.w d0,(a0)+

145 move.l #_continue_startup,d0

146 move.l d0,(a0)+

147

148 /* Jump to code segment in internal SRAM */

149 jmp __SRAM

150

151 /********************************************************************/

152

153 .end