begriffs open source - cmsis-freertos/blob - Demo/WizNET_DEMO_GCC

1 /*

4

5 VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.

6

7 This file is part of the FreeRTOS distribution.

8

9 FreeRTOS is free software; you can redistribute it and/or modify it under

10 the terms of the GNU General Public License (version 2) as published by the

11 Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.

12

13 ***************************************************************************

14 >>! NOTE: The modification to the GPL is included to allow you to !<<

15 >>! distribute a combined work that includes FreeRTOS without being !<<

16 >>! obliged to provide the source code for proprietary components !<<

17 >>! outside of the FreeRTOS kernel. !<<

18 ***************************************************************************

19

20 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY

21 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS

22 FOR A PARTICULAR PURPOSE. Full license text is available on the following

23 link: http://www.freertos.org/a00114.html

24

25 ***************************************************************************

26 * *

27 * FreeRTOS provides completely free yet professionally developed, *

28 * robust, strictly quality controlled, supported, and cross *

29 * platform software that is more than just the market leader, it *

30 * is the industry's de facto standard. *

31 * *

32 * Help yourself get started quickly while simultaneously helping *

33 * to support the FreeRTOS project by purchasing a FreeRTOS *

34 * tutorial book, reference manual, or both: *

35 * http://www.FreeRTOS.org/Documentation *

36 * *

37 ***************************************************************************

38

39 http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading

40 the FAQ page "My application does not run, what could be wrong?". Have you

41 defined configASSERT()?

42

43 http://www.FreeRTOS.org/support - In return for receiving this top quality

44 embedded software for free we request you assist our global community by

45 participating in the support forum.

46

47 http://www.FreeRTOS.org/training - Investing in training allows your team to

48 be as productive as possible as early as possible. Now you can receive

49 FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers

50 Ltd, and the world's leading authority on the world's leading RTOS.

51

52 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,

53 including FreeRTOS+Trace - an indispensable productivity tool, a DOS

54 compatible FAT file system, and our tiny thread aware UDP/IP stack.

55

56 http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.

57 Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.

58

59 http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High

60 Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS

61 licenses offer ticketed support, indemnification and commercial middleware.

62

63 http://www.SafeRTOS.com - High Integrity Systems also provide a safety

64 engineered and independently SIL3 certified version for use in safety and

65 mission critical applications that require provable dependability.

66

67 1 tab == 4 spaces!

68 */

69

70

71 /* Standard includes. */

72 #include <stdlib.h>

73

74 /* Scheduler include files. */

75 #include "FreeRTOS.h"

76 #include "queue.h"

77 #include "semphr.h"

78

79 /* Application includes. */

80 #include "i2c.h"

81

82 /*-----------------------------------------------------------*/

83

84 /* Constants to setup the microcontroller IO. */

85 #define mainSDA_ENABLE ( ( unsigned long ) 0x0040 )

86 #define mainSCL_ENABLE ( ( unsigned long ) 0x0010 )

87

88 /* Bit definitions within the I2CONCLR register. */

89 #define i2cSTA_BIT ( ( unsigned char ) 0x20 )

90 #define i2cSI_BIT ( ( unsigned char ) 0x08 )

91 #define i2cSTO_BIT ( ( unsigned char ) 0x10 )

92

93 /* Constants required to setup the VIC. */

94 #define i2cI2C_VIC_CHANNEL ( ( unsigned long ) 0x0009 )

95 #define i2cI2C_VIC_CHANNEL_BIT ( ( unsigned long ) 0x0200 )

96 #define i2cI2C_VIC_ENABLE ( ( unsigned long ) 0x0020 )

97

98 /* Misc constants. */

99 #define i2cNO_BLOCK ( ( TickType_t ) 0 )

100 #define i2cQUEUE_LENGTH ( ( unsigned char ) 5 )

101 #define i2cEXTRA_MESSAGES ( ( unsigned char ) 2 )

102 #define i2cREAD_TX_LEN ( ( unsigned long ) 2 )

103 #define i2cACTIVE_MASTER_MODE ( ( unsigned char ) 0x40 )

104 #define i2cTIMERL ( 200 )

105 #define i2cTIMERH ( 200 )

106

107 /* Array of message definitions. See the header file for more information

108 on the structure members. There are two more places in the queue than as

109 defined by i2cQUEUE_LENGTH. This is to ensure that there is always a free

110 message available - one can be in the process of being transmitted and one

111 can be left free. */

112 static xI2CMessage xTxMessages[ i2cQUEUE_LENGTH + i2cEXTRA_MESSAGES ];

113

114 /* Function in the ARM part of the code used to create the queues. */

115 extern void vI2CISRCreateQueues( unsigned portBASE_TYPE uxQueueLength, QueueHandle_t *pxTxMessages, unsigned long **ppulBusFree );

116

117 /* Index to the next free message in the xTxMessages array. */

118 unsigned long ulNextFreeMessage = ( unsigned long ) 0;

119

120 /* Queue of messages that are waiting transmission. */

121 static QueueHandle_t xMessagesForTx;

122

123 /* Flag to indicate the state of the I2C ISR state machine. */

124 static unsigned long *pulBusFree;

125

126 /*-----------------------------------------------------------*/

127 void i2cMessage( const unsigned char * const pucMessage, long lMessageLength, unsigned char ucSlaveAddress, unsigned short usBufferAddress, unsigned long ulDirection, SemaphoreHandle_t xMessageCompleteSemaphore, TickType_t xBlockTime )

128 {

129 extern volatile xI2CMessage *pxCurrentMessage;

130 xI2CMessage *pxNextFreeMessage;

131 signed portBASE_TYPE xReturn;

132

133 portENTER_CRITICAL();

134 {

135 /* This message is guaranteed to be free as there are two more messages

136 than spaces in the queue allowing for one message to be in process of

137 being transmitted and one to be left free. */

138 pxNextFreeMessage = &( xTxMessages[ ulNextFreeMessage ] );

139

140 /* Fill the message with the data to be sent. */

141

142 /* Pointer to the actual data. Only a pointer is stored (i.e. the

143 actual data is not copied, so the data being pointed to must still

144 be valid when the message eventually gets sent (it may be queued for

145 a while. */

146 pxNextFreeMessage->pucBuffer = ( unsigned char * ) pucMessage;

147

148 /* This is the address of the I2C device we are going to transmit this

149 message to. */

150 pxNextFreeMessage->ucSlaveAddress = ucSlaveAddress | ( unsigned char ) ulDirection;

151

152 /* A semaphore can be used to allow the I2C ISR to indicate that the

153 message has been sent. This can be NULL if you don't want to wait for

154 the message transmission to complete. */

155 pxNextFreeMessage->xMessageCompleteSemaphore = xMessageCompleteSemaphore;

156

157 /* How many bytes are to be sent? */

158 pxNextFreeMessage->lMessageLength = lMessageLength;

159

160 /* The address within the WIZnet device to which the data will be

161 written. This could be the address of a register, or alternatively

162 a location within the WIZnet Tx buffer. */

163 pxNextFreeMessage->ucBufferAddressLowByte = ( unsigned char ) ( usBufferAddress & 0xff );

164

165 /* Second byte of the address. */

166 usBufferAddress >>= 8;

167 pxNextFreeMessage->ucBufferAddressHighByte = ( unsigned char ) ( usBufferAddress & 0xff );

168

169 /* Increment to the next message in the array - with a wrap around check. */

170 ulNextFreeMessage++;

171 if( ulNextFreeMessage >= ( i2cQUEUE_LENGTH + i2cEXTRA_MESSAGES ) )

172 {

173 ulNextFreeMessage = ( unsigned long ) 0;

174 }

175

176 /* Is the I2C interrupt in the middle of transmitting a message? */

177 if( *pulBusFree == ( unsigned long ) pdTRUE )

178 {

179 /* No message is currently being sent or queued to be sent. We

180 can start the ISR sending this message immediately. */

181 pxCurrentMessage = pxNextFreeMessage;

182

183 I2C_I2CONCLR = i2cSI_BIT;

184 I2C_I2CONSET = i2cSTA_BIT;

185

186 *pulBusFree = ( unsigned long ) pdFALSE;

187 }

188 else

189 {

190 /* The I2C interrupt routine is mid sending a message. Queue

191 this message ready to be sent. */

192 xReturn = xQueueSend( xMessagesForTx, &pxNextFreeMessage, xBlockTime );

193

194 /* We may have blocked while trying to queue the message. If this

195 was the case then the interrupt would have been enabled and we may

196 now find that the I2C interrupt routine is no longer sending a

197 message. */

198 if( ( *pulBusFree == ( unsigned long ) pdTRUE ) && ( xReturn == pdPASS ) )

199 {

200 /* Get the next message in the queue (this should be the

201 message we just posted) and start off the transmission

202 again. */

203 xQueueReceive( xMessagesForTx, &pxNextFreeMessage, i2cNO_BLOCK );

204 pxCurrentMessage = pxNextFreeMessage;

205

206 I2C_I2CONCLR = i2cSI_BIT;

207 I2C_I2CONSET = i2cSTA_BIT;

208

209 *pulBusFree = ( unsigned long ) pdFALSE;

210 }

211 }

212 }

213 portEXIT_CRITICAL();

214 }

215 /*-----------------------------------------------------------*/

216

217 void i2cInit( void )

218 {

219 extern void ( vI2C_ISR_Wrapper )( void );

220

221 /* Create the queue used to send messages to the ISR. */

222 vI2CISRCreateQueues( i2cQUEUE_LENGTH, &xMessagesForTx, &pulBusFree );

223

224 /* Configure the I2C hardware. */

225

226 I2C_I2CONCLR = 0xff;

227

228 PCB_PINSEL0 |= mainSDA_ENABLE;

229 PCB_PINSEL0 |= mainSCL_ENABLE;

230

231 I2C_I2SCLL = i2cTIMERL;

232 I2C_I2SCLH = i2cTIMERH;

233 I2C_I2CONSET = i2cACTIVE_MASTER_MODE;

234

235 portENTER_CRITICAL();

236 {

237 /* Setup the VIC for the i2c interrupt. */

238 VICIntSelect &= ~( i2cI2C_VIC_CHANNEL_BIT );

239 VICIntEnable |= i2cI2C_VIC_CHANNEL_BIT;

240 VICVectAddr2 = ( long ) vI2C_ISR_Wrapper;

241

242 VICVectCntl2 = i2cI2C_VIC_CHANNEL | i2cI2C_VIC_ENABLE;

243 }

244 portEXIT_CRITICAL();

245 }

246