1 /**************************************************************************//**
3 * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File
6 ******************************************************************************/
8 * Copyright (c) 2009-2023 Arm Limited. All rights reserved.
10 * SPDX-License-Identifier: Apache-2.0
12 * Licensed under the Apache License, Version 2.0 (the License); you may
13 * not use this file except in compliance with the License.
14 * You may obtain a copy of the License at
16 * www.apache.org/licenses/LICENSE-2.0
18 * Unless required by applicable law or agreed to in writing, software
19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 * See the License for the specific language governing permissions and
22 * limitations under the License.
25 #if defined ( __ICCARM__ )
26 #pragma system_include /* treat file as system include file for MISRA check */
27 #elif defined (__clang__)
28 #pragma clang system_header /* treat file as system include file */
29 #elif defined ( __GNUC__ )
30 #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */
33 #ifndef __CORE_CM23_H_GENERIC
34 #define __CORE_CM23_H_GENERIC
43 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
44 CMSIS violates the following MISRA-C:2004 rules:
46 \li Required Rule 8.5, object/function definition in header file.<br>
47 Function definitions in header files are used to allow 'inlining'.
49 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
50 Unions are used for effective representation of core registers.
52 \li Advisory Rule 19.7, Function-like macro defined.<br>
53 Function-like macros are used to allow more efficient code.
57 /*******************************************************************************
59 ******************************************************************************/
65 #include "cmsis_version.h"
67 /* CMSIS definitions */
68 #define __CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
69 #define __CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
70 #define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \
71 __CM23_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
73 #define __CORTEX_M (23U) /*!< Cortex-M Core */
75 /** __FPU_USED indicates whether an FPU is used or not.
76 This core does not support an FPU at all
80 #if defined ( __CC_ARM )
81 #if defined __TARGET_FPU_VFP
82 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
85 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
87 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
90 #elif defined (__ti__)
92 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
95 #elif defined ( __GNUC__ )
96 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
97 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
100 #elif defined ( __ICCARM__ )
101 #if defined __ARMVFP__
102 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
105 #elif defined ( __TI_ARM__ )
106 #if defined __TI_VFP_SUPPORT__
107 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
110 #elif defined ( __TASKING__ )
111 #if defined __FPU_VFP__
112 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
115 #elif defined ( __CSMC__ )
116 #if ( __CSMC__ & 0x400U)
117 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
122 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
129 #endif /* __CORE_CM23_H_GENERIC */
131 #ifndef __CMSIS_GENERIC
133 #ifndef __CORE_CM23_H_DEPENDANT
134 #define __CORE_CM23_H_DEPENDANT
140 /* check device defines and use defaults */
141 #if defined __CHECK_DEVICE_DEFINES
143 #define __CM23_REV 0x0000U
144 #warning "__CM23_REV not defined in device header file; using default!"
147 #ifndef __FPU_PRESENT
148 #define __FPU_PRESENT 0U
149 #warning "__FPU_PRESENT not defined in device header file; using default!"
152 #ifndef __MPU_PRESENT
153 #define __MPU_PRESENT 0U
154 #warning "__MPU_PRESENT not defined in device header file; using default!"
157 #ifndef __SAUREGION_PRESENT
158 #define __SAUREGION_PRESENT 0U
159 #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
162 #ifndef __VTOR_PRESENT
163 #define __VTOR_PRESENT 0U
164 #warning "__VTOR_PRESENT not defined in device header file; using default!"
167 #ifndef __NVIC_PRIO_BITS
168 #define __NVIC_PRIO_BITS 2U
169 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
172 #ifndef __Vendor_SysTickConfig
173 #define __Vendor_SysTickConfig 0U
174 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
177 #ifndef __ETM_PRESENT
178 #define __ETM_PRESENT 0U
179 #warning "__ETM_PRESENT not defined in device header file; using default!"
182 #ifndef __MTB_PRESENT
183 #define __MTB_PRESENT 0U
184 #warning "__MTB_PRESENT not defined in device header file; using default!"
189 /* IO definitions (access restrictions to peripheral registers) */
191 \defgroup CMSIS_glob_defs CMSIS Global Defines
193 <strong>IO Type Qualifiers</strong> are used
194 \li to specify the access to peripheral variables.
195 \li for automatic generation of peripheral register debug information.
198 #define __I volatile /*!< Defines 'read only' permissions */
200 #define __I volatile const /*!< Defines 'read only' permissions */
202 #define __O volatile /*!< Defines 'write only' permissions */
203 #define __IO volatile /*!< Defines 'read / write' permissions */
205 /* following defines should be used for structure members */
206 #define __IM volatile const /*! Defines 'read only' structure member permissions */
207 #define __OM volatile /*! Defines 'write only' structure member permissions */
208 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
210 /*@} end of group Cortex_M23 */
214 /*******************************************************************************
215 * Register Abstraction
216 Core Register contain:
220 - Core SysTick Register
221 - Core Debug Register
224 ******************************************************************************/
226 \defgroup CMSIS_core_register Defines and Type Definitions
227 \brief Type definitions and defines for Cortex-M processor based devices.
231 \ingroup CMSIS_core_register
232 \defgroup CMSIS_CORE Status and Control Registers
233 \brief Core Register type definitions.
238 \brief Union type to access the Application Program Status Register (APSR).
244 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
245 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
246 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
247 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
248 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
249 } b; /*!< Structure used for bit access */
250 uint32_t w; /*!< Type used for word access */
253 /* APSR Register Definitions */
254 #define APSR_N_Pos 31U /*!< APSR: N Position */
255 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
257 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
258 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
260 #define APSR_C_Pos 29U /*!< APSR: C Position */
261 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
263 #define APSR_V_Pos 28U /*!< APSR: V Position */
264 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
268 \brief Union type to access the Interrupt Program Status Register (IPSR).
274 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
275 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
276 } b; /*!< Structure used for bit access */
277 uint32_t w; /*!< Type used for word access */
280 /* IPSR Register Definitions */
281 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
282 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
286 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
292 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
293 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
294 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
295 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
296 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
297 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
298 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
299 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
300 } b; /*!< Structure used for bit access */
301 uint32_t w; /*!< Type used for word access */
304 /* xPSR Register Definitions */
305 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
306 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
308 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
309 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
311 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
312 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
314 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
315 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
317 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
318 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
320 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
321 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
325 \brief Union type to access the Control Registers (CONTROL).
331 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
332 uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
333 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
334 } b; /*!< Structure used for bit access */
335 uint32_t w; /*!< Type used for word access */
338 /* CONTROL Register Definitions */
339 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
340 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
342 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
343 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
345 /*@} end of group CMSIS_CORE */
349 \ingroup CMSIS_core_register
350 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
351 \brief Type definitions for the NVIC Registers
356 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
360 __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
361 uint32_t RESERVED0[16U];
362 __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
363 uint32_t RSERVED1[16U];
364 __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
365 uint32_t RESERVED2[16U];
366 __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
367 uint32_t RESERVED3[16U];
368 __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
369 uint32_t RESERVED4[16U];
370 __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
371 uint32_t RESERVED5[16U];
372 __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
375 /*@} end of group CMSIS_NVIC */
379 \ingroup CMSIS_core_register
380 \defgroup CMSIS_SCB System Control Block (SCB)
381 \brief Type definitions for the System Control Block Registers
386 \brief Structure type to access the System Control Block (SCB).
390 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
391 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
392 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
393 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
397 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
398 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
399 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
401 __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
402 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
405 /* SCB CPUID Register Definitions */
406 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
407 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
409 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
410 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
412 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
413 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
415 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
416 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
418 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
419 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
421 /* SCB Interrupt Control State Register Definitions */
422 #define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
423 #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
425 #define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
426 #define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
428 #define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
429 #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
431 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
432 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
434 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
435 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
437 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
438 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
440 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
441 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
443 #define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
444 #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
446 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
447 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
449 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
450 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
452 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
453 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
455 #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
456 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
458 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
459 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
461 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
462 /* SCB Vector Table Offset Register Definitions */
463 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
464 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
467 /* SCB Application Interrupt and Reset Control Register Definitions */
468 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
469 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
471 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
472 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
474 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
475 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
477 #define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
478 #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
480 #define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
481 #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
483 #define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
484 #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
486 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
487 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
489 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
490 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
492 /* SCB System Control Register Definitions */
493 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
494 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
496 #define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
497 #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
499 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
500 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
502 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
503 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
505 /* SCB Configuration Control Register Definitions */
506 #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
507 #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
509 #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
510 #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
512 #define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
513 #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
515 #define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
516 #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
518 #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
519 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
521 #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
522 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
524 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
525 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
527 #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
528 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
530 /* SCB System Handler Control and State Register Definitions */
531 #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
532 #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
534 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
535 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
537 #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
538 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
540 #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
541 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
543 #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
544 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
546 #define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
547 #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
549 #define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
550 #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
552 /*@} end of group CMSIS_SCB */
556 \ingroup CMSIS_core_register
557 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
558 \brief Type definitions for the System Timer Registers.
563 \brief Structure type to access the System Timer (SysTick).
567 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
568 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
569 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
570 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
573 /* SysTick Control / Status Register Definitions */
574 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
575 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
577 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
578 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
580 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
581 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
583 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
584 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
586 /* SysTick Reload Register Definitions */
587 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
588 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
590 /* SysTick Current Register Definitions */
591 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
592 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
594 /* SysTick Calibration Register Definitions */
595 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
596 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
598 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
599 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
601 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
602 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
604 /*@} end of group CMSIS_SysTick */
608 \ingroup CMSIS_core_register
609 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
610 \brief Type definitions for the Data Watchpoint and Trace (DWT)
615 \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
619 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
620 uint32_t RESERVED0[6U];
621 __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
622 __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
623 uint32_t RESERVED1[1U];
624 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
625 uint32_t RESERVED2[1U];
626 __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
627 uint32_t RESERVED3[1U];
628 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
629 uint32_t RESERVED4[1U];
630 __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
631 uint32_t RESERVED5[1U];
632 __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
633 uint32_t RESERVED6[1U];
634 __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
635 uint32_t RESERVED7[1U];
636 __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
637 uint32_t RESERVED8[1U];
638 __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
639 uint32_t RESERVED9[1U];
640 __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
641 uint32_t RESERVED10[1U];
642 __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
643 uint32_t RESERVED11[1U];
644 __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
645 uint32_t RESERVED12[1U];
646 __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
647 uint32_t RESERVED13[1U];
648 __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
649 uint32_t RESERVED14[1U];
650 __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
651 uint32_t RESERVED15[1U];
652 __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
653 uint32_t RESERVED16[1U];
654 __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
655 uint32_t RESERVED17[1U];
656 __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
657 uint32_t RESERVED18[1U];
658 __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
659 uint32_t RESERVED19[1U];
660 __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
661 uint32_t RESERVED20[1U];
662 __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
663 uint32_t RESERVED21[1U];
664 __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
665 uint32_t RESERVED22[1U];
666 __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
667 uint32_t RESERVED23[1U];
668 __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
669 uint32_t RESERVED24[1U];
670 __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
671 uint32_t RESERVED25[1U];
672 __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
673 uint32_t RESERVED26[1U];
674 __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
675 uint32_t RESERVED27[1U];
676 __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
677 uint32_t RESERVED28[1U];
678 __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
679 uint32_t RESERVED29[1U];
680 __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
681 uint32_t RESERVED30[1U];
682 __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
683 uint32_t RESERVED31[1U];
684 __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
687 /* DWT Control Register Definitions */
688 #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
689 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
691 #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
692 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
694 #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
695 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
697 #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
698 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
700 #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
701 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
703 /* DWT Comparator Function Register Definitions */
704 #define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
705 #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
707 #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
708 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
710 #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
711 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
713 #define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
714 #define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
716 #define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
717 #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
719 /*@}*/ /* end of group CMSIS_DWT */
723 \ingroup CMSIS_core_register
724 \defgroup CMSIS_TPI Trace Port Interface (TPI)
725 \brief Type definitions for the Trace Port Interface (TPI)
730 \brief Structure type to access the Trace Port Interface Register (TPI).
734 __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
735 __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
736 uint32_t RESERVED0[2U];
737 __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
738 uint32_t RESERVED1[55U];
739 __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
740 uint32_t RESERVED2[131U];
741 __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
742 __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
743 __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */
744 uint32_t RESERVED3[759U];
745 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
746 __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */
747 __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */
748 uint32_t RESERVED4[1U];
749 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */
750 __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */
751 __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
752 uint32_t RESERVED5[39U];
753 __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
754 __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
755 uint32_t RESERVED7[8U];
756 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */
757 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */
760 /* TPI Asynchronous Clock Prescaler Register Definitions */
761 #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
762 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
764 /* TPI Selected Pin Protocol Register Definitions */
765 #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
766 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
768 /* TPI Formatter and Flush Status Register Definitions */
769 #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
770 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
772 #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
773 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
775 #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
776 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
778 #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
779 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
781 /* TPI Formatter and Flush Control Register Definitions */
782 #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
783 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
785 #define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */
786 #define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */
788 #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
789 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
791 /* TPI TRIGGER Register Definitions */
792 #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
793 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
795 /* TPI Integration Test FIFO Test Data 0 Register Definitions */
796 #define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */
797 #define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */
799 #define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */
800 #define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */
802 #define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */
803 #define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */
805 #define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */
806 #define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */
808 #define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */
809 #define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */
811 #define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */
812 #define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */
814 #define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */
815 #define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */
817 /* TPI Integration Test ATB Control Register 2 Register Definitions */
818 #define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */
819 #define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */
821 #define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */
822 #define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */
824 #define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */
825 #define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */
827 #define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */
828 #define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */
830 /* TPI Integration Test FIFO Test Data 1 Register Definitions */
831 #define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */
832 #define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */
834 #define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */
835 #define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */
837 #define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */
838 #define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */
840 #define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */
841 #define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */
843 #define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */
844 #define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */
846 #define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */
847 #define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */
849 #define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */
850 #define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */
852 /* TPI Integration Test ATB Control Register 0 Definitions */
853 #define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */
854 #define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */
856 #define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */
857 #define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */
859 #define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */
860 #define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */
862 #define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */
863 #define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */
865 /* TPI Integration Mode Control Register Definitions */
866 #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
867 #define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
869 /* TPI DEVID Register Definitions */
870 #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
871 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
873 #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
874 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
876 #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
877 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
879 #define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */
880 #define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */
882 #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
883 #define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
885 /* TPI DEVTYPE Register Definitions */
886 #define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
887 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
889 #define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
890 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
892 /*@}*/ /* end of group CMSIS_TPI */
895 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
897 \ingroup CMSIS_core_register
898 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
899 \brief Type definitions for the Memory Protection Unit (MPU)
904 \brief Structure type to access the Memory Protection Unit (MPU).
908 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
909 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
910 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
911 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
912 __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
913 uint32_t RESERVED0[7U];
915 __IOM uint32_t MAIR[2];
917 __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
918 __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
923 #define MPU_TYPE_RALIASES 1U
925 /* MPU Type Register Definitions */
926 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
927 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
929 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
930 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
932 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
933 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
935 /* MPU Control Register Definitions */
936 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
937 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
939 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
940 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
942 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
943 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
945 /* MPU Region Number Register Definitions */
946 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
947 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
949 /* MPU Region Base Address Register Definitions */
950 #define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
951 #define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
953 #define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
954 #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
956 #define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
957 #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
959 #define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
960 #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
962 /* MPU Region Limit Address Register Definitions */
963 #define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
964 #define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
966 #define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
967 #define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
969 #define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */
970 #define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */
972 /* MPU Memory Attribute Indirection Register 0 Definitions */
973 #define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
974 #define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
976 #define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
977 #define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
979 #define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
980 #define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
982 #define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
983 #define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
985 /* MPU Memory Attribute Indirection Register 1 Definitions */
986 #define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
987 #define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
989 #define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
990 #define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
992 #define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
993 #define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
995 #define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
996 #define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
998 /*@} end of group CMSIS_MPU */
1002 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1004 \ingroup CMSIS_core_register
1005 \defgroup CMSIS_SAU Security Attribution Unit (SAU)
1006 \brief Type definitions for the Security Attribution Unit (SAU)
1011 \brief Structure type to access the Security Attribution Unit (SAU).
1015 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
1016 __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
1017 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
1018 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
1019 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
1020 __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
1024 /* SAU Control Register Definitions */
1025 #define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
1026 #define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
1028 #define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
1029 #define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
1031 /* SAU Type Register Definitions */
1032 #define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
1033 #define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
1035 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
1036 /* SAU Region Number Register Definitions */
1037 #define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
1038 #define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
1040 /* SAU Region Base Address Register Definitions */
1041 #define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
1042 #define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
1044 /* SAU Region Limit Address Register Definitions */
1045 #define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
1046 #define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
1048 #define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
1049 #define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
1051 #define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
1052 #define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
1054 #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
1056 /*@} end of group CMSIS_SAU */
1057 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
1060 /* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */
1062 \ingroup CMSIS_core_register
1063 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
1064 \brief Type definitions for the Core Debug Registers
1069 \brief \deprecated Structure type to access the Core Debug Register (CoreDebug).
1073 __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
1074 __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
1075 __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
1076 __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
1077 uint32_t RESERVED0[1U];
1078 __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
1079 __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
1082 /* Debug Halting Control and Status Register Definitions */
1083 #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */
1084 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */
1086 #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */
1087 #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */
1089 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */
1090 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */
1092 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */
1093 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */
1095 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */
1096 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */
1098 #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */
1099 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */
1101 #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */
1102 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */
1104 #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */
1105 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */
1107 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */
1108 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */
1110 #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */
1111 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */
1113 #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */
1114 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */
1116 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */
1117 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */
1119 /* Debug Core Register Selector Register Definitions */
1120 #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */
1121 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */
1123 #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */
1124 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */
1126 /* Debug Exception and Monitor Control Register */
1127 #define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: DWTENA Position */
1128 #define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< \deprecated CoreDebug DEMCR: DWTENA Mask */
1130 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */
1131 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */
1133 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */
1134 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */
1136 /* Debug Authentication Control Register Definitions */
1137 #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
1138 #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
1140 #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */
1141 #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
1143 #define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */
1144 #define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */
1146 #define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */
1147 #define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */
1149 /* Debug Security Control and Status Register Definitions */
1150 #define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */
1151 #define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */
1153 #define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */
1154 #define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */
1156 #define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */
1157 #define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */
1159 /*@} end of group CMSIS_CoreDebug */
1163 \ingroup CMSIS_core_register
1164 \defgroup CMSIS_DCB Debug Control Block
1165 \brief Type definitions for the Debug Control Block Registers
1170 \brief Structure type to access the Debug Control Block Registers (DCB).
1174 __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
1175 __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
1176 __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
1177 __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
1178 uint32_t RESERVED0[1U];
1179 __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
1180 __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
1183 /* DHCSR, Debug Halting Control and Status Register Definitions */
1184 #define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */
1185 #define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */
1187 #define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */
1188 #define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */
1190 #define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */
1191 #define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */
1193 #define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */
1194 #define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */
1196 #define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */
1197 #define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */
1199 #define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */
1200 #define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */
1202 #define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */
1203 #define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */
1205 #define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */
1206 #define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */
1208 #define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */
1209 #define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */
1211 #define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */
1212 #define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */
1214 #define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */
1215 #define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */
1217 #define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */
1218 #define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */
1220 #define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */
1221 #define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */
1223 /* DCRSR, Debug Core Register Select Register Definitions */
1224 #define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */
1225 #define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */
1227 #define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */
1228 #define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */
1230 /* DCRDR, Debug Core Register Data Register Definitions */
1231 #define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */
1232 #define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */
1234 /* DEMCR, Debug Exception and Monitor Control Register Definitions */
1235 #define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */
1236 #define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */
1238 #define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */
1239 #define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */
1241 #define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */
1242 #define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */
1244 /* DAUTHCTRL, Debug Authentication Control Register Definitions */
1245 #define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */
1246 #define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */
1248 #define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */
1249 #define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */
1251 #define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */
1252 #define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */
1254 #define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */
1255 #define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */
1257 /* DSCSR, Debug Security Control and Status Register Definitions */
1258 #define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */
1259 #define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */
1261 #define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */
1262 #define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */
1264 #define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */
1265 #define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */
1267 #define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */
1268 #define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */
1270 /*@} end of group CMSIS_DCB */
1275 \ingroup CMSIS_core_register
1276 \defgroup CMSIS_DIB Debug Identification Block
1277 \brief Type definitions for the Debug Identification Block Registers
1282 \brief Structure type to access the Debug Identification Block Registers (DIB).
1286 __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */
1287 __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */
1288 __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */
1289 __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */
1290 __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */
1293 /* DLAR, SCS Software Lock Access Register Definitions */
1294 #define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */
1295 #define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */
1297 /* DLSR, SCS Software Lock Status Register Definitions */
1298 #define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */
1299 #define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */
1301 #define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */
1302 #define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */
1304 #define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */
1305 #define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */
1307 /* DAUTHSTATUS, Debug Authentication Status Register Definitions */
1308 #define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */
1309 #define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */
1311 #define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */
1312 #define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */
1314 #define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */
1315 #define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */
1317 #define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */
1318 #define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */
1320 /* DDEVARCH, SCS Device Architecture Register Definitions */
1321 #define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */
1322 #define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */
1324 #define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */
1325 #define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */
1327 #define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */
1328 #define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */
1330 #define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */
1331 #define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */
1333 #define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */
1334 #define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */
1336 /* DDEVTYPE, SCS Device Type Register Definitions */
1337 #define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */
1338 #define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */
1340 #define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */
1341 #define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */
1344 /*@} end of group CMSIS_DIB */
1348 \ingroup CMSIS_core_register
1349 \defgroup CMSIS_core_bitfield Core register bit field macros
1350 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
1355 \brief Mask and shift a bit field value for use in a register bit range.
1356 \param[in] field Name of the register bit field.
1357 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
1358 \return Masked and shifted value.
1360 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
1363 \brief Mask and shift a register value to extract a bit filed value.
1364 \param[in] field Name of the register bit field.
1365 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
1366 \return Masked and shifted bit field value.
1368 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
1370 /*@} end of group CMSIS_core_bitfield */
1374 \ingroup CMSIS_core_register
1375 \defgroup CMSIS_core_base Core Definitions
1376 \brief Definitions for base addresses, unions, and structures.
1380 /* Memory mapping of Core Hardware */
1381 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
1382 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
1383 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
1384 #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */
1385 #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */
1386 #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */
1387 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
1388 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
1389 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
1392 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
1393 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
1394 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
1395 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
1396 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
1397 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */
1398 #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */
1399 #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */
1401 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1402 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
1403 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
1406 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1407 #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
1408 #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
1411 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1412 #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
1413 #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */
1414 #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */
1415 #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */
1416 #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
1417 #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
1418 #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
1420 #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
1421 #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
1422 #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
1423 #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */
1424 #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */
1425 #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */
1427 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1428 #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
1429 #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
1432 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
1437 /*******************************************************************************
1438 * Hardware Abstraction Layer
1439 Core Function Interface contains:
1440 - Core NVIC Functions
1441 - Core SysTick Functions
1442 - Core Debug Functions
1443 - Core Register Access Functions
1444 ******************************************************************************/
1446 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
1451 /* ########################## NVIC functions #################################### */
1453 \ingroup CMSIS_Core_FunctionInterface
1454 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
1455 \brief Functions that manage interrupts and exceptions via the NVIC.
1459 #ifdef CMSIS_NVIC_VIRTUAL
1460 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
1461 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
1463 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
1465 /*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */
1466 /*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */
1467 #define NVIC_EnableIRQ __NVIC_EnableIRQ
1468 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
1469 #define NVIC_DisableIRQ __NVIC_DisableIRQ
1470 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
1471 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
1472 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
1473 #define NVIC_GetActive __NVIC_GetActive
1474 #define NVIC_SetPriority __NVIC_SetPriority
1475 #define NVIC_GetPriority __NVIC_GetPriority
1476 #define NVIC_SystemReset __NVIC_SystemReset
1477 #endif /* CMSIS_NVIC_VIRTUAL */
1479 #ifdef CMSIS_VECTAB_VIRTUAL
1480 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
1481 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
1483 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
1485 #define NVIC_SetVector __NVIC_SetVector
1486 #define NVIC_GetVector __NVIC_GetVector
1487 #endif /* (CMSIS_VECTAB_VIRTUAL) */
1489 #define NVIC_USER_IRQ_OFFSET 16
1492 /* Special LR values for Secure/Non-Secure call handling and exception handling */
1494 /* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
1495 #define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
1497 /* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
1498 #define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
1499 #define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
1500 #define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
1501 #define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
1502 #define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
1503 #define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */
1504 #define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
1506 /* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
1507 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
1508 #define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
1510 #define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
1514 /* Interrupt Priorities are WORD accessible only under Armv6-M */
1515 /* The following MACROS handle generation of the register offset and byte masks */
1516 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
1517 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
1518 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
1520 #define __NVIC_SetPriorityGrouping(X) (void)(X)
1521 #define __NVIC_GetPriorityGrouping() (0U)
1524 \brief Enable Interrupt
1525 \details Enables a device specific interrupt in the NVIC interrupt controller.
1526 \param [in] IRQn Device specific interrupt number.
1527 \note IRQn must not be negative.
1529 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
1531 if ((int32_t)(IRQn) >= 0)
1533 __COMPILER_BARRIER();
1534 NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1535 __COMPILER_BARRIER();
1541 \brief Get Interrupt Enable status
1542 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
1543 \param [in] IRQn Device specific interrupt number.
1544 \return 0 Interrupt is not enabled.
1545 \return 1 Interrupt is enabled.
1546 \note IRQn must not be negative.
1548 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
1550 if ((int32_t)(IRQn) >= 0)
1552 return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1562 \brief Disable Interrupt
1563 \details Disables a device specific interrupt in the NVIC interrupt controller.
1564 \param [in] IRQn Device specific interrupt number.
1565 \note IRQn must not be negative.
1567 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
1569 if ((int32_t)(IRQn) >= 0)
1571 NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1579 \brief Get Pending Interrupt
1580 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
1581 \param [in] IRQn Device specific interrupt number.
1582 \return 0 Interrupt status is not pending.
1583 \return 1 Interrupt status is pending.
1584 \note IRQn must not be negative.
1586 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
1588 if ((int32_t)(IRQn) >= 0)
1590 return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1600 \brief Set Pending Interrupt
1601 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
1602 \param [in] IRQn Device specific interrupt number.
1603 \note IRQn must not be negative.
1605 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
1607 if ((int32_t)(IRQn) >= 0)
1609 NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1615 \brief Clear Pending Interrupt
1616 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
1617 \param [in] IRQn Device specific interrupt number.
1618 \note IRQn must not be negative.
1620 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
1622 if ((int32_t)(IRQn) >= 0)
1624 NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1630 \brief Get Active Interrupt
1631 \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
1632 \param [in] IRQn Device specific interrupt number.
1633 \return 0 Interrupt status is not active.
1634 \return 1 Interrupt status is active.
1635 \note IRQn must not be negative.
1637 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
1639 if ((int32_t)(IRQn) >= 0)
1641 return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1650 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1652 \brief Get Interrupt Target State
1653 \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
1654 \param [in] IRQn Device specific interrupt number.
1655 \return 0 if interrupt is assigned to Secure
1656 \return 1 if interrupt is assigned to Non Secure
1657 \note IRQn must not be negative.
1659 __STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
1661 if ((int32_t)(IRQn) >= 0)
1663 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1673 \brief Set Interrupt Target State
1674 \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
1675 \param [in] IRQn Device specific interrupt number.
1676 \return 0 if interrupt is assigned to Secure
1677 1 if interrupt is assigned to Non Secure
1678 \note IRQn must not be negative.
1680 __STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
1682 if ((int32_t)(IRQn) >= 0)
1684 NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
1685 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1695 \brief Clear Interrupt Target State
1696 \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
1697 \param [in] IRQn Device specific interrupt number.
1698 \return 0 if interrupt is assigned to Secure
1699 1 if interrupt is assigned to Non Secure
1700 \note IRQn must not be negative.
1702 __STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
1704 if ((int32_t)(IRQn) >= 0)
1706 NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
1707 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1714 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
1718 \brief Set Interrupt Priority
1719 \details Sets the priority of a device specific interrupt or a processor exception.
1720 The interrupt number can be positive to specify a device specific interrupt,
1721 or negative to specify a processor exception.
1722 \param [in] IRQn Interrupt number.
1723 \param [in] priority Priority to set.
1724 \note The priority cannot be set for every processor exception.
1726 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
1728 if ((int32_t)(IRQn) >= 0)
1730 NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
1731 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
1735 SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
1736 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
1742 \brief Get Interrupt Priority
1743 \details Reads the priority of a device specific interrupt or a processor exception.
1744 The interrupt number can be positive to specify a device specific interrupt,
1745 or negative to specify a processor exception.
1746 \param [in] IRQn Interrupt number.
1747 \return Interrupt Priority.
1748 Value is aligned automatically to the implemented priority bits of the microcontroller.
1750 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
1753 if ((int32_t)(IRQn) >= 0)
1755 return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
1759 return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
1765 \brief Encode Priority
1766 \details Encodes the priority for an interrupt with the given priority group,
1767 preemptive priority value, and subpriority value.
1768 In case of a conflict between priority grouping and available
1769 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
1770 \param [in] PriorityGroup Used priority group.
1771 \param [in] PreemptPriority Preemptive priority value (starting from 0).
1772 \param [in] SubPriority Subpriority value (starting from 0).
1773 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
1775 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
1777 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
1778 uint32_t PreemptPriorityBits;
1779 uint32_t SubPriorityBits;
1781 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
1782 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
1785 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
1786 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
1792 \brief Decode Priority
1793 \details Decodes an interrupt priority value with a given priority group to
1794 preemptive priority value and subpriority value.
1795 In case of a conflict between priority grouping and available
1796 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
1797 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
1798 \param [in] PriorityGroup Used priority group.
1799 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
1800 \param [out] pSubPriority Subpriority value (starting from 0).
1802 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
1804 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
1805 uint32_t PreemptPriorityBits;
1806 uint32_t SubPriorityBits;
1808 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
1809 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
1811 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
1812 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
1817 \brief Set Interrupt Vector
1818 \details Sets an interrupt vector in SRAM based interrupt vector table.
1819 The interrupt number can be positive to specify a device specific interrupt,
1820 or negative to specify a processor exception.
1821 VTOR must been relocated to SRAM before.
1822 If VTOR is not present address 0 must be mapped to SRAM.
1823 \param [in] IRQn Interrupt number
1824 \param [in] vector Address of interrupt handler function
1826 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
1828 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
1829 uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR);
1831 uint32_t *vectors = (uint32_t *)0x0U;
1833 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
1839 \brief Get Interrupt Vector
1840 \details Reads an interrupt vector from interrupt vector table.
1841 The interrupt number can be positive to specify a device specific interrupt,
1842 or negative to specify a processor exception.
1843 \param [in] IRQn Interrupt number.
1844 \return Address of interrupt handler function
1846 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
1848 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
1849 uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR);
1851 uint32_t *vectors = (uint32_t *)0x0U;
1853 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
1859 \details Initiates a system reset request to reset the MCU.
1861 __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
1863 __DSB(); /* Ensure all outstanding memory accesses included
1864 buffered write are completed before reset */
1865 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
1866 SCB_AIRCR_SYSRESETREQ_Msk);
1867 __DSB(); /* Ensure completion of memory access */
1869 for(;;) /* wait until reset */
1875 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1877 \brief Enable Interrupt (non-secure)
1878 \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
1879 \param [in] IRQn Device specific interrupt number.
1880 \note IRQn must not be negative.
1882 __STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
1884 if ((int32_t)(IRQn) >= 0)
1886 NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1892 \brief Get Interrupt Enable status (non-secure)
1893 \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
1894 \param [in] IRQn Device specific interrupt number.
1895 \return 0 Interrupt is not enabled.
1896 \return 1 Interrupt is enabled.
1897 \note IRQn must not be negative.
1899 __STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
1901 if ((int32_t)(IRQn) >= 0)
1903 return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1913 \brief Disable Interrupt (non-secure)
1914 \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
1915 \param [in] IRQn Device specific interrupt number.
1916 \note IRQn must not be negative.
1918 __STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
1920 if ((int32_t)(IRQn) >= 0)
1922 NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1928 \brief Get Pending Interrupt (non-secure)
1929 \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
1930 \param [in] IRQn Device specific interrupt number.
1931 \return 0 Interrupt status is not pending.
1932 \return 1 Interrupt status is pending.
1933 \note IRQn must not be negative.
1935 __STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
1937 if ((int32_t)(IRQn) >= 0)
1939 return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1949 \brief Set Pending Interrupt (non-secure)
1950 \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
1951 \param [in] IRQn Device specific interrupt number.
1952 \note IRQn must not be negative.
1954 __STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
1956 if ((int32_t)(IRQn) >= 0)
1958 NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1964 \brief Clear Pending Interrupt (non-secure)
1965 \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
1966 \param [in] IRQn Device specific interrupt number.
1967 \note IRQn must not be negative.
1969 __STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
1971 if ((int32_t)(IRQn) >= 0)
1973 NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1979 \brief Get Active Interrupt (non-secure)
1980 \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
1981 \param [in] IRQn Device specific interrupt number.
1982 \return 0 Interrupt status is not active.
1983 \return 1 Interrupt status is active.
1984 \note IRQn must not be negative.
1986 __STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
1988 if ((int32_t)(IRQn) >= 0)
1990 return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2000 \brief Set Interrupt Priority (non-secure)
2001 \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
2002 The interrupt number can be positive to specify a device specific interrupt,
2003 or negative to specify a processor exception.
2004 \param [in] IRQn Interrupt number.
2005 \param [in] priority Priority to set.
2006 \note The priority cannot be set for every non-secure processor exception.
2008 __STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
2010 if ((int32_t)(IRQn) >= 0)
2012 NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
2013 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
2017 SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
2018 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
2024 \brief Get Interrupt Priority (non-secure)
2025 \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
2026 The interrupt number can be positive to specify a device specific interrupt,
2027 or negative to specify a processor exception.
2028 \param [in] IRQn Interrupt number.
2029 \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
2031 __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
2034 if ((int32_t)(IRQn) >= 0)
2036 return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
2040 return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
2043 #endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
2045 /*@} end of CMSIS_Core_NVICFunctions */
2047 /* ########################## MPU functions #################################### */
2049 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
2051 #include "m-profile/armv8m_mpu.h"
2055 /* ########################## FPU functions #################################### */
2057 \ingroup CMSIS_Core_FunctionInterface
2058 \defgroup CMSIS_Core_FpuFunctions FPU Functions
2059 \brief Function that provides FPU type.
2065 \details returns the FPU type
2068 - \b 1: Single precision FPU
2069 - \b 2: Double + Single precision FPU
2071 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
2073 return 0U; /* No FPU */
2077 /*@} end of CMSIS_Core_FpuFunctions */
2081 /* ########################## SAU functions #################################### */
2083 \ingroup CMSIS_Core_FunctionInterface
2084 \defgroup CMSIS_Core_SAUFunctions SAU Functions
2085 \brief Functions that configure the SAU.
2089 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2093 \details Enables the Security Attribution Unit (SAU).
2095 __STATIC_INLINE void TZ_SAU_Enable(void)
2097 SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
2104 \details Disables the Security Attribution Unit (SAU).
2106 __STATIC_INLINE void TZ_SAU_Disable(void)
2108 SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
2111 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
2113 /*@} end of CMSIS_Core_SAUFunctions */
2118 /* ################################## Debug Control function ############################################ */
2120 \ingroup CMSIS_Core_FunctionInterface
2121 \defgroup CMSIS_Core_DCBFunctions Debug Control Functions
2122 \brief Functions that access the Debug Control Block.
2128 \brief Set Debug Authentication Control Register
2129 \details writes to Debug Authentication Control register.
2130 \param [in] value value to be writen.
2132 __STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value)
2136 DCB->DAUTHCTRL = value;
2143 \brief Get Debug Authentication Control Register
2144 \details Reads Debug Authentication Control register.
2145 \return Debug Authentication Control Register.
2147 __STATIC_INLINE uint32_t DCB_GetAuthCtrl(void)
2149 return (DCB->DAUTHCTRL);
2153 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2155 \brief Set Debug Authentication Control Register (non-secure)
2156 \details writes to non-secure Debug Authentication Control register when in secure state.
2157 \param [in] value value to be writen
2159 __STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value)
2163 DCB_NS->DAUTHCTRL = value;
2170 \brief Get Debug Authentication Control Register (non-secure)
2171 \details Reads non-secure Debug Authentication Control register when in secure state.
2172 \return Debug Authentication Control Register.
2174 __STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void)
2176 return (DCB_NS->DAUTHCTRL);
2178 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
2180 /*@} end of CMSIS_Core_DCBFunctions */
2185 /* ################################## Debug Identification function ############################################ */
2187 \ingroup CMSIS_Core_FunctionInterface
2188 \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions
2189 \brief Functions that access the Debug Identification Block.
2195 \brief Get Debug Authentication Status Register
2196 \details Reads Debug Authentication Status register.
2197 \return Debug Authentication Status Register.
2199 __STATIC_INLINE uint32_t DIB_GetAuthStatus(void)
2201 return (DIB->DAUTHSTATUS);
2205 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2207 \brief Get Debug Authentication Status Register (non-secure)
2208 \details Reads non-secure Debug Authentication Status register when in secure state.
2209 \return Debug Authentication Status Register.
2211 __STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void)
2213 return (DIB_NS->DAUTHSTATUS);
2215 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
2217 /*@} end of CMSIS_Core_DCBFunctions */
2222 /* ################################## SysTick function ############################################ */
2224 \ingroup CMSIS_Core_FunctionInterface
2225 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
2226 \brief Functions that configure the System.
2230 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
2233 \brief System Tick Configuration
2234 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
2235 Counter is in free running mode to generate periodic interrupts.
2236 \param [in] ticks Number of ticks between two interrupts.
2237 \return 0 Function succeeded.
2238 \return 1 Function failed.
2239 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
2240 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
2241 must contain a vendor-specific implementation of this function.
2243 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
2245 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
2247 return (1UL); /* Reload value impossible */
2250 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
2251 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
2252 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
2253 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
2254 SysTick_CTRL_TICKINT_Msk |
2255 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
2256 return (0UL); /* Function successful */
2259 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2261 \brief System Tick Configuration (non-secure)
2262 \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
2263 Counter is in free running mode to generate periodic interrupts.
2264 \param [in] ticks Number of ticks between two interrupts.
2265 \return 0 Function succeeded.
2266 \return 1 Function failed.
2267 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
2268 function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
2269 must contain a vendor-specific implementation of this function.
2272 __STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
2274 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
2276 return (1UL); /* Reload value impossible */
2279 SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
2280 TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
2281 SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
2282 SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
2283 SysTick_CTRL_TICKINT_Msk |
2284 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
2285 return (0UL); /* Function successful */
2287 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
2291 /*@} end of CMSIS_Core_SysTickFunctions */
2300 #endif /* __CORE_CM23_H_DEPENDANT */
2302 #endif /* __CMSIS_GENERIC */
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