begriffs open source - cmsis/blob - CMSIS/DoxyGen/Core_A/src/ref_cache.txt

   1 /* ##########################  L1 Cache functions  ################################# */
   2
   3 /**
   4 \defgroup L1_cache_functions L1 Cache Functions
   5 \ingroup CMSIS_Core_FunctionInterface
   6 \brief L1 Cache Functions give support to enable, clean and invalidate level 1 instruction and data caches, as well as to enable branch target address cache.
   7 @{
   8 \fn __STATIC_INLINE void L1C_EnableCaches(void)
   9 \fn __STATIC_INLINE void L1C_DisableCaches(void)
  10 \fn __STATIC_INLINE void L1C_EnableBTAC(void)
  11 \fn __STATIC_INLINE void L1C_DisableBTAC(void)
  12 \fn __STATIC_INLINE void L1C_InvalidateBTAC(void)
  13 \fn __STATIC_INLINE void L1C_InvalidateICacheAll(void)
  14 \fn __STATIC_INLINE void L1C_CleanDCacheMVA(void *va)
  15 \fn __STATIC_INLINE void L1C_InvalidateDCacheMVA(void *va)
  16 \fn __STATIC_INLINE void L1C_CleanInvalidateDCacheMVA(void *va)
  17
  18 \fn __STATIC_INLINE void L1C_CleanInvalidateCache(uint32_t op)
  19 \details
  20 Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
  21
  22 \fn __STATIC_INLINE void L1C_InvalidateDCacheAll(void)
  23 \fn __STATIC_INLINE void L1C_CleanDCacheAll(void)
  24 \fn __STATIC_INLINE void L1C_CleanInvalidateDCacheAll(void)
  25 \fn __STATIC_INLINE __ASM void __L1C_CleanInvalidateCache(uint32_t op)
  26 \details
  27 Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
  28
  29 The parameter \b op defines which cleaning/invalidation strategy should be used:
  30  - 0 - Cache is invalidated using DCISW register.
  31  - 1 - Cache is cleaned using DCCSW register.
  32  - other - Cache is invalidated and cleaned using DCCISW register.
  33 @}
  34 */
  35
  36 /* ##########################  L2 Cache functions  ################################# */
  37
  38 /**
  39 \defgroup L2_cache_functions L2C-310 Cache Controller Functions
  40 \ingroup CMSIS_Core_FunctionInterface
  41 \brief L2C-310 Cache Controller gives access to functions for level 2 cache maintenance.\n
  42 Reference: <a href="http://infocenter.arm.com/help/topic/com.arm.doc.ddi0246h/index.html">Level 2 Cache Controller L2C-310 Technical Reference Manual</a>.
  43 */
  44 /** @{ */
  45
  46 /**
  47 \struct L2C_310_TypeDef
  48 \def L2C_310
  49 \fn __STATIC_INLINE void L2C_Sync(void)
  50 \fn __STATIC_INLINE int L2C_GetID (void)
  51 \fn __STATIC_INLINE int L2C_GetType (void)
  52 \fn __STATIC_INLINE void L2C_InvAllByWay (void)
  53 \fn __STATIC_INLINE void L2C_CleanInvAllByWay (void)
  54 \fn __STATIC_INLINE void L2C_Enable(void)
  55 \fn __STATIC_INLINE void L2C_Disable(void)
  56 \fn __STATIC_INLINE void L2C_InvPa (void *pa)
  57 \fn __STATIC_INLINE void L2C_CleanPa (void *pa)
  58 \fn __STATIC_INLINE void L2C_CleanInvPa (void *pa)
  59 */
  60
  61 /** @} */
  62
  63 /* ########################## L2C_310_TypeDef Member ########################## */
  64 /**
  65 \var L2C_310_TypeDef::ADDRESS_FILTER_END
  66 \brief
  67
  68 \var __IOM uint32_t L2C_310_TypeDef::ADDRESS_FILTER_START
  69 \brief
  70
  71 \var __IOM uint32_t L2C_310_TypeDef::AUX_CNT
  72 \brief
  73
  74 \var __IM  uint32_t L2C_310_TypeDef::CACHE_ID
  75 \brief
  76
  77 \var __IOM uint32_t L2C_310_TypeDef::CACHE_SYNC
  78 \brief
  79
  80 \var __IM  uint32_t L2C_310_TypeDef::CACHE_TYPE
  81 \brief
  82
  83 \var __IOM uint32_t L2C_310_TypeDef::CLEAN_INV_LINE_INDEX_WAY
  84 \brief
  85
  86 \var __IOM uint32_t L2C_310_TypeDef::CLEAN_INV_LINE_PA
  87 \brief
  88
  89 \var __IOM uint32_t L2C_310_TypeDef::CLEAN_INV_WAY
  90 \brief
  91
  92 \var __IOM uint32_t L2C_310_TypeDef::CLEAN_LINE_INDEX_WAY
  93 \brief
  94
  95 \var __IOM uint32_t L2C_310_TypeDef::CLEAN_LINE_PA
  96 \brief
  97
  98 \var __IOM uint32_t L2C_310_TypeDef::CLEAN_WAY
  99 \brief
 100
 101 \var __IOM uint32_t L2C_310_TypeDef::CONTROL
 102 \brief
 103
 104 \var __IOM uint32_t L2C_310_TypeDef::DATA_LOCK_0_WAY
 105 \brief
 106
 107 \var __IOM uint32_t L2C_310_TypeDef::DATA_LOCK_1_WAY
 108 \brief
 109
 110 \var __IOM uint32_t L2C_310_TypeDef::DATA_LOCK_2_WAY
 111 \brief
 112
 113 \var __IOM uint32_t L2C_310_TypeDef::DATA_LOCK_3_WAY
 114 \brief
 115
 116 \var __IOM uint32_t L2C_310_TypeDef::DATA_LOCK_4_WAY
 117 \brief
 118
 119 \var __IOM uint32_t L2C_310_TypeDef::DATA_LOCK_5_WAY
 120 \brief
 121
 122 \var __IOM uint32_t L2C_310_TypeDef::DATA_LOCK_6_WAY
 123 \brief
 124
 125 \var __IOM uint32_t L2C_310_TypeDef::DATA_LOCK_7_WAY
 126 \brief
 127
 128 \var __IOM uint32_t L2C_310_TypeDef::DEBUG_CONTROL
 129 \brief
 130
 131 \var __IOM uint32_t L2C_310_TypeDef::EVENT_CONTROL
 132 \brief
 133
 134 \var __IOM uint32_t L2C_310_TypeDef::EVENT_COUNTER0_CONF
 135 \brief
 136
 137 \var __IOM uint32_t L2C_310_TypeDef::EVENT_COUNTER1_CONF
 138 \brief
 139
 140 \var __IOM uint32_t L2C_310_TypeDef::INST_LOCK_0_WAY
 141 \brief
 142
 143 \var __IOM uint32_t L2C_310_TypeDef::INST_LOCK_1_WAY
 144 \brief
 145
 146 \var __IOM uint32_t L2C_310_TypeDef::INST_LOCK_2_WAY
 147 \brief
 148
 149 \var __IOM uint32_t L2C_310_TypeDef::INST_LOCK_3_WAY
 150 \brief
 151
 152 \var __IOM uint32_t L2C_310_TypeDef::INST_LOCK_4_WAY
 153 \brief
 154
 155 \var __IOM uint32_t L2C_310_TypeDef::INST_LOCK_5_WAY
 156 \brief
 157
 158 \var __IOM uint32_t L2C_310_TypeDef::INST_LOCK_6_WAY
 159 \brief
 160
 161 \var __IOM uint32_t L2C_310_TypeDef::INST_LOCK_7_WAY
 162 \brief
 163
 164 \var __OM  uint32_t L2C_310_TypeDef::INTERRUPT_CLEAR
 165 \brief
 166
 167 \var __IOM uint32_t L2C_310_TypeDef::INTERRUPT_MASK
 168 \brief
 169
 170 \var __IOM uint32_t L2C_310_TypeDef::INV_LINE_PA
 171 \brief
 172
 173 \var __IOM uint32_t L2C_310_TypeDef::INV_WAY
 174 \brief
 175
 176 \var __IOM uint32_t L2C_310_TypeDef::LOCK_LINE_EN
 177 \brief
 178
 179 \var __IM  uint32_t L2C_310_TypeDef::MASKED_INT_STATUS
 180 \brief
 181
 182 \var __IM  uint32_t L2C_310_TypeDef::RAW_INT_STATUS
 183 \brief
 184
 185 \var __IOM uint32_t L2C_310_TypeDef::UNLOCK_ALL_BY_WAY
 186 \brief
 187 */