begriffs open source - cmsis/blob - CMSIS/CoreValidation/Source/Config/CV_Config.h

   1 /*-----------------------------------------------------------------------------
   2  *      Name:         CV_Config.h
   3  *      Purpose:      CV Config header
   4  *----------------------------------------------------------------------------
   5  *      Copyright (c) 2017 - 2024 Arm Limited. All rights reserved.
   6  *----------------------------------------------------------------------------*/
   7 #ifndef __CV_CONFIG_H
   8 #define __CV_CONFIG_H
   9
  10 #include "RTE_Components.h"
  11 #include CMSIS_device_header
  12
  13 #define RTE_CV_COREINSTR 1
  14 #define RTE_CV_COREFUNC  1
  15 #define RTE_CV_CORESIMD  1
  16 #define RTE_CV_MPUFUNC   (__MPU_PRESENT)
  17 #if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \
  18      (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)))
  19 #define RTE_CV_L1CACHE   (__ICACHE_PRESENT || __DCACHE_PRESENT)
  20 #endif
  21
  22 //-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
  23
  24 // <h> Common Test Settings
  25 // <o> Print Output Format <0=> Plain Text <1=> XML
  26 // <i> Set the test results output format to plain text or XML
  27 #ifndef PRINT_XML_REPORT
  28 #define PRINT_XML_REPORT            1
  29 #endif
  30 // <o> Buffer size for assertions results
  31 // <i> Set the buffer size for assertions results buffer
  32 #define BUFFER_ASSERTIONS           128U
  33 // </h>
  34
  35 // <h> Disable Test Cases
  36 // <i> Uncheck to disable an individual test case
  37 // <q0> TC_CoreInstr_NOP
  38 #define TC_COREINSTR_NOP_EN                        1
  39 // <q0> TC_CoreInstr_SEV
  40 #define TC_COREINSTR_SEV_EN                        1
  41 // <q0> TC_CoreInstr_BKPT
  42 #define TC_COREINSTR_BKPT_EN                       1
  43 // <q0> TC_CoreInstr_ISB
  44 #define TC_COREINSTR_ISB_EN                        1
  45 // <q0> TC_CoreInstr_DSB
  46 #define TC_COREINSTR_DSB_EN                        1
  47 // <q0> TC_CoreInstr_DMB
  48 #define TC_COREINSTR_DMB_EN                        1
  49 // <q0> TC_CoreInstr_WFI
  50 #define TC_COREINSTR_WFI_EN                        0
  51 // <q0> TC_CoreInstr_WFE
  52 #define TC_COREINSTR_WFE_EN                        0
  53
  54 // <q0> TC_CoreInstr_REV
  55 #define TC_COREINSTR_REV_EN                        1
  56 // <q0> TC_CoreInstr_REV16
  57 #define TC_COREINSTR_REV16_EN                      1
  58 // <q0> TC_CoreInstr_REVSH
  59 #define TC_COREINSTR_REVSH_EN                      1
  60 // <q0> TC_CoreInstr_ROR
  61 #define TC_COREINSTR_ROR_EN                        1
  62 // <q0> TC_CoreInstr_RBIT
  63 #define TC_COREINSTR_RBIT_EN                       1
  64 // <q0> TC_CoreInstr_CLZ
  65 #define TC_COREINSTR_CLZ_EN                        1
  66 // <q0> TC_CoreInstr_SSAT
  67 #define TC_COREINSTR_SSAT_EN                       1
  68 // <q0> TC_CoreInstr_USAT
  69 #define TC_COREINSTR_USAT_EN                       1
  70 // <q0> TC_CoreInstr_RRX
  71 #define TC_COREINSTR_RRX_EN                        1
  72 // <q0> TC_CoreInstr_LoadStoreExlusive
  73 #define TC_COREINSTR_LOADSTOREEXCLUSIVE_EN         1
  74 // <q0> TC_CoreInstr_LoadStoreUnpriv
  75 #define TC_COREINSTR_LOADSTOREUNPRIV_EN            1
  76 // <q0> TC_CoreInstr_LoadStoreAcquire
  77 #define TC_COREINSTR_LOADSTOREACQUIRE_EN           1
  78 // <q0> TC_CoreInstr_LoadStoreAcquireExclusive
  79 #define TC_COREINSTR_LOADSTOREACQUIREEXCLUSIVE_EN  1
  80 // <q0> TC_CoreInstr_UnalignedUint16
  81 #define TC_COREINSTR_UNALIGNEDUINT16_EN            1
  82 // <q0> TC_CoreInstr_UnalignedUint32
  83 #define TC_COREINSTR_UNALIGNEDUINT32_EN            1
  84
  85 // <q0> TC_CoreSimd_SatAddSub
  86 #define TC_CORESIMD_SATADDSUB_EN                   1
  87 // <q0> TC_CoreSimd_ParSat16
  88 #define TC_CORESIMD_PARSAT16_EN                    1
  89 // <q0> TC_CoreSimd_PackUnpack
  90 #define TC_CORESIMD_PACKUNPACK_EN                  1
  91 // <q0> TC_CoreSimd_ParSel
  92 #define TC_CORESIMD_PARSEL_EN                      1
  93 // <q0> TC_CoreSimd_ParAddSub8
  94 #define TC_CORESIMD_PARADDSUB8_EN                  1
  95 // <q0> TC_CoreSimd_AbsDif8
  96 #define TC_CORESIMD_ABSDIF8_EN                     1
  97 // <q0> TC_CoreSimd_ParAddSub16
  98 #define TC_CORESIMD_PARADDSUB16_EN                 1
  99 // <q0> TC_CoreSimd_ParMul16
 100 #define TC_CORESIMD_PARMUL16_EN                    1
 101 // <q0> TC_CoreSimd_Pack16
 102 #define TC_CORESIMD_PACK16_EN                      1
 103 // <q0> TC_CoreSimd_MulAcc32
 104 #define TC_CORESIMD_MULACC32_EN                    1
 105
 106 // <q0> TC_CoreFunc_EnDisIRQ
 107 #define TC_COREFUNC_ENDISIRQ_EN                    1
 108 // <q0> TC_CoreFunc_IRQPrio
 109 #define TC_COREFUNC_IRQPRIO_EN                     1
 110 // <q0> TC_CoreFunc_EncDecIRQPrio
 111 #define TC_COREFUNC_ENCDECIRQPRIO_EN               1
 112 // <q0> TC_CoreFunc_IRQVect
 113 #define TC_COREFUNC_IRQVECT_EN                     1
 114 // <q0> TC_CoreFunc_Control
 115 #define TC_COREFUNC_CONTROL_EN                     1
 116 // <q0> TC_CoreFunc_IPSR
 117 #define TC_COREFUNC_IPSR_EN                        1
 118 // <q0> TC_CoreFunc_APSR
 119 #define TC_COREFUNC_APSR_EN                        1
 120 // <q0> TC_CoreFunc_PSP
 121 #define TC_COREFUNC_PSP_EN                         1
 122 // <q0> TC_CoreFunc_MSP
 123 #define TC_COREFUNC_MSP_EN                         1
 124
 125 // <q0> TC_CoreFunc_PSPLIM
 126 #define TC_COREFUNC_PSPLIM_EN                      1
 127 // <q0> TC_CoreFunc_PSPLIM_NS
 128 #define TC_COREFUNC_PSPLIM_NS_EN                   1
 129 // <q0> TC_CoreFunc_MSPLIM
 130 #define TC_COREFUNC_MSPLIM_EN                      1
 131 // <q0> TC_CoreFunc_MSPLIM_NS
 132 #define TC_COREFUNC_MSPLIM_NS_EN                   1
 133 // <q0> TC_CoreFunc_PRIMASK
 134 #define TC_COREFUNC_PRIMASK_EN                     1
 135 // <q0> TC_CoreFunc_FAULTMASK
 136 #define TC_COREFUNC_FAULTMASK_EN                   1
 137 // <q0> TC_CoreFunc_BASEPRI
 138 #define TC_COREFUNC_BASEPRI_EN                     1
 139 // <q0> TC_CoreFunc_FPUType
 140 #define TC_COREFUNC_FPUTYPE_EN                     1
 141 // <q0> TC_CoreFunc_FPSCR
 142 #define TC_COREFUNC_FPSCR_EN                       1
 143
 144 // <q0> TC_MPU_SetClear
 145 #define TC_MPU_SETCLEAR_EN                         1
 146 // <q0> TC_MPU_Load
 147 #define TC_MPU_LOAD_EN                             1
 148
 149 // <q0> TC_CML1Cache_EnDisableICache
 150 #define TC_CML1CACHE_ENDISABLE_ICACHE              1
 151 // <q0> TC_CML1Cache_EnDisableDCache
 152 #define TC_CML1CACHE_ENDISABLE_DCACHE              1
 153 // <q0> TC_CML1Cache_CleanDCacheByAddrWhileDisabled
 154 #define TC_CML1CACHE_CLEANDCACHEBYADDRWHILEDISABLED 1
 155
 156 // </h>
 157
 158 #endif /* __CV_CONFIG_H */
 159