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 130   <div class="headertitle"><div class="title">Memory Management Unit Files mmu_&lt;device&gt;.c </div></div>
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 132 <div class="contents">
 133 <div class="textblock"><pre class="fragment">/**************************************************************************//**
 134  * @file     system_Device.c
 135  * @brief    MMU Configuration
 136  *           Device &lt;DeviceAbbreviation&gt;
 137  * @version  V1.1.0
 138  * @date     23. November 2018
 139  ******************************************************************************/
 140 /*
 141  * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
 142  *
 143  * SPDX-License-Identifier: Apache-2.0
 144  *
 145  * Licensed under the Apache License, Version 2.0 (the License); you may
 146  * not use this file except in compliance with the License.
 147  * You may obtain a copy of the License at
 148  *
 149  * www.apache.org/licenses/LICENSE-2.0
 150  *
 151  * Unless required by applicable law or agreed to in writing, software
 152  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
 153  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 154  * See the License for the specific language governing permissions and
 155  * limitations under the License.
 156  */
 157
 158 /* Memory map description
 159
 160    ToDo: add in this file your device memory map description
 161          following is an example of a Cortex-A9 Arm FVP device
 162
 163                                                      Memory Type
 164 0xFFFFFFFF |--------------------------|             ------------
 165            |       FLAG SYNC          |             Device Memory
 166 0xFFFFF000 |--------------------------|             ------------
 167            |         Fault            |                Fault
 168 0xFFF00000 |--------------------------|             ------------
 169            |                          |                Normal
 170            |                          |
 171            |      Daughterboard       |
 172            |         memory           |
 173            |                          |
 174 0x80505000 |--------------------------|             ------------
 175            |TTB (L2 Sync Flags   ) 4k |                Normal
 176 0x80504C00 |--------------------------|             ------------
 177            |TTB (L2 Peripherals-B) 16k|                Normal
 178 0x80504800 |--------------------------|             ------------
 179            |TTB (L2 Peripherals-A) 16k|                Normal
 180 0x80504400 |--------------------------|             ------------
 181            |TTB (L2 Priv Periphs)  4k |                Normal
 182 0x80504000 |--------------------------|             ------------
 183            |    TTB (L1 Descriptors)  |                Normal
 184 0x80500000 |--------------------------|             ------------
 185            |           Heap           |                Normal
 186            |--------------------------|             ------------
 187            |          Stack           |                Normal
 188 0x80400000 |--------------------------|             ------------
 189            |         ZI Data          |                Normal
 190 0x80300000 |--------------------------|             ------------
 191            |         RW Data          |                Normal
 192 0x80200000 |--------------------------|             ------------
 193            |         RO Data          |                Normal
 194            |--------------------------|             ------------
 195            |         RO Code          |              USH Normal
 196 0x80000000 |--------------------------|             ------------
 197            |      Daughterboard       |                Fault
 198            |      HSB AXI buses       |
 199 0x40000000 |--------------------------|             ------------
 200            |      Daughterboard       |                Fault
 201            |  test chips peripherals  |
 202 0x2C002000 |--------------------------|             ------------
 203            |     Private Address      |            Device Memory
 204 0x2C000000 |--------------------------|             ------------
 205            |      Daughterboard       |                Fault
 206            |  test chips peripherals  |
 207 0x20000000 |--------------------------|             ------------
 208            |       Peripherals        |           Device Memory RW/RO
 209            |                          |              &amp; Fault
 210 0x00000000 |--------------------------|
 211 */
 212
 213 // L1 Cache info and restrictions about architecture of the caches (CCSIR register):
 214 // Write-Through support *not* available
 215 // Write-Back support available.
 216 // Read allocation support available.
 217 // Write allocation support available.
 218
 219 // Note: You should use the Shareable attribute carefully.
 220 // For cores without coherency logic (such as SCU) marking a region as shareable forces the processor to not cache that region regardless of the inner cache settings.
 221 // Cortex-A versions of RTX use LDREX/STREX instructions relying on Local monitors. Local monitors will be used only when the region gets cached, regions that are not cached will use the Global Monitor.
 222 // Some Cortex-A implementations do not include Global Monitors, so wrongly setting the attribute Shareable may cause STREX to fail.
 223
 224 // Recall: When the Shareable attribute is applied to a memory region that is not Write-Back, Normal memory, data held in this region is treated as Non-cacheable.
 225 // When SMP bit = 0, Inner WB/WA Cacheable Shareable attributes are treated as Non-cacheable.
 226 // When SMP bit = 1, Inner WB/WA Cacheable Shareable attributes are treated as Cacheable.
 227
 228 // Following MMU configuration is expected
 229 // SCTLR.AFE == 1 (Simplified access permissions model - AP[2:1] define access permissions, AP[0] is an access flag)
 230 // SCTLR.TRE == 0 (TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor)
 231 // Domain 0 is always the Client domain
 232 // Descriptors should place all memory in domain 0
 233
 234 #include "&lt;Device&gt;.h" /* ToDo: replace '&lt;Device&gt;' with your device name */
 235
 236 // L2 table pointers
 237 //-----------------------------------------------------
 238 #define PRIVATE_TABLE_L2_BASE_4k       (0x80504000) //Map 4k Private Address space
 239 #define SYNC_FLAGS_TABLE_L2_BASE_4k    (0x80504C00) //Map 4k Flag synchronization
 240 #define PERIPHERAL_A_TABLE_L2_BASE_64k (0x80504400) //Map 64k Peripheral #1
 241 #define PERIPHERAL_B_TABLE_L2_BASE_64k (0x80504800) //Map 64k Peripheral #2
 242
 243 //--------------------- PERIPHERALS -------------------
 244 #define PERIPHERAL_A_FAULT             (0x00000000 + 0x1C000000)
 245 #define PERIPHERAL_B_FAULT             (0x00100000 + 0x1C000000)
 246
 247 //--------------------- SYNC FLAGS --------------------
 248 #define FLAG_SYNC                       0xFFFFF000
 249 #define F_SYNC_BASE                     0xFFF00000  //1M aligned
 250
 251 //Import symbols from linker
 252 extern uint32_t Image$$VECTORS$$Base;
 253 extern uint32_t Image$$RW_DATA$$Base;
 254 extern uint32_t Image$$ZI_DATA$$Base;
 255 extern uint32_t Image$$TTB$$ZI$$Base;
 256
 257 static uint32_t Sect_Normal;        // outer &amp; inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0
 258 static uint32_t Sect_Normal_Cod;    // outer &amp; inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0
 259 static uint32_t Sect_Normal_RO;     // as Sect_Normal_Cod, but not executable
 260 static uint32_t Sect_Normal_RW;     // as Sect_Normal_Cod, but writeable and not executable
 261 static uint32_t Sect_Device_RO;     // device, non-shareable, non-executable, ro, domain 0, base addr 0
 262 static uint32_t Sect_Device_RW;     // as Sect_Device_RO, but writeable
 263
 264 /* Define global descriptors */
 265 static uint32_t Page_L1_4k  = 0x0;  // generic
 266 static uint32_t Page_L1_64k = 0x0;  // generic
 267 static uint32_t Page_4k_Device_RW;  // shared device, not executable, rw, domain 0
 268 static uint32_t Page_64k_Device_RW; // shared device, not executable, rw, domain 0
 269
 270 void MMU_CreateTranslationTable(void)
 271 {
 272   mmu_region_attributes_Type region;
 273
 274   // Create 4GB of faulting entries
 275   MMU_TTSection (&amp;Image$$TTB$$ZI$$Base, 0, 4096, DESCRIPTOR_FAULT);
 276
 277   /*
 278    * Generate descriptors. Refer to core_ca.h to get information about attributes
 279    *
 280    */
 281   // Create descriptors for Vectors, RO, RW, ZI sections
 282   section_normal(Sect_Normal, region);
 283   section_normal_cod(Sect_Normal_Cod, region);
 284   section_normal_ro(Sect_Normal_RO, region);
 285   section_normal_rw(Sect_Normal_RW, region);
 286   // Create descriptors for peripherals
 287   section_Device_ro(Sect_Device_RO, region);
 288   section_Device_rw(Sect_Device_RW, region);
 289   // Create descriptors for 64k pages
 290   page64k_Device_rw(Page_L1_64k, Page_64k_Device_RW, region);
 291   // Create descriptors for 4k pages
 292   page4k_Device_rw(Page_L1_4k, Page_4k_Device_RW, region);
 293
 294   /*
 295    *  Define MMU flat-map regions and attributes
 296    *
 297    */
 298   // Define Image
 299   MMU_TTSection (&amp;Image$$TTB$$ZI$$Base, (uint32_t)&amp;Image$$VECTORS$$Base     ,    1U, Sect_Normal_Cod);
 300   MMU_TTSection (&amp;Image$$TTB$$ZI$$Base, (uint32_t)&amp;Image$$RW_DATA$$Base     ,    1U, Sect_Normal_RW);
 301   MMU_TTSection (&amp;Image$$TTB$$ZI$$Base, (uint32_t)&amp;Image$$ZI_DATA$$Base     ,    1U, Sect_Normal_RW);
 302
 303   // All DRAM executable, RW, cacheable - applications may choose to divide memory into RO executable
 304   MMU_TTSection (&amp;Image$$TTB$$ZI$$Base, (uint32_t)&amp;Image$$TTB$$ZI$$Base     , 2043U, Sect_Normal);
 305
 306   //--------------------- PERIPHERALS -------------------
 307   MMU_TTSection (&amp;Image$$TTB$$ZI$$Base, &lt;DeviceAbbreviation&gt;_FLASH_BASE0    ,   64U, Sect_Device_RO);
 308   MMU_TTSection (&amp;Image$$TTB$$ZI$$Base, &lt;DeviceAbbreviation&gt;_FLASH_BASE1    ,   64U, Sect_Device_RO);
 309   MMU_TTSection (&amp;Image$$TTB$$ZI$$Base, &lt;DeviceAbbreviation&gt;_SRAM_BASE      ,   64U, Sect_Device_RW);
 310   MMU_TTSection (&amp;Image$$TTB$$ZI$$Base, &lt;DeviceAbbreviation&gt;_VRAM_BASE      ,   32U, Sect_Device_RW);
 311   MMU_TTSection (&amp;Image$$TTB$$ZI$$Base, &lt;DeviceAbbreviation&gt;_ETHERNET_BASE  ,   16U, Sect_Device_RW);
 312   MMU_TTSection (&amp;Image$$TTB$$ZI$$Base, &lt;DeviceAbbreviation&gt;_USB_BASE       ,   16U, Sect_Device_RW);
 313
 314   // Create (16 * 64k)=1MB faulting entries to cover peripheral range
 315   MMU_TTPage64k(&amp;Image$$TTB$$ZI$$Base, PERIPHERAL_A_FAULT                   ,   16U, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, DESCRIPTOR_FAULT);
 316   // Define peripheral range
 317   MMU_TTPage64k(&amp;Image$$TTB$$ZI$$Base, &lt;DeviceAbbreviation&gt;_DAP_BASE        ,    1U, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
 318   MMU_TTPage64k(&amp;Image$$TTB$$ZI$$Base, &lt;DeviceAbbreviation&gt;_SYSTEM_REG_BASE ,    1U, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
 319   MMU_TTPage64k(&amp;Image$$TTB$$ZI$$Base, &lt;DeviceAbbreviation&gt;_SERIAL_BASE     ,    1U, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
 320   MMU_TTPage64k(&amp;Image$$TTB$$ZI$$Base, &lt;DeviceAbbreviation&gt;_AACI_BASE       ,    1U, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
 321   MMU_TTPage64k(&amp;Image$$TTB$$ZI$$Base, &lt;DeviceAbbreviation&gt;_MMCI_BASE       ,    1U, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
 322   MMU_TTPage64k(&amp;Image$$TTB$$ZI$$Base, &lt;DeviceAbbreviation&gt;_KMI0_BASE       ,    2U, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
 323   MMU_TTPage64k(&amp;Image$$TTB$$ZI$$Base, &lt;DeviceAbbreviation&gt;_UART_BASE       ,    4U, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
 324   MMU_TTPage64k(&amp;Image$$TTB$$ZI$$Base, &lt;DeviceAbbreviation&gt;_WDT_BASE        ,    1U, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
 325
 326   // Create (16 * 64k)=1MB faulting entries to cover peripheral range
 327   MMU_TTPage64k(&amp;Image$$TTB$$ZI$$Base, PERIPHERAL_B_FAULT                   ,   16U, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, DESCRIPTOR_FAULT);
 328   // Define peripheral range
 329   MMU_TTPage64k(&amp;Image$$TTB$$ZI$$Base, &lt;DeviceAbbreviation&gt;_TIMER_BASE      ,    2U, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
 330   MMU_TTPage64k(&amp;Image$$TTB$$ZI$$Base, &lt;DeviceAbbreviation&gt;_DVI_BASE        ,    1U, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
 331   MMU_TTPage64k(&amp;Image$$TTB$$ZI$$Base, &lt;DeviceAbbreviation&gt;_RTC_BASE        ,    1U, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
 332   MMU_TTPage64k(&amp;Image$$TTB$$ZI$$Base, &lt;DeviceAbbreviation&gt;_UART4_BASE      ,    1U, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
 333   MMU_TTPage64k(&amp;Image$$TTB$$ZI$$Base, &lt;DeviceAbbreviation&gt;_CLCD_BASE       ,    1U, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
 334
 335   // Create (256 * 4k)=1MB faulting entries to cover private address space. Needs to be marked as Device memory
 336   MMU_TTPage4k (&amp;Image$$TTB$$ZI$$Base, __get_CBAR()                         ,  256U,  Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, DESCRIPTOR_FAULT);
 337   // Define private address space entry
 338   MMU_TTPage4k (&amp;Image$$TTB$$ZI$$Base, __get_CBAR()                         ,    2U,  Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, Page_4k_Device_RW);
 339   // Define L2CC entry
 340   MMU_TTPage4k (&amp;Image$$TTB$$ZI$$Base, &lt;DeviceAbbreviation&gt;_L2C_BASE        ,    1U,  Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, Page_4k_Device_RW);
 341
 342   // Create (256 * 4k)=1MB faulting entries to synchronization space (Useful if some non-cacheable DMA agent is present in the SoC)
 343   MMU_TTPage4k (&amp;Image$$TTB$$ZI$$Base, F_SYNC_BASE                          ,  256U, Page_L1_4k, (uint32_t *)SYNC_FLAGS_TABLE_L2_BASE_4k, DESCRIPTOR_FAULT);
 344   // Define synchronization space entry.
 345   MMU_TTPage4k (&amp;Image$$TTB$$ZI$$Base, FLAG_SYNC                            ,    1U, Page_L1_4k, (uint32_t *)SYNC_FLAGS_TABLE_L2_BASE_4k, Page_4k_Device_RW);
 346
 347   /* Set location of level 1 page table
 348   ; 31:14 - Translation table base addr (31:14-TTBCR.N, TTBCR.N is 0 out of reset)
 349   ; 13:7  - 0x0
 350   ; 6     - IRGN[0] 0x1  (Inner WB WA)
 351   ; 5     - NOS     0x0  (Non-shared)
 352   ; 4:3   - RGN     0x01 (Outer WB WA)
 353   ; 2     - IMP     0x0  (Implementation Defined)
 354   ; 1     - S       0x0  (Non-shared)
 355   ; 0     - IRGN[1] 0x0  (Inner WB WA) */
 356   __set_TTBR0(((uint32_t)&amp;Image$$TTB$$ZI$$Base) | 0x48);
 357   __ISB();
 358
 359   /* Set up domain access control register
 360   ; We set domain 0 to Client and all other domains to No Access.
 361   ; All translation table entries specify domain 0 */
 362   __set_DACR(1);
 363   __ISB();
 364 }
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