begriffs open source - cmsis/blob - v6.0.0/Driver/group__nand__bus__mode__codes.html

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  43    <div id="projectname">CMSIS-Driver
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  52    <div id="projectbrief">Peripheral Interface for Middleware and Application Code</div>
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 126 <div class="header">
 127   <div class="summary">
 128 <a href="#define-members">Macros</a>  </div>
 129   <div class="headertitle"><div class="title">NAND Bus Modes<div class="ingroups"><a class="el" href="group__nand__interface__gr.html">NAND Interface</a> &raquo; <a class="el" href="group__nand__control__gr.html">NAND Control Codes</a></div></div></div>
 130 </div><!--header-->
 131 <div class="contents">
 132
 133 <p>Specify bus mode of the NAND interface.
 134 <a href="#details">More...</a></p>
 135 <table class="memberdecls">
 136 <tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="define-members" name="define-members"></a>
 137 Macros</h2></td></tr>
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 139 <tr class="memdesc:gac7743aeb6411b97f9fc6a24b556f4963"><td class="mdescLeft">&#160;</td><td class="mdescRight">Data Interface: SDR (Single Data Rate) - Traditional interface (default)  <br /></td></tr>
 140 <tr class="separator:gac7743aeb6411b97f9fc6a24b556f4963"><td class="memSeparator" colspan="2">&#160;</td></tr>
 141 <tr class="memitem:ga82b8261b3d0d85881535adada318a7df"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#ga82b8261b3d0d85881535adada318a7df">ARM_NAND_BUS_DDR</a>&#160;&#160;&#160;(0x01UL &lt;&lt; <a class="el" href="Driver__NAND_8h.html#a372fc9b9cc1315046ceaffd6fd99e12c">ARM_NAND_BUS_INTERFACE_Pos</a>)</td></tr>
 142 <tr class="memdesc:ga82b8261b3d0d85881535adada318a7df"><td class="mdescLeft">&#160;</td><td class="mdescRight">Data Interface: NV-DDR (Double Data Rate)  <br /></td></tr>
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 145 <tr class="memdesc:ga13c102201d6021db184a2f068656c518"><td class="mdescLeft">&#160;</td><td class="mdescRight">Data Interface: NV-DDR2 (Double Data Rate)  <br /></td></tr>
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 148 <tr class="memdesc:ga971e574ac412bbba445055e9afc384ba"><td class="mdescLeft">&#160;</td><td class="mdescRight">Timing Mode 0 (default)  <br /></td></tr>
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 151 <tr class="memdesc:ga475a339e929eca46e11bc8a7b330aa45"><td class="mdescLeft">&#160;</td><td class="mdescRight">Timing Mode 1.  <br /></td></tr>
 152 <tr class="separator:ga475a339e929eca46e11bc8a7b330aa45"><td class="memSeparator" colspan="2">&#160;</td></tr>
 153 <tr class="memitem:gaed6154fb03b5516faf0bfd11d7a46309"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#gaed6154fb03b5516faf0bfd11d7a46309">ARM_NAND_BUS_TIMING_MODE_2</a>&#160;&#160;&#160;(0x02UL &lt;&lt; <a class="el" href="Driver__NAND_8h.html#acc98e42d23656734c7f9a8a5421842d6">ARM_NAND_BUS_TIMING_MODE_Pos</a>)</td></tr>
 154 <tr class="memdesc:gaed6154fb03b5516faf0bfd11d7a46309"><td class="mdescLeft">&#160;</td><td class="mdescRight">Timing Mode 2.  <br /></td></tr>
 155 <tr class="separator:gaed6154fb03b5516faf0bfd11d7a46309"><td class="memSeparator" colspan="2">&#160;</td></tr>
 156 <tr class="memitem:gacbc4e07e1af6ef0e4c656428e81464a9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#gacbc4e07e1af6ef0e4c656428e81464a9">ARM_NAND_BUS_TIMING_MODE_3</a>&#160;&#160;&#160;(0x03UL &lt;&lt; <a class="el" href="Driver__NAND_8h.html#acc98e42d23656734c7f9a8a5421842d6">ARM_NAND_BUS_TIMING_MODE_Pos</a>)</td></tr>
 157 <tr class="memdesc:gacbc4e07e1af6ef0e4c656428e81464a9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Timing Mode 3.  <br /></td></tr>
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 160 <tr class="memdesc:ga709d51a5215cd23ce2d85aec57141456"><td class="mdescLeft">&#160;</td><td class="mdescRight">Timing Mode 4 (SDR EDO capable)  <br /></td></tr>
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 162 <tr class="memitem:gaee3cad14ce2b8b9af69149bf74597791"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#gaee3cad14ce2b8b9af69149bf74597791">ARM_NAND_BUS_TIMING_MODE_5</a>&#160;&#160;&#160;(0x05UL &lt;&lt; <a class="el" href="Driver__NAND_8h.html#acc98e42d23656734c7f9a8a5421842d6">ARM_NAND_BUS_TIMING_MODE_Pos</a>)</td></tr>
 163 <tr class="memdesc:gaee3cad14ce2b8b9af69149bf74597791"><td class="mdescLeft">&#160;</td><td class="mdescRight">Timing Mode 5 (SDR EDO capable)  <br /></td></tr>
 164 <tr class="separator:gaee3cad14ce2b8b9af69149bf74597791"><td class="memSeparator" colspan="2">&#160;</td></tr>
 165 <tr class="memitem:ga4a3524e0eba994b3a66e06cde877f0f6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#ga4a3524e0eba994b3a66e06cde877f0f6">ARM_NAND_BUS_TIMING_MODE_6</a>&#160;&#160;&#160;(0x06UL &lt;&lt; <a class="el" href="Driver__NAND_8h.html#acc98e42d23656734c7f9a8a5421842d6">ARM_NAND_BUS_TIMING_MODE_Pos</a>)</td></tr>
 166 <tr class="memdesc:ga4a3524e0eba994b3a66e06cde877f0f6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Timing Mode 6 (NV-DDR2 only)  <br /></td></tr>
 167 <tr class="separator:ga4a3524e0eba994b3a66e06cde877f0f6"><td class="memSeparator" colspan="2">&#160;</td></tr>
 168 <tr class="memitem:gaa63d75f5f2b48a7345a066d58de1bd23"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#gaa63d75f5f2b48a7345a066d58de1bd23">ARM_NAND_BUS_TIMING_MODE_7</a>&#160;&#160;&#160;(0x07UL &lt;&lt; <a class="el" href="Driver__NAND_8h.html#acc98e42d23656734c7f9a8a5421842d6">ARM_NAND_BUS_TIMING_MODE_Pos</a>)</td></tr>
 169 <tr class="memdesc:gaa63d75f5f2b48a7345a066d58de1bd23"><td class="mdescLeft">&#160;</td><td class="mdescRight">Timing Mode 7 (NV-DDR2 only)  <br /></td></tr>
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 172 <tr class="memdesc:ga77348df5f5c2c96bcaeec60b6da02c1b"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDR2 Data Output Warm-up cycles: 0 (default)  <br /></td></tr>
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 175 <tr class="memdesc:ga5839be0b4b2eb930ec039a3403b5e89e"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDR2 Data Output Warm-up cycles: 1.  <br /></td></tr>
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 178 <tr class="memdesc:ga10a1ef3be69bfa7e6cc657bee751a077"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDR2 Data Output Warm-up cycles: 2.  <br /></td></tr>
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 181 <tr class="memdesc:ga7f9e8416c4a4e20c4a04323e39f2100d"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDR2 Data Output Warm-up cycles: 4.  <br /></td></tr>
 182 <tr class="separator:ga7f9e8416c4a4e20c4a04323e39f2100d"><td class="memSeparator" colspan="2">&#160;</td></tr>
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 184 <tr class="memdesc:gaeee1853dea5e96cb19d2596cc0e70169"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDR2 Data Input Warm-up cycles: 0 (default)  <br /></td></tr>
 185 <tr class="separator:gaeee1853dea5e96cb19d2596cc0e70169"><td class="memSeparator" colspan="2">&#160;</td></tr>
 186 <tr class="memitem:ga42560a1f046e20cc4956276156c4ce25"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#ga42560a1f046e20cc4956276156c4ce25">ARM_NAND_BUS_DDR2_DI_WCYC_1</a>&#160;&#160;&#160;(0x01UL &lt;&lt; <a class="el" href="Driver__NAND_8h.html#aa80b898cdf665aa14ff0e181e4ff31f1">ARM_NAND_BUS_DDR2_DI_WCYC_Pos</a>)</td></tr>
 187 <tr class="memdesc:ga42560a1f046e20cc4956276156c4ce25"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDR2 Data Input Warm-up cycles: 1.  <br /></td></tr>
 188 <tr class="separator:ga42560a1f046e20cc4956276156c4ce25"><td class="memSeparator" colspan="2">&#160;</td></tr>
 189 <tr class="memitem:gaad2e7807292d84a5070143626f5c2756"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#gaad2e7807292d84a5070143626f5c2756">ARM_NAND_BUS_DDR2_DI_WCYC_2</a>&#160;&#160;&#160;(0x02UL &lt;&lt; <a class="el" href="Driver__NAND_8h.html#aa80b898cdf665aa14ff0e181e4ff31f1">ARM_NAND_BUS_DDR2_DI_WCYC_Pos</a>)</td></tr>
 190 <tr class="memdesc:gaad2e7807292d84a5070143626f5c2756"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDR2 Data Input Warm-up cycles: 2.  <br /></td></tr>
 191 <tr class="separator:gaad2e7807292d84a5070143626f5c2756"><td class="memSeparator" colspan="2">&#160;</td></tr>
 192 <tr class="memitem:ga3ebb54a1ae971cd34f3c8fc9ff3ab6d5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#ga3ebb54a1ae971cd34f3c8fc9ff3ab6d5">ARM_NAND_BUS_DDR2_DI_WCYC_4</a>&#160;&#160;&#160;(0x03UL &lt;&lt; <a class="el" href="Driver__NAND_8h.html#aa80b898cdf665aa14ff0e181e4ff31f1">ARM_NAND_BUS_DDR2_DI_WCYC_Pos</a>)</td></tr>
 193 <tr class="memdesc:ga3ebb54a1ae971cd34f3c8fc9ff3ab6d5"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDR2 Data Input Warm-up cycles: 4.  <br /></td></tr>
 194 <tr class="separator:ga3ebb54a1ae971cd34f3c8fc9ff3ab6d5"><td class="memSeparator" colspan="2">&#160;</td></tr>
 195 <tr class="memitem:ga465ae06a6e097959620346304182e273"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#ga465ae06a6e097959620346304182e273">ARM_NAND_BUS_DDR2_VEN</a>&#160;&#160;&#160;(1UL &lt;&lt; 16)</td></tr>
 196 <tr class="memdesc:ga465ae06a6e097959620346304182e273"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDR2 Enable external VREFQ as reference.  <br /></td></tr>
 197 <tr class="separator:ga465ae06a6e097959620346304182e273"><td class="memSeparator" colspan="2">&#160;</td></tr>
 198 <tr class="memitem:gad38354e4a34adbf881afc7f89ff06e89"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#gad38354e4a34adbf881afc7f89ff06e89">ARM_NAND_BUS_DDR2_CMPD</a>&#160;&#160;&#160;(1UL &lt;&lt; 17)</td></tr>
 199 <tr class="memdesc:gad38354e4a34adbf881afc7f89ff06e89"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDR2 Enable complementary DQS (DQS_c) signal.  <br /></td></tr>
 200 <tr class="separator:gad38354e4a34adbf881afc7f89ff06e89"><td class="memSeparator" colspan="2">&#160;</td></tr>
 201 <tr class="memitem:ga8a2d599082b9fe56cee1c6454bb3c6a1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__nand__bus__mode__codes.html#ga8a2d599082b9fe56cee1c6454bb3c6a1">ARM_NAND_BUS_DDR2_CMPR</a>&#160;&#160;&#160;(1UL &lt;&lt; 18)</td></tr>
 202 <tr class="memdesc:ga8a2d599082b9fe56cee1c6454bb3c6a1"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDR2 Enable complementary RE_n (RE_c) signal.  <br /></td></tr>
 203 <tr class="separator:ga8a2d599082b9fe56cee1c6454bb3c6a1"><td class="memSeparator" colspan="2">&#160;</td></tr>
 204 </table>
 205 <a name="details" id="details"></a><h2 class="groupheader">Description</h2>
 206 <p>Specify bus mode of the NAND interface. </p>
 207 <p>The defines can be used in the function <a class="el" href="group__nand__interface__gr.html#ga83061d6d53ffb148853efbc87a864607">ARM_NAND_Control</a> for the parameter <em>arg</em> and with the <a class="el" href="Driver__NAND_8h.html#a9b063c3078e86b50d4aa892518b2e2d8">ARM_NAND_BUS_MODE</a> as the <em>control</em> code. </p>
 208 <h2 class="groupheader">Macro Definition Documentation</h2>
 209 <a id="gac7743aeb6411b97f9fc6a24b556f4963" name="gac7743aeb6411b97f9fc6a24b556f4963"></a>
 210 <h2 class="memtitle"><span class="permalink"><a href="#gac7743aeb6411b97f9fc6a24b556f4963">&#9670;&#160;</a></span>ARM_NAND_BUS_SDR</h2>
 211
 212 <div class="memitem">
 213 <div class="memproto">
 214       <table class="memname">
 215         <tr>
 216           <td class="memname">#define ARM_NAND_BUS_SDR&#160;&#160;&#160;(0x00UL &lt;&lt; <a class="el" href="Driver__NAND_8h.html#a372fc9b9cc1315046ceaffd6fd99e12c">ARM_NAND_BUS_INTERFACE_Pos</a>)</td>
 217         </tr>
 218       </table>
 219 </div><div class="memdoc">
 220
 221 <p>Data Interface: SDR (Single Data Rate) - Traditional interface (default) </p>
 222
 223 </div>
 224 </div>
 225 <a id="ga82b8261b3d0d85881535adada318a7df" name="ga82b8261b3d0d85881535adada318a7df"></a>
 226 <h2 class="memtitle"><span class="permalink"><a href="#ga82b8261b3d0d85881535adada318a7df">&#9670;&#160;</a></span>ARM_NAND_BUS_DDR</h2>
 227
 228 <div class="memitem">
 229 <div class="memproto">
 230       <table class="memname">
 231         <tr>
 232           <td class="memname">#define ARM_NAND_BUS_DDR&#160;&#160;&#160;(0x01UL &lt;&lt; <a class="el" href="Driver__NAND_8h.html#a372fc9b9cc1315046ceaffd6fd99e12c">ARM_NAND_BUS_INTERFACE_Pos</a>)</td>
 233         </tr>
 234       </table>
 235 </div><div class="memdoc">
 236
 237 <p>Data Interface: NV-DDR (Double Data Rate) </p>
 238
 239 </div>
 240 </div>
 241 <a id="ga13c102201d6021db184a2f068656c518" name="ga13c102201d6021db184a2f068656c518"></a>
 242 <h2 class="memtitle"><span class="permalink"><a href="#ga13c102201d6021db184a2f068656c518">&#9670;&#160;</a></span>ARM_NAND_BUS_DDR2</h2>
 243
 244 <div class="memitem">
 245 <div class="memproto">
 246       <table class="memname">
 247         <tr>
 248           <td class="memname">#define ARM_NAND_BUS_DDR2&#160;&#160;&#160;(0x02UL &lt;&lt; <a class="el" href="Driver__NAND_8h.html#a372fc9b9cc1315046ceaffd6fd99e12c">ARM_NAND_BUS_INTERFACE_Pos</a>)</td>
 249         </tr>
 250       </table>
 251 </div><div class="memdoc">
 252
 253 <p>Data Interface: NV-DDR2 (Double Data Rate) </p>
 254
 255 </div>
 256 </div>
 257 <a id="ga971e574ac412bbba445055e9afc384ba" name="ga971e574ac412bbba445055e9afc384ba"></a>
 258 <h2 class="memtitle"><span class="permalink"><a href="#ga971e574ac412bbba445055e9afc384ba">&#9670;&#160;</a></span>ARM_NAND_BUS_TIMING_MODE_0</h2>
 259
 260 <div class="memitem">
 261 <div class="memproto">
 262       <table class="memname">
 263         <tr>
 264           <td class="memname">#define ARM_NAND_BUS_TIMING_MODE_0&#160;&#160;&#160;(0x00UL &lt;&lt; <a class="el" href="Driver__NAND_8h.html#acc98e42d23656734c7f9a8a5421842d6">ARM_NAND_BUS_TIMING_MODE_Pos</a>)</td>
 265         </tr>
 266       </table>
 267 </div><div class="memdoc">
 268
 269 <p>Timing Mode 0 (default) </p>
 270
 271 </div>
 272 </div>
 273 <a id="ga475a339e929eca46e11bc8a7b330aa45" name="ga475a339e929eca46e11bc8a7b330aa45"></a>
 274 <h2 class="memtitle"><span class="permalink"><a href="#ga475a339e929eca46e11bc8a7b330aa45">&#9670;&#160;</a></span>ARM_NAND_BUS_TIMING_MODE_1</h2>
 275
 276 <div class="memitem">
 277 <div class="memproto">
 278       <table class="memname">
 279         <tr>
 280           <td class="memname">#define ARM_NAND_BUS_TIMING_MODE_1&#160;&#160;&#160;(0x01UL &lt;&lt; <a class="el" href="Driver__NAND_8h.html#acc98e42d23656734c7f9a8a5421842d6">ARM_NAND_BUS_TIMING_MODE_Pos</a>)</td>
 281         </tr>
 282       </table>
 283 </div><div class="memdoc">
 284
 285 <p>Timing Mode 1. </p>
 286
 287 </div>
 288 </div>
 289 <a id="gaed6154fb03b5516faf0bfd11d7a46309" name="gaed6154fb03b5516faf0bfd11d7a46309"></a>
 290 <h2 class="memtitle"><span class="permalink"><a href="#gaed6154fb03b5516faf0bfd11d7a46309">&#9670;&#160;</a></span>ARM_NAND_BUS_TIMING_MODE_2</h2>
 291
 292 <div class="memitem">
 293 <div class="memproto">
 294       <table class="memname">
 295         <tr>
 296           <td class="memname">#define ARM_NAND_BUS_TIMING_MODE_2&#160;&#160;&#160;(0x02UL &lt;&lt; <a class="el" href="Driver__NAND_8h.html#acc98e42d23656734c7f9a8a5421842d6">ARM_NAND_BUS_TIMING_MODE_Pos</a>)</td>
 297         </tr>
 298       </table>
 299 </div><div class="memdoc">
 300
 301 <p>Timing Mode 2. </p>
 302
 303 </div>
 304 </div>
 305 <a id="gacbc4e07e1af6ef0e4c656428e81464a9" name="gacbc4e07e1af6ef0e4c656428e81464a9"></a>
 306 <h2 class="memtitle"><span class="permalink"><a href="#gacbc4e07e1af6ef0e4c656428e81464a9">&#9670;&#160;</a></span>ARM_NAND_BUS_TIMING_MODE_3</h2>
 307
 308 <div class="memitem">
 309 <div class="memproto">
 310       <table class="memname">
 311         <tr>
 312           <td class="memname">#define ARM_NAND_BUS_TIMING_MODE_3&#160;&#160;&#160;(0x03UL &lt;&lt; <a class="el" href="Driver__NAND_8h.html#acc98e42d23656734c7f9a8a5421842d6">ARM_NAND_BUS_TIMING_MODE_Pos</a>)</td>
 313         </tr>
 314       </table>
 315 </div><div class="memdoc">
 316
 317 <p>Timing Mode 3. </p>
 318
 319 </div>
 320 </div>
 321 <a id="ga709d51a5215cd23ce2d85aec57141456" name="ga709d51a5215cd23ce2d85aec57141456"></a>
 322 <h2 class="memtitle"><span class="permalink"><a href="#ga709d51a5215cd23ce2d85aec57141456">&#9670;&#160;</a></span>ARM_NAND_BUS_TIMING_MODE_4</h2>
 323
 324 <div class="memitem">
 325 <div class="memproto">
 326       <table class="memname">
 327         <tr>
 328           <td class="memname">#define ARM_NAND_BUS_TIMING_MODE_4&#160;&#160;&#160;(0x04UL &lt;&lt; <a class="el" href="Driver__NAND_8h.html#acc98e42d23656734c7f9a8a5421842d6">ARM_NAND_BUS_TIMING_MODE_Pos</a>)</td>
 329         </tr>
 330       </table>
 331 </div><div class="memdoc">
 332
 333 <p>Timing Mode 4 (SDR EDO capable) </p>
 334
 335 </div>
 336 </div>
 337 <a id="gaee3cad14ce2b8b9af69149bf74597791" name="gaee3cad14ce2b8b9af69149bf74597791"></a>
 338 <h2 class="memtitle"><span class="permalink"><a href="#gaee3cad14ce2b8b9af69149bf74597791">&#9670;&#160;</a></span>ARM_NAND_BUS_TIMING_MODE_5</h2>
 339
 340 <div class="memitem">
 341 <div class="memproto">
 342       <table class="memname">
 343         <tr>
 344           <td class="memname">#define ARM_NAND_BUS_TIMING_MODE_5&#160;&#160;&#160;(0x05UL &lt;&lt; <a class="el" href="Driver__NAND_8h.html#acc98e42d23656734c7f9a8a5421842d6">ARM_NAND_BUS_TIMING_MODE_Pos</a>)</td>
 345         </tr>
 346       </table>
 347 </div><div class="memdoc">
 348
 349 <p>Timing Mode 5 (SDR EDO capable) </p>
 350
 351 </div>
 352 </div>
 353 <a id="ga4a3524e0eba994b3a66e06cde877f0f6" name="ga4a3524e0eba994b3a66e06cde877f0f6"></a>
 354 <h2 class="memtitle"><span class="permalink"><a href="#ga4a3524e0eba994b3a66e06cde877f0f6">&#9670;&#160;</a></span>ARM_NAND_BUS_TIMING_MODE_6</h2>
 355
 356 <div class="memitem">
 357 <div class="memproto">
 358       <table class="memname">
 359         <tr>
 360           <td class="memname">#define ARM_NAND_BUS_TIMING_MODE_6&#160;&#160;&#160;(0x06UL &lt;&lt; <a class="el" href="Driver__NAND_8h.html#acc98e42d23656734c7f9a8a5421842d6">ARM_NAND_BUS_TIMING_MODE_Pos</a>)</td>
 361         </tr>
 362       </table>
 363 </div><div class="memdoc">
 364
 365 <p>Timing Mode 6 (NV-DDR2 only) </p>
 366
 367 </div>
 368 </div>
 369 <a id="gaa63d75f5f2b48a7345a066d58de1bd23" name="gaa63d75f5f2b48a7345a066d58de1bd23"></a>
 370 <h2 class="memtitle"><span class="permalink"><a href="#gaa63d75f5f2b48a7345a066d58de1bd23">&#9670;&#160;</a></span>ARM_NAND_BUS_TIMING_MODE_7</h2>
 371
 372 <div class="memitem">
 373 <div class="memproto">
 374       <table class="memname">
 375         <tr>
 376           <td class="memname">#define ARM_NAND_BUS_TIMING_MODE_7&#160;&#160;&#160;(0x07UL &lt;&lt; <a class="el" href="Driver__NAND_8h.html#acc98e42d23656734c7f9a8a5421842d6">ARM_NAND_BUS_TIMING_MODE_Pos</a>)</td>
 377         </tr>
 378       </table>
 379 </div><div class="memdoc">
 380
 381 <p>Timing Mode 7 (NV-DDR2 only) </p>
 382
 383 </div>
 384 </div>
 385 <a id="ga77348df5f5c2c96bcaeec60b6da02c1b" name="ga77348df5f5c2c96bcaeec60b6da02c1b"></a>
 386 <h2 class="memtitle"><span class="permalink"><a href="#ga77348df5f5c2c96bcaeec60b6da02c1b">&#9670;&#160;</a></span>ARM_NAND_BUS_DDR2_DO_WCYC_0</h2>
 387
 388 <div class="memitem">
 389 <div class="memproto">
 390       <table class="memname">
 391         <tr>
 392           <td class="memname">#define ARM_NAND_BUS_DDR2_DO_WCYC_0&#160;&#160;&#160;(0x00UL &lt;&lt; <a class="el" href="Driver__NAND_8h.html#a57b282c0818c87b79ea4f11d03cc4f3c">ARM_NAND_BUS_DDR2_DO_WCYC_Pos</a>)</td>
 393         </tr>
 394       </table>
 395 </div><div class="memdoc">
 396
 397 <p>DDR2 Data Output Warm-up cycles: 0 (default) </p>
 398
 399 </div>
 400 </div>
 401 <a id="ga5839be0b4b2eb930ec039a3403b5e89e" name="ga5839be0b4b2eb930ec039a3403b5e89e"></a>
 402 <h2 class="memtitle"><span class="permalink"><a href="#ga5839be0b4b2eb930ec039a3403b5e89e">&#9670;&#160;</a></span>ARM_NAND_BUS_DDR2_DO_WCYC_1</h2>
 403
 404 <div class="memitem">
 405 <div class="memproto">
 406       <table class="memname">
 407         <tr>
 408           <td class="memname">#define ARM_NAND_BUS_DDR2_DO_WCYC_1&#160;&#160;&#160;(0x01UL &lt;&lt; <a class="el" href="Driver__NAND_8h.html#a57b282c0818c87b79ea4f11d03cc4f3c">ARM_NAND_BUS_DDR2_DO_WCYC_Pos</a>)</td>
 409         </tr>
 410       </table>
 411 </div><div class="memdoc">
 412
 413 <p>DDR2 Data Output Warm-up cycles: 1. </p>
 414
 415 </div>
 416 </div>
 417 <a id="ga10a1ef3be69bfa7e6cc657bee751a077" name="ga10a1ef3be69bfa7e6cc657bee751a077"></a>
 418 <h2 class="memtitle"><span class="permalink"><a href="#ga10a1ef3be69bfa7e6cc657bee751a077">&#9670;&#160;</a></span>ARM_NAND_BUS_DDR2_DO_WCYC_2</h2>
 419
 420 <div class="memitem">
 421 <div class="memproto">
 422       <table class="memname">
 423         <tr>
 424           <td class="memname">#define ARM_NAND_BUS_DDR2_DO_WCYC_2&#160;&#160;&#160;(0x02UL &lt;&lt; <a class="el" href="Driver__NAND_8h.html#a57b282c0818c87b79ea4f11d03cc4f3c">ARM_NAND_BUS_DDR2_DO_WCYC_Pos</a>)</td>
 425         </tr>
 426       </table>
 427 </div><div class="memdoc">
 428
 429 <p>DDR2 Data Output Warm-up cycles: 2. </p>
 430
 431 </div>
 432 </div>
 433 <a id="ga7f9e8416c4a4e20c4a04323e39f2100d" name="ga7f9e8416c4a4e20c4a04323e39f2100d"></a>
 434 <h2 class="memtitle"><span class="permalink"><a href="#ga7f9e8416c4a4e20c4a04323e39f2100d">&#9670;&#160;</a></span>ARM_NAND_BUS_DDR2_DO_WCYC_4</h2>
 435
 436 <div class="memitem">
 437 <div class="memproto">
 438       <table class="memname">
 439         <tr>
 440           <td class="memname">#define ARM_NAND_BUS_DDR2_DO_WCYC_4&#160;&#160;&#160;(0x03UL &lt;&lt; <a class="el" href="Driver__NAND_8h.html#a57b282c0818c87b79ea4f11d03cc4f3c">ARM_NAND_BUS_DDR2_DO_WCYC_Pos</a>)</td>
 441         </tr>
 442       </table>
 443 </div><div class="memdoc">
 444
 445 <p>DDR2 Data Output Warm-up cycles: 4. </p>
 446
 447 </div>
 448 </div>
 449 <a id="gaeee1853dea5e96cb19d2596cc0e70169" name="gaeee1853dea5e96cb19d2596cc0e70169"></a>
 450 <h2 class="memtitle"><span class="permalink"><a href="#gaeee1853dea5e96cb19d2596cc0e70169">&#9670;&#160;</a></span>ARM_NAND_BUS_DDR2_DI_WCYC_0</h2>
 451
 452 <div class="memitem">
 453 <div class="memproto">
 454       <table class="memname">
 455         <tr>
 456           <td class="memname">#define ARM_NAND_BUS_DDR2_DI_WCYC_0&#160;&#160;&#160;(0x00UL &lt;&lt; <a class="el" href="Driver__NAND_8h.html#aa80b898cdf665aa14ff0e181e4ff31f1">ARM_NAND_BUS_DDR2_DI_WCYC_Pos</a>)</td>
 457         </tr>
 458       </table>
 459 </div><div class="memdoc">
 460
 461 <p>DDR2 Data Input Warm-up cycles: 0 (default) </p>
 462
 463 </div>
 464 </div>
 465 <a id="ga42560a1f046e20cc4956276156c4ce25" name="ga42560a1f046e20cc4956276156c4ce25"></a>
 466 <h2 class="memtitle"><span class="permalink"><a href="#ga42560a1f046e20cc4956276156c4ce25">&#9670;&#160;</a></span>ARM_NAND_BUS_DDR2_DI_WCYC_1</h2>
 467
 468 <div class="memitem">
 469 <div class="memproto">
 470       <table class="memname">
 471         <tr>
 472           <td class="memname">#define ARM_NAND_BUS_DDR2_DI_WCYC_1&#160;&#160;&#160;(0x01UL &lt;&lt; <a class="el" href="Driver__NAND_8h.html#aa80b898cdf665aa14ff0e181e4ff31f1">ARM_NAND_BUS_DDR2_DI_WCYC_Pos</a>)</td>
 473         </tr>
 474       </table>
 475 </div><div class="memdoc">
 476
 477 <p>DDR2 Data Input Warm-up cycles: 1. </p>
 478
 479 </div>
 480 </div>
 481 <a id="gaad2e7807292d84a5070143626f5c2756" name="gaad2e7807292d84a5070143626f5c2756"></a>
 482 <h2 class="memtitle"><span class="permalink"><a href="#gaad2e7807292d84a5070143626f5c2756">&#9670;&#160;</a></span>ARM_NAND_BUS_DDR2_DI_WCYC_2</h2>
 483
 484 <div class="memitem">
 485 <div class="memproto">
 486       <table class="memname">
 487         <tr>
 488           <td class="memname">#define ARM_NAND_BUS_DDR2_DI_WCYC_2&#160;&#160;&#160;(0x02UL &lt;&lt; <a class="el" href="Driver__NAND_8h.html#aa80b898cdf665aa14ff0e181e4ff31f1">ARM_NAND_BUS_DDR2_DI_WCYC_Pos</a>)</td>
 489         </tr>
 490       </table>
 491 </div><div class="memdoc">
 492
 493 <p>DDR2 Data Input Warm-up cycles: 2. </p>
 494
 495 </div>
 496 </div>
 497 <a id="ga3ebb54a1ae971cd34f3c8fc9ff3ab6d5" name="ga3ebb54a1ae971cd34f3c8fc9ff3ab6d5"></a>
 498 <h2 class="memtitle"><span class="permalink"><a href="#ga3ebb54a1ae971cd34f3c8fc9ff3ab6d5">&#9670;&#160;</a></span>ARM_NAND_BUS_DDR2_DI_WCYC_4</h2>
 499
 500 <div class="memitem">
 501 <div class="memproto">
 502       <table class="memname">
 503         <tr>
 504           <td class="memname">#define ARM_NAND_BUS_DDR2_DI_WCYC_4&#160;&#160;&#160;(0x03UL &lt;&lt; <a class="el" href="Driver__NAND_8h.html#aa80b898cdf665aa14ff0e181e4ff31f1">ARM_NAND_BUS_DDR2_DI_WCYC_Pos</a>)</td>
 505         </tr>
 506       </table>
 507 </div><div class="memdoc">
 508
 509 <p>DDR2 Data Input Warm-up cycles: 4. </p>
 510
 511 </div>
 512 </div>
 513 <a id="ga465ae06a6e097959620346304182e273" name="ga465ae06a6e097959620346304182e273"></a>
 514 <h2 class="memtitle"><span class="permalink"><a href="#ga465ae06a6e097959620346304182e273">&#9670;&#160;</a></span>ARM_NAND_BUS_DDR2_VEN</h2>
 515
 516 <div class="memitem">
 517 <div class="memproto">
 518       <table class="memname">
 519         <tr>
 520           <td class="memname">#define ARM_NAND_BUS_DDR2_VEN&#160;&#160;&#160;(1UL &lt;&lt; 16)</td>
 521         </tr>
 522       </table>
 523 </div><div class="memdoc">
 524
 525 <p>DDR2 Enable external VREFQ as reference. </p>
 526
 527 </div>
 528 </div>
 529 <a id="gad38354e4a34adbf881afc7f89ff06e89" name="gad38354e4a34adbf881afc7f89ff06e89"></a>
 530 <h2 class="memtitle"><span class="permalink"><a href="#gad38354e4a34adbf881afc7f89ff06e89">&#9670;&#160;</a></span>ARM_NAND_BUS_DDR2_CMPD</h2>
 531
 532 <div class="memitem">
 533 <div class="memproto">
 534       <table class="memname">
 535         <tr>
 536           <td class="memname">#define ARM_NAND_BUS_DDR2_CMPD&#160;&#160;&#160;(1UL &lt;&lt; 17)</td>
 537         </tr>
 538       </table>
 539 </div><div class="memdoc">
 540
 541 <p>DDR2 Enable complementary DQS (DQS_c) signal. </p>
 542
 543 </div>
 544 </div>
 545 <a id="ga8a2d599082b9fe56cee1c6454bb3c6a1" name="ga8a2d599082b9fe56cee1c6454bb3c6a1"></a>
 546 <h2 class="memtitle"><span class="permalink"><a href="#ga8a2d599082b9fe56cee1c6454bb3c6a1">&#9670;&#160;</a></span>ARM_NAND_BUS_DDR2_CMPR</h2>
 547
 548 <div class="memitem">
 549 <div class="memproto">
 550       <table class="memname">
 551         <tr>
 552           <td class="memname">#define ARM_NAND_BUS_DDR2_CMPR&#160;&#160;&#160;(1UL &lt;&lt; 18)</td>
 553         </tr>
 554       </table>
 555 </div><div class="memdoc">
 556
 557 <p>DDR2 Enable complementary RE_n (RE_c) signal. </p>
 558
 559 </div>
 560 </div>
 561 </div><!-- contents -->
 562 </div><!-- doc-content -->
 563 <!-- start footer part -->
 564 <div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
 565   <ul>
 566     <li class="footer">
 567       <script type="text/javascript">
 568         <!--
 569         writeFooter.call(this);
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