1 /**************************************************************************//**
3 * @brief CMSIS OS Tick SysTick implementation
5 * @date 20. January 2023
6 ******************************************************************************/
8 * Copyright (c) 2017-2023 ARM Limited. All rights reserved.
10 * SPDX-License-Identifier: Apache-2.0
12 * Licensed under the Apache License, Version 2.0 (the License); you may
13 * not use this file except in compliance with the License.
14 * You may obtain a copy of the License at
16 * www.apache.org/licenses/LICENSE-2.0
18 * Unless required by applicable law or agreed to in writing, software
19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 * See the License for the specific language governing permissions and
22 * limitations under the License.
27 //lint -emacro((923,9078),SCB,SysTick) "cast from unsigned long to pointer"
28 #include "RTE_Components.h"
29 #include CMSIS_device_header
33 #ifndef SYSTICK_IRQ_PRIORITY
34 #define SYSTICK_IRQ_PRIORITY 0xFFU
37 static uint8_t PendST __attribute__((section(".bss.os")));
40 __WEAK int32_t OS_Tick_Setup (uint32_t freq, IRQHandler_t handler) {
45 //lint -e{904} "Return statement before end of function"
49 load = (SystemCoreClock / freq) - 1U;
50 if (load > 0x00FFFFFFU) {
51 //lint -e{904} "Return statement before end of function"
55 // Set SysTick Interrupt Priority
56 #if ((defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ != 0)) || \
57 (defined(__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ != 0)) || \
58 (defined(__CORTEX_M) && (__CORTEX_M == 7U)))
59 SCB->SHPR[11] = SYSTICK_IRQ_PRIORITY;
60 #elif (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ != 0))
61 SCB->SHPR[1] |= ((uint32_t)SYSTICK_IRQ_PRIORITY << 24);
62 #elif ((defined(__ARM_ARCH_7M__) && (__ARM_ARCH_7M__ != 0)) || \
63 (defined(__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ != 0)))
64 SCB->SHP[11] = SYSTICK_IRQ_PRIORITY;
65 #elif (defined(__ARM_ARCH_6M__) && (__ARM_ARCH_6M__ != 0))
66 SCB->SHP[1] |= ((uint32_t)SYSTICK_IRQ_PRIORITY << 24);
68 #error "Unknown ARM Core!"
71 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk;
81 __WEAK void OS_Tick_Enable (void) {
85 SCB->ICSR = SCB_ICSR_PENDSTSET_Msk;
88 SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
92 __WEAK void OS_Tick_Disable (void) {
94 SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
96 if ((SCB->ICSR & SCB_ICSR_PENDSTSET_Msk) != 0U) {
97 SCB->ICSR = SCB_ICSR_PENDSTCLR_Msk;
102 // Acknowledge OS Tick IRQ.
103 __WEAK void OS_Tick_AcknowledgeIRQ (void) {
107 // Get OS Tick IRQ number.
108 __WEAK int32_t OS_Tick_GetIRQn (void) {
109 return ((int32_t)SysTick_IRQn);
112 // Get OS Tick clock.
113 __WEAK uint32_t OS_Tick_GetClock (void) {
114 return (SystemCoreClock);
117 // Get OS Tick interval.
118 __WEAK uint32_t OS_Tick_GetInterval (void) {
119 return (SysTick->LOAD + 1U);
122 // Get OS Tick count value.
123 __WEAK uint32_t OS_Tick_GetCount (void) {
129 count = (SysTick->LOAD - val) + 1U;
137 // Get OS Tick overflow status.
138 __WEAK uint32_t OS_Tick_GetOverflow (void) {
139 return ((SCB->ICSR & SCB_ICSR_PENDSTSET_Msk) >> SCB_ICSR_PENDSTSET_Pos);