begriffs open source - cmsis/blob - CMSIS/DoxyGen/Core/src/RegMap_CMSIS2ARM_Doc.txt

   1 /**
   2 \page regMap_pg  Register Mapping
   3
   4 \details
   5
   6 The table below associates some common register names used in CMSIS to the register names
   7 used in Technical Reference Manuals.
   8
   9 <table class="cmtable" summary="Register Mapping">
  10     <tr>
  11       <th>CMSIS Register Name</th>
  12       <th>Cortex-M3, Cortex-M4, and Cortex-M7</th>
  13       <th>Cortex-M0 and Cortex-M0+</th>
  14       <th>Register Name</th>
  15     </tr>
  16     <tr>
  17       <th colspan="4">Nested Vectored Interrupt Controller (NVIC) Register Access</th>
  18     </tr>
  19     <tr>
  20       <td>NVIC->ISER[]</td>
  21       <td>NVIC_ISER0..7</td>
  22       <td>ISER</td>
  23       <td>Interrupt Set-Enable Registers</td>
  24     </tr>
  25     <tr>
  26       <td>NVIC->ICER[]</td>
  27       <td>NVIC_ICER0..7</td>
  28       <td>ICER</td>
  29       <td>Interrupt Clear-Enable Registers</td>
  30     </tr>
  31    <tr>
  32       <td>NVIC->ISPR[]</td>
  33       <td>NVIC_ISPR0..7</td>
  34       <td>ISPR</td>
  35       <td>Interrupt Set-Pending Registers</td>
  36     </tr>
  37   <tr>
  38       <td>NVIC->ICPR[]</td>
  39       <td>NVIC_ICPR0..7</td>
  40       <td>ICPR</td>
  41       <td>Interrupt Clear-Pending Registers</td>
  42     </tr>
  43   <tr>
  44       <td>NVIC->IABR[]</td>
  45       <td>NVIC_IABR0..7</td>
  46       <td>-</td>
  47       <td>Interrupt Active Bit Register</td>
  48   </tr>
  49   <tr>
  50       <td>NVIC->IP[]</td>
  51       <td>NVIC_IPR0..59</td>
  52       <td>IPR0..7</td>
  53       <td>Interrupt Priority Register</td>
  54   </tr>
  55   <tr>
  56       <td>NVIC->STIR</td>
  57       <td>STIR</td>
  58       <td>-</td>
  59       <td>Software Triggered Interrupt Register</td>
  60   </tr>
  61   <tr>
  62     <th colspan="4">System Control Block (SCB) Register Access</th>
  63   </tr>
  64   <tr>
  65       <td>SCB->CPUID</td>
  66       <td>CPUID</td>
  67       <td>CPUID</td>
  68       <td>CPUID Base Register</td>
  69   </tr>
  70   <tr>
  71       <td>SCB->ICSR</td>
  72       <td>ICSR</td>
  73       <td>ICSR</td>
  74       <td>Interrupt Control and State Register</td>
  75   </tr>
  76   <tr>
  77       <td>SCB->VTOR</td>
  78       <td>VTOR</td>
  79       <td>-</td>
  80       <td>Vector Table Offset Register</td>
  81   </tr>
  82   <tr>
  83       <td>SCB->AIRCR</td>
  84       <td>AIRCR</td>
  85       <td>AIRCR</td>
  86       <td>Application Interrupt and Reset Control Register</td>
  87   </tr>
  88   <tr>
  89       <td>SCB->SCR</td>
  90       <td>SCR</td>
  91       <td>SCR</td>
  92       <td>System Control Register</td>
  93   </tr>
  94   <tr>
  95       <td>SCB->CCR</td>
  96       <td>CCR</td>
  97       <td>CCR</td>
  98       <td>Configuration and Control Register</td>
  99   </tr>
 100   <tr>
 101       <td>SCB->SHP[]</td>
 102       <td>SHPR1..3</td>
 103       <td>SHPR2..3</td>
 104       <td>System Handler Priority Registers</td>
 105   </tr>
 106   <tr>
 107       <td>SCB->SHCSR</td>
 108       <td>SHCSR</td>
 109       <td>SHCSR</td>
 110       <td>System Handler Control and State Register</td>
 111   </tr>
 112   <tr>
 113       <td>SCB->CFSR</td>
 114       <td>CFSR</td>
 115       <td>-</td>
 116       <td>Configurable Fault Status Registers</td>
 117   </tr>
 118   <tr>
 119       <td>SCB->HFSR</td>
 120       <td>HFSR</td>
 121       <td>-</td>
 122       <td>HardFault Status Register</td>
 123   </tr>
 124   <tr>
 125       <td>SCB->DFSR</td>
 126       <td>DFSR</td>
 127       <td>-</td>
 128       <td>Debug Fault Status Register</td>
 129   </tr>
 130   <tr>
 131       <td>SCB->MMFAR</td>
 132       <td>MMFAR</td>
 133       <td>-</td>
 134       <td>MemManage Fault Address Register</td>
 135   </tr>
 136   <tr>
 137       <td>SCB->BFAR</td>
 138       <td>BFAR</td>
 139       <td>-</td>
 140       <td>BusFault Address Register</td>
 141   </tr>
 142   <tr>
 143       <td>SCB->AFSR</td>
 144       <td>AFSR</td>
 145       <td>-</td>
 146       <td>Auxiliary Fault Status Register</td>
 147   </tr>
 148   <tr>
 149       <td>SCB->PFR[]</td>
 150       <td>ID_PFR0..1</td>
 151       <td>-</td>
 152       <td>Processor Feature Registers</td>
 153   </tr>
 154   <tr>
 155       <td>SCB->DFR</td>
 156       <td>ID_DFR0</td>
 157       <td>-</td>
 158       <td>Debug Feature Register</td>
 159   </tr>
 160   <tr>
 161       <td>SCB->ADR</td>
 162       <td>ID_AFR0</td>
 163       <td>-</td>
 164       <td>Auxiliary Feature Register</td>
 165   </tr>
 166   <tr>
 167       <td>SCB->MMFR[]</td>
 168       <td>ID_MMFR0..3</td>
 169       <td>-</td>
 170       <td>Memory Model Feature Registers</td>
 171   </tr>
 172   <tr>
 173       <td>SCB->ISAR[]</td>
 174       <td>ID_ISAR0..4</td>
 175       <td>-</td>
 176       <td>Instruction Set Attributes Registers</td>
 177   </tr>
 178   <tr>
 179       <td>SCB->CPACR</td>
 180       <td>CPACR</td>
 181       <td>-</td>
 182       <td>Coprocessor Access Control Register</td>
 183   </tr>
 184   <tr>
 185     <th colspan="4">System Control and ID Registers not in the SCB (SCnSCB) Register Access</th>
 186   </tr>
 187   <tr>
 188       <td>SCnSCB->ICTR</td>
 189       <td>ICTR</td>
 190       <td>-</td>
 191       <td>Interrupt Controller Type Register</td>
 192   </tr>
 193   <tr>
 194       <td>SCnSCB->ACTLR</td>
 195       <td>ACTLR</td>
 196       <td>-</td>
 197       <td>Auxiliary Control Register</td>
 198   </tr>
 199   <tr>
 200     <th colspan="4">System Timer (SysTick) Control and Status Register Access</th>
 201   </tr>
 202   <tr>
 203       <td>SysTick->CTRL</td>
 204       <td>STCSR</td>
 205       <td>SYST_CSR</td>
 206       <td>SysTick Control and Status Register</td>
 207   </tr>
 208   <tr>
 209       <td>SysTick->LOAD</td>
 210       <td>STRVR</td>
 211       <td>SYST_RVR</td>
 212       <td>SysTick Reload Value Register</td>
 213   </tr>
 214   <tr>
 215       <td>SysTick->VAL</td>
 216       <td>STCVR</td>
 217       <td>SYST_CVR</td>
 218       <td>SysTick Current Value Register</td>
 219   </tr>
 220   <tr>
 221       <td>SysTick->CALIB</td>
 222       <td>STCR</td>
 223       <td>SYST_CALIB</td>
 224       <td>SysTick Calibaration Value Register</td>
 225   </tr>
 226   <tr>
 227     <th colspan="4">Data Watchpoint and Trace (DWT) Register Access</th>
 228   </tr>
 229   <tr>
 230       <td>DWT->CTRL</td>
 231       <td>DWT_CTRL</td>
 232       <td>-</td>
 233       <td>Control Register</td>
 234   </tr>
 235   <tr>
 236       <td>DWT->CYCCNT</td>
 237       <td>DWT_CYCCNT</td>
 238       <td>-</td>
 239       <td>Cycle Count Register</td>
 240   </tr>
 241   <tr>
 242       <td>DWT->CPICNT</td>
 243       <td>DWT_CPICNT</td>
 244       <td>-</td>
 245       <td>CPI Count Register</td>
 246   </tr>
 247   <tr>
 248       <td>DWT->EXCCNT</td>
 249       <td>DWT_EXCCNT</td>
 250       <td>-</td>
 251       <td>Exception Overhead Count Register</td>
 252   </tr>
 253   <tr>
 254       <td>DWT->SLEEPCNT</td>
 255       <td>DWT_SLEEPCNT</td>
 256       <td>-</td>
 257       <td>Sleep Count Register</td>
 258   </tr>
 259   <tr>
 260       <td>DWT->LSUCNT</td>
 261       <td>DWT_LSUCNT</td>
 262       <td>-</td>
 263       <td>LSU Count Register</td>
 264   </tr>
 265   <tr>
 266       <td>DWT->FOLDCNT</td>
 267       <td>DWT_FOLDCNT</td>
 268       <td>-</td>
 269       <td>Folded-instruction Count Register</td>
 270   </tr>
 271   <tr>
 272       <td>DWT->PCSR</td>
 273       <td>DWT_PCSR</td>
 274       <td>-</td>
 275       <td>Program Counter Sample Register</td>
 276   </tr>
 277   <tr>
 278       <td>DWT->COMP0..3</td>
 279       <td>DWT_COMP0..3</td>
 280       <td>-</td>
 281       <td>Comparator Register 0..3</td>
 282   </tr>
 283   <tr>
 284       <td>DWT->MASK0..3</td>
 285       <td>DWT_MASK0..3</td>
 286       <td>-</td>
 287       <td>Mask Register 0..3</td>
 288   </tr>
 289   <tr>
 290       <td>DWT->FUNCTION0..3</td>
 291       <td>DWT_FUNCTION0..3</td>
 292       <td>-</td>
 293       <td>Function Register 0..3</td>
 294   </tr>
 295   <tr>
 296     <th colspan="4">Instrumentation Trace Macrocell (ITM) Register Access</th>
 297   </tr>
 298   <tr>
 299       <td>ITM->PORT[]</td>
 300       <td>ITM_STIM0..31</td>
 301       <td>-</td>
 302       <td>Stimulus Port Registers</td>
 303   </tr>
 304   <tr>
 305       <td>ITM->TER</td>
 306       <td>ITM_TER</td>
 307       <td>-</td>
 308       <td>Trace Enable Register</td>
 309   </tr>
 310   <tr>
 311       <td>ITM->TPR</td>
 312       <td>ITM_TPR</td>
 313       <td>-</td>
 314       <td>ITM Trace Privilege Register</td>
 315   </tr>
 316   <tr>
 317       <td>ITM->TCR</td>
 318       <td>ITM_TCR</td>
 319       <td>-</td>
 320       <td>Trace Control Register</td>
 321   </tr>
 322   <tr>
 323     <th colspan="4">Trace Port Interface (TPIU) Register Access</th>
 324   </tr>
 325   <tr>
 326       <td>TPI->SSPSR</td>
 327       <td>TPIU_SSPR</td>
 328       <td>-</td>
 329       <td>Supported Parallel Port Size Register</td>
 330   </tr>
 331   <tr>
 332       <td>TPI->CSPSR</td>
 333       <td>TPIU_CSPSR</td>
 334       <td>-</td>
 335       <td>Current Parallel Port Size Register</td>
 336   </tr>
 337   <tr>
 338       <td>TPI->ACPR</td>
 339       <td>TPIU_ACPR</td>
 340       <td>-</td>
 341       <td>Asynchronous Clock Prescaler Register</td>
 342   </tr>
 343   <tr>
 344       <td>TPI->SPPR</td>
 345       <td>TPIU_SPPR</td>
 346       <td>-</td>
 347       <td>Selected Pin Protocol Register</td>
 348   </tr>
 349   <tr>
 350       <td>TPI->FFSR</td>
 351       <td>TPIU_FFSR</td>
 352       <td>-</td>
 353       <td>Formatter and Flush Status Register</td>
 354   </tr>
 355   <tr>
 356       <td>TPI->FFCR</td>
 357       <td>TPIU_FFCR</td>
 358       <td>-</td>
 359       <td>Formatter and Flush Control Register</td>
 360   </tr>
 361   <tr>
 362       <td>TPI->FSCR</td>
 363       <td>TPIU_FSCR</td>
 364       <td>-</td>
 365       <td>Formatter Synchronization Counter Register</td>
 366   </tr>
 367   <tr>
 368       <td>TPI->TRIGGER</td>
 369       <td>TRIGGER</td>
 370       <td>-</td>
 371       <td>TRIGGER</td>
 372   </tr>
 373   <tr>
 374       <td>TPI->FIFO0</td>
 375       <td>FIFO data 0</td>
 376       <td>-</td>
 377       <td>Integration ETM Data</td>
 378   </tr>
 379   <tr>
 380       <td>TPI->ITATBCTR2</td>
 381       <td>ITATBCTR2</td>
 382       <td>-</td>
 383       <td>ITATBCTR2</td>
 384   </tr>
 385   <tr>
 386       <td>TPI->ITATBCTR0</td>
 387       <td>ITATBCTR0</td>
 388       <td>-</td>
 389       <td>ITATBCTR0</td>
 390   </tr>
 391   <tr>
 392       <td>TPI->FIFO1</td>
 393       <td>FIFO data 1</td>
 394       <td>-</td>
 395       <td>Integration ITM Data</td>
 396   </tr>
 397   <tr>
 398       <td>TPI->ITCTRL</td>
 399       <td>TPIU_ITCTRL</td>
 400       <td>-</td>
 401       <td>Integration Mode Control</td>
 402   </tr>
 403   <tr>
 404       <td>TPI->CLAIMSET</td>
 405       <td>CLAIMSET</td>
 406       <td>-</td>
 407       <td>Claim tag set</td>
 408   </tr>
 409   <tr>
 410       <td>TPI->CLAIMCLR</td>
 411       <td>CLAIMCLR</td>
 412       <td>-</td>
 413       <td>Claim tag clear</td>
 414   </tr>
 415   <tr>
 416       <td>TPI->DEVID</td>
 417       <td>TPIU_DEVID</td>
 418       <td>-</td>
 419       <td>TPIU_DEVID</td>
 420   </tr>
 421   <tr>
 422       <td>TPI->DEVTYPE</td>
 423       <td>TPIU_DEVTYPE</td>
 424       <td>-</td>
 425       <td>TPIU_DEVTYPE</td>
 426   </tr>
 427   <tr>
 428     <th colspan="4">Memory Protection Unit (MPU) Register Access</th>
 429   </tr>
 430   <tr>
 431       <td>MPU->TYPE</td>
 432       <td>MPU_TYPE</td>
 433       <td>-</td>
 434       <td>MPU Type Register</td>
 435   </tr>
 436   <tr>
 437       <td>MPU->CTRL</td>
 438       <td>MPU_CTRL</td>
 439       <td>-</td>
 440       <td>MPU Control Register</td>
 441   </tr>
 442   <tr>
 443       <td>MPU->RNR</td>
 444       <td>MPU_RNR</td>
 445       <td>-</td>
 446       <td>MPU Region Number Register</td>
 447   </tr>
 448   <tr>
 449       <td>MPU->RBAR</td>
 450       <td>MPU_RBAR</td>
 451       <td>-</td>
 452       <td>MPU Region Base Address Register</td>
 453   </tr>
 454   <tr>
 455       <td>MPU->RASR</td>
 456       <td>MPU_RASR</td>
 457       <td>-</td>
 458       <td>MPU Region Attribute and Size Register</td>
 459   </tr>
 460   <tr>
 461       <td>MPU->RBAR_A1..3</td>
 462       <td>MPU_RBAR_A1..3</td>
 463       <td>-</td>
 464       <td>MPU alias Register</td>
 465   </tr>
 466   <tr>
 467       <td>MPU->RASR_A1..3</td>
 468       <td>MPU_RASR_A1..3</td>
 469       <td>-</td>
 470       <td>MPU alias Register</td>
 471   </tr>
 472   <tr>
 473     <th colspan="4">Floating Point Unit (FPU) Register Access [only Cortex-M4 and Cortex-M7 both with FPU]</th>
 474   </tr>
 475   <tr>
 476       <td>FPU->FPCCR</td>
 477       <td>FPCCR</td>
 478       <td>-</td>
 479       <td>FP Context Control Register</td>
 480   </tr>
 481   <tr>
 482       <td>FPU->FPCAR</td>
 483       <td>FPCAR</td>
 484       <td>-</td>
 485       <td>FP Context Address Register</td>
 486   </tr>
 487   <tr>
 488       <td>FPU->FPDSCR</td>
 489       <td>FPDSCR</td>
 490       <td>-</td>
 491       <td>FP Default Status Control Register</td>
 492   </tr>
 493   <tr>
 494       <td>FPU->MVFR0..1</td>
 495       <td>MVFR0..1</td>
 496       <td>-</td>
 497       <td>Media and VFP Feature Registers</td>
 498   </tr>
 499 </table>
 500 */