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52 <div id="projectbrief">CMSIS-Core support for Cortex-A processor-based devices</div>
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132 <div class="headertitle"><div class="title">core_ca.h File Reference</div></div>
134 <div class="contents">
135 <table class="memberdecls">
136 <tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="nested-classes" name="nested-classes"></a>
137 Data Structures</h2></td></tr>
138 <tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="unionCPSR__Type.html">CPSR_Type</a></td></tr>
139 <tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">Bit field declaration for CPSR layout. <a href="unionCPSR__Type.html#details">More...</a><br /></td></tr>
140 <tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
141 <tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="unionSCTLR__Type.html">SCTLR_Type</a></td></tr>
142 <tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">Bit field declaration for SCTLR layout. <a href="unionSCTLR__Type.html#details">More...</a><br /></td></tr>
143 <tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
144 <tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="unionACTLR__Type.html">ACTLR_Type</a></td></tr>
145 <tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">Bit field declaration for ACTLR layout. <a href="unionACTLR__Type.html#details">More...</a><br /></td></tr>
146 <tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
147 <tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="unionCPACR__Type.html">CPACR_Type</a></td></tr>
148 <tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">Bit field declaration for CPACR layout. <a href="unionCPACR__Type.html#details">More...</a><br /></td></tr>
149 <tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
150 <tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="unionDFSR__Type.html">DFSR_Type</a></td></tr>
151 <tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">Bit field declaration for DFSR layout. <a href="unionDFSR__Type.html#details">More...</a><br /></td></tr>
152 <tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
153 <tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="unionIFSR__Type.html">IFSR_Type</a></td></tr>
154 <tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">Bit field declaration for IFSR layout. <a href="unionIFSR__Type.html#details">More...</a><br /></td></tr>
155 <tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
156 <tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="unionISR__Type.html">ISR_Type</a></td></tr>
157 <tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">Bit field declaration for ISR layout. <a href="unionISR__Type.html#details">More...</a><br /></td></tr>
158 <tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
159 <tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="structL2C__310__TypeDef.html">L2C_310_TypeDef</a></td></tr>
160 <tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">Union type to access the L2C_310 Cache Controller. <a href="structL2C__310__TypeDef.html#details">More...</a><br /></td></tr>
161 <tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
162 <tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="structGICDistributor__Type.html">GICDistributor_Type</a></td></tr>
163 <tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">Structure type to access the Generic Interrupt Controller Distributor (GICD) <a href="structGICDistributor__Type.html#details">More...</a><br /></td></tr>
164 <tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
165 <tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="structGICInterface__Type.html">GICInterface_Type</a></td></tr>
166 <tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">Structure type to access the Generic Interrupt Controller Interface (GICC) <a href="structGICInterface__Type.html#details">More...</a><br /></td></tr>
167 <tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
168 <tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="structTimer__Type.html">Timer_Type</a></td></tr>
169 <tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">Structure type to access the Private Timer. <a href="structTimer__Type.html#details">More...</a><br /></td></tr>
170 <tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
171 <tr class="memitem:"><td class="memItemLeft" align="right" valign="top">union  </td><td class="memItemRight" valign="bottom"><a class="el" href="unionCNTP__CTL__Type.html">CNTP_CTL_Type</a></td></tr>
172 <tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">Physical Timer Control register. <a href="unionCNTP__CTL__Type.html#details">More...</a><br /></td></tr>
173 <tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
174 <tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="structmmu__region__attributes__Type.html">mmu_region_attributes_Type</a></td></tr>
175 <tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
176 </table><table class="memberdecls">
177 <tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="define-members" name="define-members"></a>
178 Macros</h2></td></tr>
179 <tr class="memitem:aa167d0f532a7c2b2e3a6395db2fa0776"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#aa167d0f532a7c2b2e3a6395db2fa0776">__FPU_USED</a>   0U</td></tr>
180 <tr class="separator:aa167d0f532a7c2b2e3a6395db2fa0776"><td class="memSeparator" colspan="2"> </td></tr>
181 <tr class="memitem:add5658d95f6b79934202e6fbf1795b12"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#add5658d95f6b79934202e6fbf1795b12">__CORE_CA_H_DEPENDANT</a></td></tr>
182 <tr class="separator:add5658d95f6b79934202e6fbf1795b12"><td class="memSeparator" colspan="2"> </td></tr>
183 <tr class="memitem:ac1ba8a48ca926bddc88be9bfd7d42641"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#ac1ba8a48ca926bddc88be9bfd7d42641">__FPU_PRESENT</a>   0U</td></tr>
184 <tr class="separator:ac1ba8a48ca926bddc88be9bfd7d42641"><td class="memSeparator" colspan="2"> </td></tr>
185 <tr class="memitem:a6690a7e24ea0ec4b36a8fb077d01a820"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a6690a7e24ea0ec4b36a8fb077d01a820">__GIC_PRESENT</a>   1U</td></tr>
186 <tr class="separator:a6690a7e24ea0ec4b36a8fb077d01a820"><td class="memSeparator" colspan="2"> </td></tr>
187 <tr class="memitem:a0e57ca9f1bc10c2de05d383d2c76267a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a0e57ca9f1bc10c2de05d383d2c76267a">__TIM_PRESENT</a>   1U</td></tr>
188 <tr class="separator:a0e57ca9f1bc10c2de05d383d2c76267a"><td class="memSeparator" colspan="2"> </td></tr>
189 <tr class="memitem:af63697ed9952cc71e1225efe205f6cd3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#af63697ed9952cc71e1225efe205f6cd3">__I</a>   volatile</td></tr>
190 <tr class="memdesc:af63697ed9952cc71e1225efe205f6cd3"><td class="mdescLeft"> </td><td class="mdescRight">Defines 'read only' permissions. <br /></td></tr>
191 <tr class="separator:af63697ed9952cc71e1225efe205f6cd3"><td class="memSeparator" colspan="2"> </td></tr>
192 <tr class="memitem:a7e25d9380f9ef903923964322e71f2f6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a7e25d9380f9ef903923964322e71f2f6">__O</a>   volatile</td></tr>
193 <tr class="memdesc:a7e25d9380f9ef903923964322e71f2f6"><td class="mdescLeft"> </td><td class="mdescRight">Defines 'write only' permissions. <br /></td></tr>
194 <tr class="separator:a7e25d9380f9ef903923964322e71f2f6"><td class="memSeparator" colspan="2"> </td></tr>
195 <tr class="memitem:aec43007d9998a0a0e01faede4133d6be"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a>   volatile</td></tr>
196 <tr class="memdesc:aec43007d9998a0a0e01faede4133d6be"><td class="mdescLeft"> </td><td class="mdescRight">Defines 'read / write' permissions. <br /></td></tr>
197 <tr class="separator:aec43007d9998a0a0e01faede4133d6be"><td class="memSeparator" colspan="2"> </td></tr>
198 <tr class="memitem:a4cc1649793116d7c2d8afce7a4ffce43"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a4cc1649793116d7c2d8afce7a4ffce43">__IM</a>   volatile const</td></tr>
199 <tr class="memdesc:a4cc1649793116d7c2d8afce7a4ffce43"><td class="mdescLeft"> </td><td class="mdescRight">Defines 'read only' structure member permissions. <br /></td></tr>
200 <tr class="separator:a4cc1649793116d7c2d8afce7a4ffce43"><td class="memSeparator" colspan="2"> </td></tr>
201 <tr class="memitem:a0ea2009ed8fd9ef35b48708280fdb758"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a0ea2009ed8fd9ef35b48708280fdb758">__OM</a>   volatile</td></tr>
202 <tr class="memdesc:a0ea2009ed8fd9ef35b48708280fdb758"><td class="mdescLeft"> </td><td class="mdescRight">Defines 'write only' structure member permissions. <br /></td></tr>
203 <tr class="separator:a0ea2009ed8fd9ef35b48708280fdb758"><td class="memSeparator" colspan="2"> </td></tr>
204 <tr class="memitem:ab6caba5853a60a17e8e04499b52bf691"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a>   volatile</td></tr>
205 <tr class="memdesc:ab6caba5853a60a17e8e04499b52bf691"><td class="mdescLeft"> </td><td class="mdescRight">Defines 'read / write' structure member permissions. <br /></td></tr>
206 <tr class="separator:ab6caba5853a60a17e8e04499b52bf691"><td class="memSeparator" colspan="2"> </td></tr>
207 <tr class="memitem:af7f66fda711fd46e157dbb6c1af88e04"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#af7f66fda711fd46e157dbb6c1af88e04">RESERVED</a>(N, T)   T RESERVED##N;</td></tr>
208 <tr class="separator:af7f66fda711fd46e157dbb6c1af88e04"><td class="memSeparator" colspan="2"> </td></tr>
209 <tr class="memitem:gaaedc00ebe496885524daac4190742f84"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__BITS.html#gaaedc00ebe496885524daac4190742f84">CPSR_N_Pos</a>   31U</td></tr>
210 <tr class="memdesc:gaaedc00ebe496885524daac4190742f84"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: N Position. <br /></td></tr>
211 <tr class="separator:gaaedc00ebe496885524daac4190742f84"><td class="memSeparator" colspan="2"> </td></tr>
212 <tr class="memitem:ga6c4a636a3b5ec71e0f2eb021ac353544"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__BITS.html#ga6c4a636a3b5ec71e0f2eb021ac353544">CPSR_N_Msk</a>   (1UL << <a class="el" href="group__CMSIS__CPSR__BITS.html#gaaedc00ebe496885524daac4190742f84">CPSR_N_Pos</a>)</td></tr>
213 <tr class="memdesc:ga6c4a636a3b5ec71e0f2eb021ac353544"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: N Mask. <br /></td></tr>
214 <tr class="separator:ga6c4a636a3b5ec71e0f2eb021ac353544"><td class="memSeparator" colspan="2"> </td></tr>
215 <tr class="memitem:ga18e9f21fcda9d385d23a4de0ef860cd4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__BITS.html#ga18e9f21fcda9d385d23a4de0ef860cd4">CPSR_Z_Pos</a>   30U</td></tr>
216 <tr class="memdesc:ga18e9f21fcda9d385d23a4de0ef860cd4"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: Z Position. <br /></td></tr>
217 <tr class="separator:ga18e9f21fcda9d385d23a4de0ef860cd4"><td class="memSeparator" colspan="2"> </td></tr>
218 <tr class="memitem:gab091112988009fb8360b01c79d993f67"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__BITS.html#gab091112988009fb8360b01c79d993f67">CPSR_Z_Msk</a>   (1UL << <a class="el" href="group__CMSIS__CPSR__BITS.html#ga18e9f21fcda9d385d23a4de0ef860cd4">CPSR_Z_Pos</a>)</td></tr>
219 <tr class="memdesc:gab091112988009fb8360b01c79d993f67"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: Z Mask. <br /></td></tr>
220 <tr class="separator:gab091112988009fb8360b01c79d993f67"><td class="memSeparator" colspan="2"> </td></tr>
221 <tr class="memitem:ga8565df3cf054dc09506e1c0ea4790131"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__BITS.html#ga8565df3cf054dc09506e1c0ea4790131">CPSR_C_Pos</a>   29U</td></tr>
222 <tr class="memdesc:ga8565df3cf054dc09506e1c0ea4790131"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: C Position. <br /></td></tr>
223 <tr class="separator:ga8565df3cf054dc09506e1c0ea4790131"><td class="memSeparator" colspan="2"> </td></tr>
224 <tr class="memitem:ga3bc30b14b9b0bf113600eb882304244c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__BITS.html#ga3bc30b14b9b0bf113600eb882304244c">CPSR_C_Msk</a>   (1UL << <a class="el" href="group__CMSIS__CPSR__BITS.html#ga8565df3cf054dc09506e1c0ea4790131">CPSR_C_Pos</a>)</td></tr>
225 <tr class="memdesc:ga3bc30b14b9b0bf113600eb882304244c"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: C Mask. <br /></td></tr>
226 <tr class="separator:ga3bc30b14b9b0bf113600eb882304244c"><td class="memSeparator" colspan="2"> </td></tr>
227 <tr class="memitem:ga5685fa5745113b4ff61181ee439bc2a5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__BITS.html#ga5685fa5745113b4ff61181ee439bc2a5">CPSR_V_Pos</a>   28U</td></tr>
228 <tr class="memdesc:ga5685fa5745113b4ff61181ee439bc2a5"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: V Position. <br /></td></tr>
229 <tr class="separator:ga5685fa5745113b4ff61181ee439bc2a5"><td class="memSeparator" colspan="2"> </td></tr>
230 <tr class="memitem:ga9b9fe5c1da5e922cbff18215b70b4252"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__BITS.html#ga9b9fe5c1da5e922cbff18215b70b4252">CPSR_V_Msk</a>   (1UL << <a class="el" href="group__CMSIS__CPSR__BITS.html#ga5685fa5745113b4ff61181ee439bc2a5">CPSR_V_Pos</a>)</td></tr>
231 <tr class="memdesc:ga9b9fe5c1da5e922cbff18215b70b4252"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: V Mask. <br /></td></tr>
232 <tr class="separator:ga9b9fe5c1da5e922cbff18215b70b4252"><td class="memSeparator" colspan="2"> </td></tr>
233 <tr class="memitem:ga84c8427c30fdce15f7191bd4f93d7ab7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__BITS.html#ga84c8427c30fdce15f7191bd4f93d7ab7">CPSR_Q_Pos</a>   27U</td></tr>
234 <tr class="memdesc:ga84c8427c30fdce15f7191bd4f93d7ab7"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: Q Position. <br /></td></tr>
235 <tr class="separator:ga84c8427c30fdce15f7191bd4f93d7ab7"><td class="memSeparator" colspan="2"> </td></tr>
236 <tr class="memitem:gaba36b1ac0438594afdc6eef220d2e146"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__BITS.html#gaba36b1ac0438594afdc6eef220d2e146">CPSR_Q_Msk</a>   (1UL << <a class="el" href="group__CMSIS__CPSR__BITS.html#ga84c8427c30fdce15f7191bd4f93d7ab7">CPSR_Q_Pos</a>)</td></tr>
237 <tr class="memdesc:gaba36b1ac0438594afdc6eef220d2e146"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: Q Mask. <br /></td></tr>
238 <tr class="separator:gaba36b1ac0438594afdc6eef220d2e146"><td class="memSeparator" colspan="2"> </td></tr>
239 <tr class="memitem:ga450f3fff0642431fd3478a04b70c3d87"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__BITS.html#ga450f3fff0642431fd3478a04b70c3d87">CPSR_IT0_Pos</a>   25U</td></tr>
240 <tr class="memdesc:ga450f3fff0642431fd3478a04b70c3d87"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: IT0 Position. <br /></td></tr>
241 <tr class="separator:ga450f3fff0642431fd3478a04b70c3d87"><td class="memSeparator" colspan="2"> </td></tr>
242 <tr class="memitem:ga128366788d0f94d52fbe4610162c97e5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__BITS.html#ga128366788d0f94d52fbe4610162c97e5">CPSR_IT0_Msk</a>   (3UL << <a class="el" href="group__CMSIS__CPSR__BITS.html#ga450f3fff0642431fd3478a04b70c3d87">CPSR_IT0_Pos</a>)</td></tr>
243 <tr class="memdesc:ga128366788d0f94d52fbe4610162c97e5"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: IT0 Mask. <br /></td></tr>
244 <tr class="separator:ga128366788d0f94d52fbe4610162c97e5"><td class="memSeparator" colspan="2"> </td></tr>
245 <tr class="memitem:ga6b49ddfb770143a51aa682b56be2e990"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__BITS.html#ga6b49ddfb770143a51aa682b56be2e990">CPSR_J_Pos</a>   24U</td></tr>
246 <tr class="memdesc:ga6b49ddfb770143a51aa682b56be2e990"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: J Position. <br /></td></tr>
247 <tr class="separator:ga6b49ddfb770143a51aa682b56be2e990"><td class="memSeparator" colspan="2"> </td></tr>
248 <tr class="memitem:ga6b52a05ec2e95ade71b65090f19285c2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__BITS.html#ga6b52a05ec2e95ade71b65090f19285c2">CPSR_J_Msk</a>   (1UL << <a class="el" href="group__CMSIS__CPSR__BITS.html#ga6b49ddfb770143a51aa682b56be2e990">CPSR_J_Pos</a>)</td></tr>
249 <tr class="memdesc:ga6b52a05ec2e95ade71b65090f19285c2"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: J Mask. <br /></td></tr>
250 <tr class="separator:ga6b52a05ec2e95ade71b65090f19285c2"><td class="memSeparator" colspan="2"> </td></tr>
251 <tr class="memitem:ga37aa76465f6c6055395790e74169d760"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__BITS.html#ga37aa76465f6c6055395790e74169d760">CPSR_GE_Pos</a>   16U</td></tr>
252 <tr class="memdesc:ga37aa76465f6c6055395790e74169d760"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: GE Position. <br /></td></tr>
253 <tr class="separator:ga37aa76465f6c6055395790e74169d760"><td class="memSeparator" colspan="2"> </td></tr>
254 <tr class="memitem:ga9a3a6a87437892954cb37662ff27521a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__BITS.html#ga9a3a6a87437892954cb37662ff27521a">CPSR_GE_Msk</a>   (0xFUL << <a class="el" href="group__CMSIS__CPSR__BITS.html#ga37aa76465f6c6055395790e74169d760">CPSR_GE_Pos</a>)</td></tr>
255 <tr class="memdesc:ga9a3a6a87437892954cb37662ff27521a"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: GE Mask. <br /></td></tr>
256 <tr class="separator:ga9a3a6a87437892954cb37662ff27521a"><td class="memSeparator" colspan="2"> </td></tr>
257 <tr class="memitem:gaa2ab21d87052b439c06f058fb65036a5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__BITS.html#gaa2ab21d87052b439c06f058fb65036a5">CPSR_IT1_Pos</a>   10U</td></tr>
258 <tr class="memdesc:gaa2ab21d87052b439c06f058fb65036a5"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: IT1 Position. <br /></td></tr>
259 <tr class="separator:gaa2ab21d87052b439c06f058fb65036a5"><td class="memSeparator" colspan="2"> </td></tr>
260 <tr class="memitem:ga791263c8a9707795b5824dae5485cd39"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__BITS.html#ga791263c8a9707795b5824dae5485cd39">CPSR_IT1_Msk</a>   (0x3FUL << <a class="el" href="group__CMSIS__CPSR__BITS.html#gaa2ab21d87052b439c06f058fb65036a5">CPSR_IT1_Pos</a>)</td></tr>
261 <tr class="memdesc:ga791263c8a9707795b5824dae5485cd39"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: IT1 Mask. <br /></td></tr>
262 <tr class="separator:ga791263c8a9707795b5824dae5485cd39"><td class="memSeparator" colspan="2"> </td></tr>
263 <tr class="memitem:ga6a5e065d9ea93489105c3d62c1d3c08f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__BITS.html#ga6a5e065d9ea93489105c3d62c1d3c08f">CPSR_E_Pos</a>   9U</td></tr>
264 <tr class="memdesc:ga6a5e065d9ea93489105c3d62c1d3c08f"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: E Position. <br /></td></tr>
265 <tr class="separator:ga6a5e065d9ea93489105c3d62c1d3c08f"><td class="memSeparator" colspan="2"> </td></tr>
266 <tr class="memitem:ga6661712dd33a50ce4a42e13bf72aa35b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__BITS.html#ga6661712dd33a50ce4a42e13bf72aa35b">CPSR_E_Msk</a>   (1UL << <a class="el" href="group__CMSIS__CPSR__BITS.html#ga6a5e065d9ea93489105c3d62c1d3c08f">CPSR_E_Pos</a>)</td></tr>
267 <tr class="memdesc:ga6661712dd33a50ce4a42e13bf72aa35b"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: E Mask. <br /></td></tr>
268 <tr class="separator:ga6661712dd33a50ce4a42e13bf72aa35b"><td class="memSeparator" colspan="2"> </td></tr>
269 <tr class="memitem:ga6f8aa35ca07825d6b4498ae6e2ab616b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__BITS.html#ga6f8aa35ca07825d6b4498ae6e2ab616b">CPSR_A_Pos</a>   8U</td></tr>
270 <tr class="memdesc:ga6f8aa35ca07825d6b4498ae6e2ab616b"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: A Position. <br /></td></tr>
271 <tr class="separator:ga6f8aa35ca07825d6b4498ae6e2ab616b"><td class="memSeparator" colspan="2"> </td></tr>
272 <tr class="memitem:ga002803fa282333e0ead5c9b4cf748cb1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__BITS.html#ga002803fa282333e0ead5c9b4cf748cb1">CPSR_A_Msk</a>   (1UL << <a class="el" href="group__CMSIS__CPSR__BITS.html#ga6f8aa35ca07825d6b4498ae6e2ab616b">CPSR_A_Pos</a>)</td></tr>
273 <tr class="memdesc:ga002803fa282333e0ead5c9b4cf748cb1"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: A Mask. <br /></td></tr>
274 <tr class="separator:ga002803fa282333e0ead5c9b4cf748cb1"><td class="memSeparator" colspan="2"> </td></tr>
275 <tr class="memitem:gad1d9be2f731f5400fc87076ce3495e59"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__BITS.html#gad1d9be2f731f5400fc87076ce3495e59">CPSR_I_Pos</a>   7U</td></tr>
276 <tr class="memdesc:gad1d9be2f731f5400fc87076ce3495e59"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: I Position. <br /></td></tr>
277 <tr class="separator:gad1d9be2f731f5400fc87076ce3495e59"><td class="memSeparator" colspan="2"> </td></tr>
278 <tr class="memitem:gad9abe93ba1179e254a70e325cb1a5834"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__BITS.html#gad9abe93ba1179e254a70e325cb1a5834">CPSR_I_Msk</a>   (1UL << <a class="el" href="group__CMSIS__CPSR__BITS.html#gad1d9be2f731f5400fc87076ce3495e59">CPSR_I_Pos</a>)</td></tr>
279 <tr class="memdesc:gad9abe93ba1179e254a70e325cb1a5834"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: I Mask. <br /></td></tr>
280 <tr class="separator:gad9abe93ba1179e254a70e325cb1a5834"><td class="memSeparator" colspan="2"> </td></tr>
281 <tr class="memitem:ga5e9868fdea8e65374b25ddd2fde1bf62"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__BITS.html#ga5e9868fdea8e65374b25ddd2fde1bf62">CPSR_F_Pos</a>   6U</td></tr>
282 <tr class="memdesc:ga5e9868fdea8e65374b25ddd2fde1bf62"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: F Position. <br /></td></tr>
283 <tr class="separator:ga5e9868fdea8e65374b25ddd2fde1bf62"><td class="memSeparator" colspan="2"> </td></tr>
284 <tr class="memitem:ga4df09481ffd9dfb17823a8e9895b1566"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__BITS.html#ga4df09481ffd9dfb17823a8e9895b1566">CPSR_F_Msk</a>   (1UL << <a class="el" href="group__CMSIS__CPSR__BITS.html#ga5e9868fdea8e65374b25ddd2fde1bf62">CPSR_F_Pos</a>)</td></tr>
285 <tr class="memdesc:ga4df09481ffd9dfb17823a8e9895b1566"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: F Mask. <br /></td></tr>
286 <tr class="separator:ga4df09481ffd9dfb17823a8e9895b1566"><td class="memSeparator" colspan="2"> </td></tr>
287 <tr class="memitem:gaa1134ff3e774b1354a43227b798a707c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__BITS.html#gaa1134ff3e774b1354a43227b798a707c">CPSR_T_Pos</a>   5U</td></tr>
288 <tr class="memdesc:gaa1134ff3e774b1354a43227b798a707c"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: T Position. <br /></td></tr>
289 <tr class="separator:gaa1134ff3e774b1354a43227b798a707c"><td class="memSeparator" colspan="2"> </td></tr>
290 <tr class="memitem:ga23ed422711cbd2f9a5dcbe6c05b2a720"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__BITS.html#ga23ed422711cbd2f9a5dcbe6c05b2a720">CPSR_T_Msk</a>   (1UL << <a class="el" href="group__CMSIS__CPSR__BITS.html#gaa1134ff3e774b1354a43227b798a707c">CPSR_T_Pos</a>)</td></tr>
291 <tr class="memdesc:ga23ed422711cbd2f9a5dcbe6c05b2a720"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: T Mask. <br /></td></tr>
292 <tr class="separator:ga23ed422711cbd2f9a5dcbe6c05b2a720"><td class="memSeparator" colspan="2"> </td></tr>
293 <tr class="memitem:ga4e9e49c9a75cf3e7d696fc77de7d44d1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__BITS.html#ga4e9e49c9a75cf3e7d696fc77de7d44d1">CPSR_M_Pos</a>   0U</td></tr>
294 <tr class="memdesc:ga4e9e49c9a75cf3e7d696fc77de7d44d1"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: M Position. <br /></td></tr>
295 <tr class="separator:ga4e9e49c9a75cf3e7d696fc77de7d44d1"><td class="memSeparator" colspan="2"> </td></tr>
296 <tr class="memitem:gadce47959b814f70f802a139250daa04c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__BITS.html#gadce47959b814f70f802a139250daa04c">CPSR_M_Msk</a>   (0x1FUL << <a class="el" href="group__CMSIS__CPSR__BITS.html#ga4e9e49c9a75cf3e7d696fc77de7d44d1">CPSR_M_Pos</a>)</td></tr>
297 <tr class="memdesc:gadce47959b814f70f802a139250daa04c"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: M Mask. <br /></td></tr>
298 <tr class="separator:gadce47959b814f70f802a139250daa04c"><td class="memSeparator" colspan="2"> </td></tr>
299 <tr class="memitem:gad716a0ee4dc815f0f01e1339d6511a4e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__M.html#gad716a0ee4dc815f0f01e1339d6511a4e">CPSR_M_USR</a>   0x10U</td></tr>
300 <tr class="memdesc:gad716a0ee4dc815f0f01e1339d6511a4e"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: M User mode (PL0) <br /></td></tr>
301 <tr class="separator:gad716a0ee4dc815f0f01e1339d6511a4e"><td class="memSeparator" colspan="2"> </td></tr>
302 <tr class="memitem:ga868ef12e003f541f90a613ca7f6ada74"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__M.html#ga868ef12e003f541f90a613ca7f6ada74">CPSR_M_FIQ</a>   0x11U</td></tr>
303 <tr class="memdesc:ga868ef12e003f541f90a613ca7f6ada74"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: M Fast Interrupt mode (PL1) <br /></td></tr>
304 <tr class="separator:ga868ef12e003f541f90a613ca7f6ada74"><td class="memSeparator" colspan="2"> </td></tr>
305 <tr class="memitem:gada3f31a773f7fc7bf6567d598cf3a1db"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__M.html#gada3f31a773f7fc7bf6567d598cf3a1db">CPSR_M_IRQ</a>   0x12U</td></tr>
306 <tr class="memdesc:gada3f31a773f7fc7bf6567d598cf3a1db"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: M Interrupt mode (PL1) <br /></td></tr>
307 <tr class="separator:gada3f31a773f7fc7bf6567d598cf3a1db"><td class="memSeparator" colspan="2"> </td></tr>
308 <tr class="memitem:ga5afcb85bd2968acc2b09cb9d99c531ad"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__M.html#ga5afcb85bd2968acc2b09cb9d99c531ad">CPSR_M_SVC</a>   0x13U</td></tr>
309 <tr class="memdesc:ga5afcb85bd2968acc2b09cb9d99c531ad"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: M Supervisor mode (PL1) <br /></td></tr>
310 <tr class="separator:ga5afcb85bd2968acc2b09cb9d99c531ad"><td class="memSeparator" colspan="2"> </td></tr>
311 <tr class="memitem:ga69d734db93f67899b4bffcf62f80f098"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__M.html#ga69d734db93f67899b4bffcf62f80f098">CPSR_M_MON</a>   0x16U</td></tr>
312 <tr class="memdesc:ga69d734db93f67899b4bffcf62f80f098"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: M Monitor mode (PL1) <br /></td></tr>
313 <tr class="separator:ga69d734db93f67899b4bffcf62f80f098"><td class="memSeparator" colspan="2"> </td></tr>
314 <tr class="memitem:gac8c0a99a21ef256f5d3115595a845bfa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__M.html#gac8c0a99a21ef256f5d3115595a845bfa">CPSR_M_ABT</a>   0x17U</td></tr>
315 <tr class="memdesc:gac8c0a99a21ef256f5d3115595a845bfa"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: M Abort mode (PL1) <br /></td></tr>
316 <tr class="separator:gac8c0a99a21ef256f5d3115595a845bfa"><td class="memSeparator" colspan="2"> </td></tr>
317 <tr class="memitem:ga002c78f542ca5c5fdd02d2aeee9f6988"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__M.html#ga002c78f542ca5c5fdd02d2aeee9f6988">CPSR_M_HYP</a>   0x1AU</td></tr>
318 <tr class="memdesc:ga002c78f542ca5c5fdd02d2aeee9f6988"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: M Hypervisor mode (PL2) <br /></td></tr>
319 <tr class="separator:ga002c78f542ca5c5fdd02d2aeee9f6988"><td class="memSeparator" colspan="2"> </td></tr>
320 <tr class="memitem:ga07d4f42d6971c2f0cc25872008ddf5ef"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__M.html#ga07d4f42d6971c2f0cc25872008ddf5ef">CPSR_M_UND</a>   0x1BU</td></tr>
321 <tr class="memdesc:ga07d4f42d6971c2f0cc25872008ddf5ef"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: M Undefined mode (PL1) <br /></td></tr>
322 <tr class="separator:ga07d4f42d6971c2f0cc25872008ddf5ef"><td class="memSeparator" colspan="2"> </td></tr>
323 <tr class="memitem:gaa0a3996ce096cd205bce34f90b10912c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR__M.html#gaa0a3996ce096cd205bce34f90b10912c">CPSR_M_SYS</a>   0x1FU</td></tr>
324 <tr class="memdesc:gaa0a3996ce096cd205bce34f90b10912c"><td class="mdescLeft"> </td><td class="mdescRight">CPSR: M System mode (PL1) <br /></td></tr>
325 <tr class="separator:gaa0a3996ce096cd205bce34f90b10912c"><td class="memSeparator" colspan="2"> </td></tr>
326 <tr class="memitem:gab0a611e2359e04624379e1ddd4dc64b1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#gab0a611e2359e04624379e1ddd4dc64b1">SCTLR_TE_Pos</a>   30U</td></tr>
327 <tr class="memdesc:gab0a611e2359e04624379e1ddd4dc64b1"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: TE Position. <br /></td></tr>
328 <tr class="separator:gab0a611e2359e04624379e1ddd4dc64b1"><td class="memSeparator" colspan="2"> </td></tr>
329 <tr class="memitem:ga4a68d6660c76951ada2541ceaf040b3b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#ga4a68d6660c76951ada2541ceaf040b3b">SCTLR_TE_Msk</a>   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#gab0a611e2359e04624379e1ddd4dc64b1">SCTLR_TE_Pos</a>)</td></tr>
330 <tr class="memdesc:ga4a68d6660c76951ada2541ceaf040b3b"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: TE Mask. <br /></td></tr>
331 <tr class="separator:ga4a68d6660c76951ada2541ceaf040b3b"><td class="memSeparator" colspan="2"> </td></tr>
332 <tr class="memitem:ga4ac80ef4db2641dc9e6e8df0825a151e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#ga4ac80ef4db2641dc9e6e8df0825a151e">SCTLR_AFE_Pos</a>   29U</td></tr>
333 <tr class="memdesc:ga4ac80ef4db2641dc9e6e8df0825a151e"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: AFE Position. <br /></td></tr>
334 <tr class="separator:ga4ac80ef4db2641dc9e6e8df0825a151e"><td class="memSeparator" colspan="2"> </td></tr>
335 <tr class="memitem:ga9016d6e50562d2584c1f1a95bde1e957"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#ga9016d6e50562d2584c1f1a95bde1e957">SCTLR_AFE_Msk</a>   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#ga4ac80ef4db2641dc9e6e8df0825a151e">SCTLR_AFE_Pos</a>)</td></tr>
336 <tr class="memdesc:ga9016d6e50562d2584c1f1a95bde1e957"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: AFE Mask. <br /></td></tr>
337 <tr class="separator:ga9016d6e50562d2584c1f1a95bde1e957"><td class="memSeparator" colspan="2"> </td></tr>
338 <tr class="memitem:gaf76fa48119363f9b88c2c8f5b74e0a04"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#gaf76fa48119363f9b88c2c8f5b74e0a04">SCTLR_TRE_Pos</a>   28U</td></tr>
339 <tr class="memdesc:gaf76fa48119363f9b88c2c8f5b74e0a04"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: TRE Position. <br /></td></tr>
340 <tr class="separator:gaf76fa48119363f9b88c2c8f5b74e0a04"><td class="memSeparator" colspan="2"> </td></tr>
341 <tr class="memitem:gab0481eb9812a4908601cb20c8ae84918"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#gab0481eb9812a4908601cb20c8ae84918">SCTLR_TRE_Msk</a>   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#gaf76fa48119363f9b88c2c8f5b74e0a04">SCTLR_TRE_Pos</a>)</td></tr>
342 <tr class="memdesc:gab0481eb9812a4908601cb20c8ae84918"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: TRE Mask. <br /></td></tr>
343 <tr class="separator:gab0481eb9812a4908601cb20c8ae84918"><td class="memSeparator" colspan="2"> </td></tr>
344 <tr class="memitem:gac1cf872c51ed0baa6ed23e26c1ed35a9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#gac1cf872c51ed0baa6ed23e26c1ed35a9">SCTLR_NMFI_Pos</a>   27U</td></tr>
345 <tr class="memdesc:gac1cf872c51ed0baa6ed23e26c1ed35a9"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: NMFI Position. <br /></td></tr>
346 <tr class="separator:gac1cf872c51ed0baa6ed23e26c1ed35a9"><td class="memSeparator" colspan="2"> </td></tr>
347 <tr class="memitem:gab92a3bd63ad9ac3d408e1b615bedc279"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#gab92a3bd63ad9ac3d408e1b615bedc279">SCTLR_NMFI_Msk</a>   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#gac1cf872c51ed0baa6ed23e26c1ed35a9">SCTLR_NMFI_Pos</a>)</td></tr>
348 <tr class="memdesc:gab92a3bd63ad9ac3d408e1b615bedc279"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: NMFI Mask. <br /></td></tr>
349 <tr class="separator:gab92a3bd63ad9ac3d408e1b615bedc279"><td class="memSeparator" colspan="2"> </td></tr>
350 <tr class="memitem:ga0baec19421bd41277c5d8783c59942fa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#ga0baec19421bd41277c5d8783c59942fa">SCTLR_EE_Pos</a>   25U</td></tr>
351 <tr class="memdesc:ga0baec19421bd41277c5d8783c59942fa"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: EE Position. <br /></td></tr>
352 <tr class="separator:ga0baec19421bd41277c5d8783c59942fa"><td class="memSeparator" colspan="2"> </td></tr>
353 <tr class="memitem:ga8d95cd61bc40dc77f8855f40c797d044"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#ga8d95cd61bc40dc77f8855f40c797d044">SCTLR_EE_Msk</a>   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#ga0baec19421bd41277c5d8783c59942fa">SCTLR_EE_Pos</a>)</td></tr>
354 <tr class="memdesc:ga8d95cd61bc40dc77f8855f40c797d044"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: EE Mask. <br /></td></tr>
355 <tr class="separator:ga8d95cd61bc40dc77f8855f40c797d044"><td class="memSeparator" colspan="2"> </td></tr>
356 <tr class="memitem:ga1372b569553a0740d881e24c0be7334f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#ga1372b569553a0740d881e24c0be7334f">SCTLR_VE_Pos</a>   24U</td></tr>
357 <tr class="memdesc:ga1372b569553a0740d881e24c0be7334f"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: VE Position. <br /></td></tr>
358 <tr class="separator:ga1372b569553a0740d881e24c0be7334f"><td class="memSeparator" colspan="2"> </td></tr>
359 <tr class="memitem:gad94a7feadba850299a68c56e39c0b274"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#gad94a7feadba850299a68c56e39c0b274">SCTLR_VE_Msk</a>   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#ga1372b569553a0740d881e24c0be7334f">SCTLR_VE_Pos</a>)</td></tr>
360 <tr class="memdesc:gad94a7feadba850299a68c56e39c0b274"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: VE Mask. <br /></td></tr>
361 <tr class="separator:gad94a7feadba850299a68c56e39c0b274"><td class="memSeparator" colspan="2"> </td></tr>
362 <tr class="memitem:gaa0431730d7ce929db03d8accee558e17"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#gaa0431730d7ce929db03d8accee558e17">SCTLR_U_Pos</a>   22U</td></tr>
363 <tr class="memdesc:gaa0431730d7ce929db03d8accee558e17"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: U Position. <br /></td></tr>
364 <tr class="separator:gaa0431730d7ce929db03d8accee558e17"><td class="memSeparator" colspan="2"> </td></tr>
365 <tr class="memitem:gaa047daa7ab35b5ad5dd238c7377a232f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#gaa047daa7ab35b5ad5dd238c7377a232f">SCTLR_U_Msk</a>   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#gaa0431730d7ce929db03d8accee558e17">SCTLR_U_Pos</a>)</td></tr>
366 <tr class="memdesc:gaa047daa7ab35b5ad5dd238c7377a232f"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: U Mask. <br /></td></tr>
367 <tr class="separator:gaa047daa7ab35b5ad5dd238c7377a232f"><td class="memSeparator" colspan="2"> </td></tr>
368 <tr class="memitem:gad88d563fa9a8b09fe36702a5329b0360"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#gad88d563fa9a8b09fe36702a5329b0360">SCTLR_FI_Pos</a>   21U</td></tr>
369 <tr class="memdesc:gad88d563fa9a8b09fe36702a5329b0360"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: FI Position. <br /></td></tr>
370 <tr class="separator:gad88d563fa9a8b09fe36702a5329b0360"><td class="memSeparator" colspan="2"> </td></tr>
371 <tr class="memitem:ga316b80925b88fe3b88ec46a55655b0bc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#ga316b80925b88fe3b88ec46a55655b0bc">SCTLR_FI_Msk</a>   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#gad88d563fa9a8b09fe36702a5329b0360">SCTLR_FI_Pos</a>)</td></tr>
372 <tr class="memdesc:ga316b80925b88fe3b88ec46a55655b0bc"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: FI Mask. <br /></td></tr>
373 <tr class="separator:ga316b80925b88fe3b88ec46a55655b0bc"><td class="memSeparator" colspan="2"> </td></tr>
374 <tr class="memitem:ga7c7d88f3db4de438ddd069cf3fbc88b3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#ga7c7d88f3db4de438ddd069cf3fbc88b3">SCTLR_UWXN_Pos</a>   20U</td></tr>
375 <tr class="memdesc:ga7c7d88f3db4de438ddd069cf3fbc88b3"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: UWXN Position. <br /></td></tr>
376 <tr class="separator:ga7c7d88f3db4de438ddd069cf3fbc88b3"><td class="memSeparator" colspan="2"> </td></tr>
377 <tr class="memitem:gab834e64e0da7c2a98d747ce73252c199"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#gab834e64e0da7c2a98d747ce73252c199">SCTLR_UWXN_Msk</a>   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#ga7c7d88f3db4de438ddd069cf3fbc88b3">SCTLR_UWXN_Pos</a>)</td></tr>
378 <tr class="memdesc:gab834e64e0da7c2a98d747ce73252c199"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: UWXN Mask. <br /></td></tr>
379 <tr class="separator:gab834e64e0da7c2a98d747ce73252c199"><td class="memSeparator" colspan="2"> </td></tr>
380 <tr class="memitem:gaf145654986fd6d014136580ad279d256"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#gaf145654986fd6d014136580ad279d256">SCTLR_WXN_Pos</a>   19U</td></tr>
381 <tr class="memdesc:gaf145654986fd6d014136580ad279d256"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: WXN Position. <br /></td></tr>
382 <tr class="separator:gaf145654986fd6d014136580ad279d256"><td class="memSeparator" colspan="2"> </td></tr>
383 <tr class="memitem:ga510b03214d135f15ad3c5d41ec20a291"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#ga510b03214d135f15ad3c5d41ec20a291">SCTLR_WXN_Msk</a>   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#gaf145654986fd6d014136580ad279d256">SCTLR_WXN_Pos</a>)</td></tr>
384 <tr class="memdesc:ga510b03214d135f15ad3c5d41ec20a291"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: WXN Mask. <br /></td></tr>
385 <tr class="separator:ga510b03214d135f15ad3c5d41ec20a291"><td class="memSeparator" colspan="2"> </td></tr>
386 <tr class="memitem:ga316882abba6c9cdd31dbbd7ba46c9f52"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#ga316882abba6c9cdd31dbbd7ba46c9f52">SCTLR_HA_Pos</a>   17U</td></tr>
387 <tr class="memdesc:ga316882abba6c9cdd31dbbd7ba46c9f52"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: HA Position. <br /></td></tr>
388 <tr class="separator:ga316882abba6c9cdd31dbbd7ba46c9f52"><td class="memSeparator" colspan="2"> </td></tr>
389 <tr class="memitem:ga6830e9bf54a6b548f329ac047f59c179"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#ga6830e9bf54a6b548f329ac047f59c179">SCTLR_HA_Msk</a>   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#ga316882abba6c9cdd31dbbd7ba46c9f52">SCTLR_HA_Pos</a>)</td></tr>
390 <tr class="memdesc:ga6830e9bf54a6b548f329ac047f59c179"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: HA Mask. <br /></td></tr>
391 <tr class="separator:ga6830e9bf54a6b548f329ac047f59c179"><td class="memSeparator" colspan="2"> </td></tr>
392 <tr class="memitem:ga86e5b78ba8f818061644688db75ddc64"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#ga86e5b78ba8f818061644688db75ddc64">SCTLR_RR_Pos</a>   14U</td></tr>
393 <tr class="memdesc:ga86e5b78ba8f818061644688db75ddc64"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: RR Position. <br /></td></tr>
394 <tr class="separator:ga86e5b78ba8f818061644688db75ddc64"><td class="memSeparator" colspan="2"> </td></tr>
395 <tr class="memitem:ga1ff9e6766c7e1ca312b025bf34d384bc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#ga1ff9e6766c7e1ca312b025bf34d384bc">SCTLR_RR_Msk</a>   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#ga86e5b78ba8f818061644688db75ddc64">SCTLR_RR_Pos</a>)</td></tr>
396 <tr class="memdesc:ga1ff9e6766c7e1ca312b025bf34d384bc"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: RR Mask. <br /></td></tr>
397 <tr class="separator:ga1ff9e6766c7e1ca312b025bf34d384bc"><td class="memSeparator" colspan="2"> </td></tr>
398 <tr class="memitem:ga57778fd6afbe5b4fe8d8ea828acf833d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#ga57778fd6afbe5b4fe8d8ea828acf833d">SCTLR_V_Pos</a>   13U</td></tr>
399 <tr class="memdesc:ga57778fd6afbe5b4fe8d8ea828acf833d"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: V Position. <br /></td></tr>
400 <tr class="separator:ga57778fd6afbe5b4fe8d8ea828acf833d"><td class="memSeparator" colspan="2"> </td></tr>
401 <tr class="memitem:gaf84f3f15bf6917acdc5b5a4ad661ac11"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#gaf84f3f15bf6917acdc5b5a4ad661ac11">SCTLR_V_Msk</a>   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#ga57778fd6afbe5b4fe8d8ea828acf833d">SCTLR_V_Pos</a>)</td></tr>
402 <tr class="memdesc:gaf84f3f15bf6917acdc5b5a4ad661ac11"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: V Mask. <br /></td></tr>
403 <tr class="separator:gaf84f3f15bf6917acdc5b5a4ad661ac11"><td class="memSeparator" colspan="2"> </td></tr>
404 <tr class="memitem:gaaaa818a1da51059bd979f0e768ebcc7c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#gaaaa818a1da51059bd979f0e768ebcc7c">SCTLR_I_Pos</a>   12U</td></tr>
405 <tr class="memdesc:gaaaa818a1da51059bd979f0e768ebcc7c"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: I Position. <br /></td></tr>
406 <tr class="separator:gaaaa818a1da51059bd979f0e768ebcc7c"><td class="memSeparator" colspan="2"> </td></tr>
407 <tr class="memitem:gab3cc0744fb07127e3c0f18cba9d51666"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#gab3cc0744fb07127e3c0f18cba9d51666">SCTLR_I_Msk</a>   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#gaaaa818a1da51059bd979f0e768ebcc7c">SCTLR_I_Pos</a>)</td></tr>
408 <tr class="memdesc:gab3cc0744fb07127e3c0f18cba9d51666"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: I Mask. <br /></td></tr>
409 <tr class="separator:gab3cc0744fb07127e3c0f18cba9d51666"><td class="memSeparator" colspan="2"> </td></tr>
410 <tr class="memitem:gaa0eade648c9a34de891af0e6f47857dd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#gaa0eade648c9a34de891af0e6f47857dd">SCTLR_Z_Pos</a>   11U</td></tr>
411 <tr class="memdesc:gaa0eade648c9a34de891af0e6f47857dd"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: Z Position. <br /></td></tr>
412 <tr class="separator:gaa0eade648c9a34de891af0e6f47857dd"><td class="memSeparator" colspan="2"> </td></tr>
413 <tr class="memitem:ga12a05acdcb8db6e99970f26206d3067c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#ga12a05acdcb8db6e99970f26206d3067c">SCTLR_Z_Msk</a>   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#gaa0eade648c9a34de891af0e6f47857dd">SCTLR_Z_Pos</a>)</td></tr>
414 <tr class="memdesc:ga12a05acdcb8db6e99970f26206d3067c"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: Z Mask. <br /></td></tr>
415 <tr class="separator:ga12a05acdcb8db6e99970f26206d3067c"><td class="memSeparator" colspan="2"> </td></tr>
416 <tr class="memitem:ga3290be0882c1493bca9a0db6b4d0bff8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#ga3290be0882c1493bca9a0db6b4d0bff8">SCTLR_SW_Pos</a>   10U</td></tr>
417 <tr class="memdesc:ga3290be0882c1493bca9a0db6b4d0bff8"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: SW Position. <br /></td></tr>
418 <tr class="separator:ga3290be0882c1493bca9a0db6b4d0bff8"><td class="memSeparator" colspan="2"> </td></tr>
419 <tr class="memitem:gae4074aefcf01786fe199c82e273271b8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#gae4074aefcf01786fe199c82e273271b8">SCTLR_SW_Msk</a>   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#ga3290be0882c1493bca9a0db6b4d0bff8">SCTLR_SW_Pos</a>)</td></tr>
420 <tr class="memdesc:gae4074aefcf01786fe199c82e273271b8"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: SW Mask. <br /></td></tr>
421 <tr class="separator:gae4074aefcf01786fe199c82e273271b8"><td class="memSeparator" colspan="2"> </td></tr>
422 <tr class="memitem:ga5f185efbe1a9eb5738b2573f076a0859"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#ga5f185efbe1a9eb5738b2573f076a0859">SCTLR_B_Pos</a>   7U</td></tr>
423 <tr class="memdesc:ga5f185efbe1a9eb5738b2573f076a0859"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: B Position. <br /></td></tr>
424 <tr class="separator:ga5f185efbe1a9eb5738b2573f076a0859"><td class="memSeparator" colspan="2"> </td></tr>
425 <tr class="memitem:ga4853d6f9ccbf919fcdadb0b2a5913cc6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#ga4853d6f9ccbf919fcdadb0b2a5913cc6">SCTLR_B_Msk</a>   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#ga5f185efbe1a9eb5738b2573f076a0859">SCTLR_B_Pos</a>)</td></tr>
426 <tr class="memdesc:ga4853d6f9ccbf919fcdadb0b2a5913cc6"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: B Mask. <br /></td></tr>
427 <tr class="separator:ga4853d6f9ccbf919fcdadb0b2a5913cc6"><td class="memSeparator" colspan="2"> </td></tr>
428 <tr class="memitem:gace284f69e1a810957665adf0cb2e4b2b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#gace284f69e1a810957665adf0cb2e4b2b">SCTLR_CP15BEN_Pos</a>   5U</td></tr>
429 <tr class="memdesc:gace284f69e1a810957665adf0cb2e4b2b"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: CP15BEN Position. <br /></td></tr>
430 <tr class="separator:gace284f69e1a810957665adf0cb2e4b2b"><td class="memSeparator" colspan="2"> </td></tr>
431 <tr class="memitem:ga5541a6a63db4d4d233b8f57b1d46fbac"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#ga5541a6a63db4d4d233b8f57b1d46fbac">SCTLR_CP15BEN_Msk</a>   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#gace284f69e1a810957665adf0cb2e4b2b">SCTLR_CP15BEN_Pos</a>)</td></tr>
432 <tr class="memdesc:ga5541a6a63db4d4d233b8f57b1d46fbac"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: CP15BEN Mask. <br /></td></tr>
433 <tr class="separator:ga5541a6a63db4d4d233b8f57b1d46fbac"><td class="memSeparator" colspan="2"> </td></tr>
434 <tr class="memitem:ga8a0394c5147b8212767087e3421deffa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#ga8a0394c5147b8212767087e3421deffa">SCTLR_C_Pos</a>   2U</td></tr>
435 <tr class="memdesc:ga8a0394c5147b8212767087e3421deffa"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: C Position. <br /></td></tr>
436 <tr class="separator:ga8a0394c5147b8212767087e3421deffa"><td class="memSeparator" colspan="2"> </td></tr>
437 <tr class="memitem:ga2be72788d984153ded81711e20fd2d33"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#ga2be72788d984153ded81711e20fd2d33">SCTLR_C_Msk</a>   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#ga8a0394c5147b8212767087e3421deffa">SCTLR_C_Pos</a>)</td></tr>
438 <tr class="memdesc:ga2be72788d984153ded81711e20fd2d33"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: C Mask. <br /></td></tr>
439 <tr class="separator:ga2be72788d984153ded81711e20fd2d33"><td class="memSeparator" colspan="2"> </td></tr>
440 <tr class="memitem:ga0d667a307e974515ebc15b5249f34146"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#ga0d667a307e974515ebc15b5249f34146">SCTLR_A_Pos</a>   1U</td></tr>
441 <tr class="memdesc:ga0d667a307e974515ebc15b5249f34146"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: A Position. <br /></td></tr>
442 <tr class="separator:ga0d667a307e974515ebc15b5249f34146"><td class="memSeparator" colspan="2"> </td></tr>
443 <tr class="memitem:ga678c919832272745678213e55211e741"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#ga678c919832272745678213e55211e741">SCTLR_A_Msk</a>   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#ga0d667a307e974515ebc15b5249f34146">SCTLR_A_Pos</a>)</td></tr>
444 <tr class="memdesc:ga678c919832272745678213e55211e741"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: A Mask. <br /></td></tr>
445 <tr class="separator:ga678c919832272745678213e55211e741"><td class="memSeparator" colspan="2"> </td></tr>
446 <tr class="memitem:ga88e34078fa8cf719aab6f53f138c9810"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#ga88e34078fa8cf719aab6f53f138c9810">SCTLR_M_Pos</a>   0U</td></tr>
447 <tr class="memdesc:ga88e34078fa8cf719aab6f53f138c9810"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: M Position. <br /></td></tr>
448 <tr class="separator:ga88e34078fa8cf719aab6f53f138c9810"><td class="memSeparator" colspan="2"> </td></tr>
449 <tr class="memitem:gaf460824cdbf549bd914aa79762572e8e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR__BITS.html#gaf460824cdbf549bd914aa79762572e8e">SCTLR_M_Msk</a>   (1UL << <a class="el" href="group__CMSIS__SCTLR__BITS.html#ga88e34078fa8cf719aab6f53f138c9810">SCTLR_M_Pos</a>)</td></tr>
450 <tr class="memdesc:gaf460824cdbf549bd914aa79762572e8e"><td class="mdescLeft"> </td><td class="mdescRight">SCTLR: M Mask. <br /></td></tr>
451 <tr class="separator:gaf460824cdbf549bd914aa79762572e8e"><td class="memSeparator" colspan="2"> </td></tr>
452 <tr class="memitem:ga5468e93550ce28af7114cbc1e19474c0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#ga5468e93550ce28af7114cbc1e19474c0">ACTLR_DDI_Pos</a>   28U</td></tr>
453 <tr class="memdesc:ga5468e93550ce28af7114cbc1e19474c0"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: DDI Position. <br /></td></tr>
454 <tr class="separator:ga5468e93550ce28af7114cbc1e19474c0"><td class="memSeparator" colspan="2"> </td></tr>
455 <tr class="memitem:gaeee8e0fc7b28f2a405b234e7d2c7486e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#gaeee8e0fc7b28f2a405b234e7d2c7486e">ACTLR_DDI_Msk</a>   (1UL << <a class="el" href="group__CMSIS__ACTLR__BITS.html#ga5468e93550ce28af7114cbc1e19474c0">ACTLR_DDI_Pos</a>)</td></tr>
456 <tr class="memdesc:gaeee8e0fc7b28f2a405b234e7d2c7486e"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: DDI Mask. <br /></td></tr>
457 <tr class="separator:gaeee8e0fc7b28f2a405b234e7d2c7486e"><td class="memSeparator" colspan="2"> </td></tr>
458 <tr class="memitem:ga0367a8413c0a37d6c1de7b90f3a56aee"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#ga0367a8413c0a37d6c1de7b90f3a56aee">ACTLR_DBDI_Pos</a>   28U</td></tr>
459 <tr class="memdesc:ga0367a8413c0a37d6c1de7b90f3a56aee"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: DBDI Position. <br /></td></tr>
460 <tr class="separator:ga0367a8413c0a37d6c1de7b90f3a56aee"><td class="memSeparator" colspan="2"> </td></tr>
461 <tr class="memitem:ga0a3d58754927731758c53bd945ac35fe"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#ga0a3d58754927731758c53bd945ac35fe">ACTLR_DBDI_Msk</a>   (1UL << <a class="el" href="group__CMSIS__ACTLR__BITS.html#ga0367a8413c0a37d6c1de7b90f3a56aee">ACTLR_DBDI_Pos</a>)</td></tr>
462 <tr class="memdesc:ga0a3d58754927731758c53bd945ac35fe"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: DBDI Mask. <br /></td></tr>
463 <tr class="separator:ga0a3d58754927731758c53bd945ac35fe"><td class="memSeparator" colspan="2"> </td></tr>
464 <tr class="memitem:ga8c81a1e1522400322f215c52ca80d47d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#ga8c81a1e1522400322f215c52ca80d47d">ACTLR_BTDIS_Pos</a>   18U</td></tr>
465 <tr class="memdesc:ga8c81a1e1522400322f215c52ca80d47d"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: BTDIS Position. <br /></td></tr>
466 <tr class="separator:ga8c81a1e1522400322f215c52ca80d47d"><td class="memSeparator" colspan="2"> </td></tr>
467 <tr class="memitem:gad48e0a1c1e59e6721547b45f37baa48b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#gad48e0a1c1e59e6721547b45f37baa48b">ACTLR_BTDIS_Msk</a>   (1UL << <a class="el" href="group__CMSIS__ACTLR__BITS.html#ga8c81a1e1522400322f215c52ca80d47d">ACTLR_BTDIS_Pos</a>)</td></tr>
468 <tr class="memdesc:gad48e0a1c1e59e6721547b45f37baa48b"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: BTDIS Mask. <br /></td></tr>
469 <tr class="separator:gad48e0a1c1e59e6721547b45f37baa48b"><td class="memSeparator" colspan="2"> </td></tr>
470 <tr class="memitem:ga4412a55ce52db3c5a4f035fcd0e350c6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#ga4412a55ce52db3c5a4f035fcd0e350c6">ACTLR_RSDIS_Pos</a>   17U</td></tr>
471 <tr class="memdesc:ga4412a55ce52db3c5a4f035fcd0e350c6"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: RSDIS Position. <br /></td></tr>
472 <tr class="separator:ga4412a55ce52db3c5a4f035fcd0e350c6"><td class="memSeparator" colspan="2"> </td></tr>
473 <tr class="memitem:ga8487babc3514e2bb8f3d524e5f80d95f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#ga8487babc3514e2bb8f3d524e5f80d95f">ACTLR_RSDIS_Msk</a>   (1UL << <a class="el" href="group__CMSIS__ACTLR__BITS.html#ga4412a55ce52db3c5a4f035fcd0e350c6">ACTLR_RSDIS_Pos</a>)</td></tr>
474 <tr class="memdesc:ga8487babc3514e2bb8f3d524e5f80d95f"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: RSDIS Mask. <br /></td></tr>
475 <tr class="separator:ga8487babc3514e2bb8f3d524e5f80d95f"><td class="memSeparator" colspan="2"> </td></tr>
476 <tr class="memitem:ga120f5d653af52bd711c27c2495ce78f6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#ga120f5d653af52bd711c27c2495ce78f6">ACTLR_BP_Pos</a>   15U</td></tr>
477 <tr class="memdesc:ga120f5d653af52bd711c27c2495ce78f6"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: BP Position. <br /></td></tr>
478 <tr class="separator:ga120f5d653af52bd711c27c2495ce78f6"><td class="memSeparator" colspan="2"> </td></tr>
479 <tr class="memitem:ga677211818d8a2c7b118115361fbef2e7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#ga677211818d8a2c7b118115361fbef2e7">ACTLR_BP_Msk</a>   (3UL << <a class="el" href="group__CMSIS__ACTLR__BITS.html#ga120f5d653af52bd711c27c2495ce78f6">ACTLR_BP_Pos</a>)</td></tr>
480 <tr class="memdesc:ga677211818d8a2c7b118115361fbef2e7"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: BP Mask. <br /></td></tr>
481 <tr class="separator:ga677211818d8a2c7b118115361fbef2e7"><td class="memSeparator" colspan="2"> </td></tr>
482 <tr class="memitem:gaa9fe7651aa9bb48eea4f5301c69ee54d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#gaa9fe7651aa9bb48eea4f5301c69ee54d">ACTLR_DDVM_Pos</a>   15U</td></tr>
483 <tr class="memdesc:gaa9fe7651aa9bb48eea4f5301c69ee54d"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: DDVM Position. <br /></td></tr>
484 <tr class="separator:gaa9fe7651aa9bb48eea4f5301c69ee54d"><td class="memSeparator" colspan="2"> </td></tr>
485 <tr class="memitem:ga4565f2632e5c4be5e1d3eb90fa6f2ac6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#ga4565f2632e5c4be5e1d3eb90fa6f2ac6">ACTLR_DDVM_Msk</a>   (1UL << <a class="el" href="group__CMSIS__ACTLR__BITS.html#gaa9fe7651aa9bb48eea4f5301c69ee54d">ACTLR_DDVM_Pos</a>)</td></tr>
486 <tr class="memdesc:ga4565f2632e5c4be5e1d3eb90fa6f2ac6"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: DDVM Mask. <br /></td></tr>
487 <tr class="separator:ga4565f2632e5c4be5e1d3eb90fa6f2ac6"><td class="memSeparator" colspan="2"> </td></tr>
488 <tr class="memitem:ga546f1f2bbf7344bad6522205257f17ae"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#ga546f1f2bbf7344bad6522205257f17ae">ACTLR_L1PCTL_Pos</a>   13U</td></tr>
489 <tr class="memdesc:ga546f1f2bbf7344bad6522205257f17ae"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: L1PCTL Position. <br /></td></tr>
490 <tr class="separator:ga546f1f2bbf7344bad6522205257f17ae"><td class="memSeparator" colspan="2"> </td></tr>
491 <tr class="memitem:gad701fa3ff69b89ba185b7482e81cb6fd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#gad701fa3ff69b89ba185b7482e81cb6fd">ACTLR_L1PCTL_Msk</a>   (3UL << <a class="el" href="group__CMSIS__ACTLR__BITS.html#ga546f1f2bbf7344bad6522205257f17ae">ACTLR_L1PCTL_Pos</a>)</td></tr>
492 <tr class="memdesc:gad701fa3ff69b89ba185b7482e81cb6fd"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: L1PCTL Mask. <br /></td></tr>
493 <tr class="separator:gad701fa3ff69b89ba185b7482e81cb6fd"><td class="memSeparator" colspan="2"> </td></tr>
494 <tr class="memitem:gaf7a424f7f8c4f46592ce8f47f4bced44"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#gaf7a424f7f8c4f46592ce8f47f4bced44">ACTLR_RADIS_Pos</a>   12U</td></tr>
495 <tr class="memdesc:gaf7a424f7f8c4f46592ce8f47f4bced44"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: RADIS Position. <br /></td></tr>
496 <tr class="separator:gaf7a424f7f8c4f46592ce8f47f4bced44"><td class="memSeparator" colspan="2"> </td></tr>
497 <tr class="memitem:gac6aea849e5320c0e93321d5d8b0c117c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#gac6aea849e5320c0e93321d5d8b0c117c">ACTLR_RADIS_Msk</a>   (1UL << <a class="el" href="group__CMSIS__ACTLR__BITS.html#gaf7a424f7f8c4f46592ce8f47f4bced44">ACTLR_RADIS_Pos</a>)</td></tr>
498 <tr class="memdesc:gac6aea849e5320c0e93321d5d8b0c117c"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: RADIS Mask. <br /></td></tr>
499 <tr class="separator:gac6aea849e5320c0e93321d5d8b0c117c"><td class="memSeparator" colspan="2"> </td></tr>
500 <tr class="memitem:gaf8b306b854ecd78110cf944d414644a1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#gaf8b306b854ecd78110cf944d414644a1">ACTLR_L1RADIS_Pos</a>   12U</td></tr>
501 <tr class="memdesc:gaf8b306b854ecd78110cf944d414644a1"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: L1RADIS Position. <br /></td></tr>
502 <tr class="separator:gaf8b306b854ecd78110cf944d414644a1"><td class="memSeparator" colspan="2"> </td></tr>
503 <tr class="memitem:ga6aafd83ca6c02f705def8edc8c064c04"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#ga6aafd83ca6c02f705def8edc8c064c04">ACTLR_L1RADIS_Msk</a>   (1UL << <a class="el" href="group__CMSIS__ACTLR__BITS.html#gaf8b306b854ecd78110cf944d414644a1">ACTLR_L1RADIS_Pos</a>)</td></tr>
504 <tr class="memdesc:ga6aafd83ca6c02f705def8edc8c064c04"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: L1RADIS Mask. <br /></td></tr>
505 <tr class="separator:ga6aafd83ca6c02f705def8edc8c064c04"><td class="memSeparator" colspan="2"> </td></tr>
506 <tr class="memitem:ga4ca2a9236b157d3f9405cf8c398897a2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#ga4ca2a9236b157d3f9405cf8c398897a2">ACTLR_DWBST_Pos</a>   11U</td></tr>
507 <tr class="memdesc:ga4ca2a9236b157d3f9405cf8c398897a2"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: DWBST Position. <br /></td></tr>
508 <tr class="separator:ga4ca2a9236b157d3f9405cf8c398897a2"><td class="memSeparator" colspan="2"> </td></tr>
509 <tr class="memitem:gab948ab9af88a9357e2e383d948e9dc7e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#gab948ab9af88a9357e2e383d948e9dc7e">ACTLR_DWBST_Msk</a>   (1UL << <a class="el" href="group__CMSIS__ACTLR__BITS.html#ga4ca2a9236b157d3f9405cf8c398897a2">ACTLR_DWBST_Pos</a>)</td></tr>
510 <tr class="memdesc:gab948ab9af88a9357e2e383d948e9dc7e"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: DWBST Mask. <br /></td></tr>
511 <tr class="separator:gab948ab9af88a9357e2e383d948e9dc7e"><td class="memSeparator" colspan="2"> </td></tr>
512 <tr class="memitem:ga505f33bbe45bbcaa9fcb738cb30daf4e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#ga505f33bbe45bbcaa9fcb738cb30daf4e">ACTLR_L2RADIS_Pos</a>   11U</td></tr>
513 <tr class="memdesc:ga505f33bbe45bbcaa9fcb738cb30daf4e"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: L2RADIS Position. <br /></td></tr>
514 <tr class="separator:ga505f33bbe45bbcaa9fcb738cb30daf4e"><td class="memSeparator" colspan="2"> </td></tr>
515 <tr class="memitem:gad84b20f4f5d1979bb000a14a582cad12"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#gad84b20f4f5d1979bb000a14a582cad12">ACTLR_L2RADIS_Msk</a>   (1UL << <a class="el" href="group__CMSIS__ACTLR__BITS.html#ga505f33bbe45bbcaa9fcb738cb30daf4e">ACTLR_L2RADIS_Pos</a>)</td></tr>
516 <tr class="memdesc:gad84b20f4f5d1979bb000a14a582cad12"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: L2RADIS Mask. <br /></td></tr>
517 <tr class="separator:gad84b20f4f5d1979bb000a14a582cad12"><td class="memSeparator" colspan="2"> </td></tr>
518 <tr class="memitem:ga96eb411770c8e2b87f5e62b95e50ee02"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#ga96eb411770c8e2b87f5e62b95e50ee02">ACTLR_DODMBS_Pos</a>   10U</td></tr>
519 <tr class="memdesc:ga96eb411770c8e2b87f5e62b95e50ee02"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: DODMBS Position. <br /></td></tr>
520 <tr class="separator:ga96eb411770c8e2b87f5e62b95e50ee02"><td class="memSeparator" colspan="2"> </td></tr>
521 <tr class="memitem:ga88a85e6310334edb190a6e9298ae98b7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#ga88a85e6310334edb190a6e9298ae98b7">ACTLR_DODMBS_Msk</a>   (1UL << <a class="el" href="group__CMSIS__ACTLR__BITS.html#ga96eb411770c8e2b87f5e62b95e50ee02">ACTLR_DODMBS_Pos</a>)</td></tr>
522 <tr class="memdesc:ga88a85e6310334edb190a6e9298ae98b7"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: DODMBS Mask. <br /></td></tr>
523 <tr class="separator:ga88a85e6310334edb190a6e9298ae98b7"><td class="memSeparator" colspan="2"> </td></tr>
524 <tr class="memitem:ga8300a65b41aa3f5c69c7cc713c847749"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#ga8300a65b41aa3f5c69c7cc713c847749">ACTLR_PARITY_Pos</a>   9U</td></tr>
525 <tr class="memdesc:ga8300a65b41aa3f5c69c7cc713c847749"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: PARITY Position. <br /></td></tr>
526 <tr class="separator:ga8300a65b41aa3f5c69c7cc713c847749"><td class="memSeparator" colspan="2"> </td></tr>
527 <tr class="memitem:gadec8e5d68791dc4749bf3f075a3559fb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#gadec8e5d68791dc4749bf3f075a3559fb">ACTLR_PARITY_Msk</a>   (1UL << <a class="el" href="group__CMSIS__ACTLR__BITS.html#ga8300a65b41aa3f5c69c7cc713c847749">ACTLR_PARITY_Pos</a>)</td></tr>
528 <tr class="memdesc:gadec8e5d68791dc4749bf3f075a3559fb"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: PARITY Mask. <br /></td></tr>
529 <tr class="separator:gadec8e5d68791dc4749bf3f075a3559fb"><td class="memSeparator" colspan="2"> </td></tr>
530 <tr class="memitem:ga633ee6b129f8668593687ab8537aeb7f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#ga633ee6b129f8668593687ab8537aeb7f">ACTLR_AOW_Pos</a>   8U</td></tr>
531 <tr class="memdesc:ga633ee6b129f8668593687ab8537aeb7f"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: AOW Position. <br /></td></tr>
532 <tr class="separator:ga633ee6b129f8668593687ab8537aeb7f"><td class="memSeparator" colspan="2"> </td></tr>
533 <tr class="memitem:ga5ca6754c31f90c7e5d1822dddfb4135c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#ga5ca6754c31f90c7e5d1822dddfb4135c">ACTLR_AOW_Msk</a>   (1UL << <a class="el" href="group__CMSIS__ACTLR__BITS.html#ga633ee6b129f8668593687ab8537aeb7f">ACTLR_AOW_Pos</a>)</td></tr>
534 <tr class="memdesc:ga5ca6754c31f90c7e5d1822dddfb4135c"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: AOW Mask. <br /></td></tr>
535 <tr class="separator:ga5ca6754c31f90c7e5d1822dddfb4135c"><td class="memSeparator" colspan="2"> </td></tr>
536 <tr class="memitem:ga17dcfbcdf5db82900354db5440699701"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#ga17dcfbcdf5db82900354db5440699701">ACTLR_EXCL_Pos</a>   7U</td></tr>
537 <tr class="memdesc:ga17dcfbcdf5db82900354db5440699701"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: EXCL Position. <br /></td></tr>
538 <tr class="separator:ga17dcfbcdf5db82900354db5440699701"><td class="memSeparator" colspan="2"> </td></tr>
539 <tr class="memitem:ga8b704419a7ed130ecbee00de9fd72d55"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#ga8b704419a7ed130ecbee00de9fd72d55">ACTLR_EXCL_Msk</a>   (1UL << <a class="el" href="group__CMSIS__ACTLR__BITS.html#ga17dcfbcdf5db82900354db5440699701">ACTLR_EXCL_Pos</a>)</td></tr>
540 <tr class="memdesc:ga8b704419a7ed130ecbee00de9fd72d55"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: EXCL Mask. <br /></td></tr>
541 <tr class="separator:ga8b704419a7ed130ecbee00de9fd72d55"><td class="memSeparator" colspan="2"> </td></tr>
542 <tr class="memitem:ga8cb19db067cca1e064189b27b1f1bcbf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#ga8cb19db067cca1e064189b27b1f1bcbf">ACTLR_SMP_Pos</a>   6U</td></tr>
543 <tr class="memdesc:ga8cb19db067cca1e064189b27b1f1bcbf"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: SMP Position. <br /></td></tr>
544 <tr class="separator:ga8cb19db067cca1e064189b27b1f1bcbf"><td class="memSeparator" colspan="2"> </td></tr>
545 <tr class="memitem:gac6dcc315f6c4527434b9b0e4106771d8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#gac6dcc315f6c4527434b9b0e4106771d8">ACTLR_SMP_Msk</a>   (1UL << <a class="el" href="group__CMSIS__ACTLR__BITS.html#ga8cb19db067cca1e064189b27b1f1bcbf">ACTLR_SMP_Pos</a>)</td></tr>
546 <tr class="memdesc:gac6dcc315f6c4527434b9b0e4106771d8"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: SMP Mask. <br /></td></tr>
547 <tr class="separator:gac6dcc315f6c4527434b9b0e4106771d8"><td class="memSeparator" colspan="2"> </td></tr>
548 <tr class="memitem:ga104112fe1d88dde49635e9b0f9530306"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#ga104112fe1d88dde49635e9b0f9530306">ACTLR_WFLZM_Pos</a>   3U</td></tr>
549 <tr class="memdesc:ga104112fe1d88dde49635e9b0f9530306"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: WFLZM Position. <br /></td></tr>
550 <tr class="separator:ga104112fe1d88dde49635e9b0f9530306"><td class="memSeparator" colspan="2"> </td></tr>
551 <tr class="memitem:gae5a89cb553773b10e86a9c826f11179f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#gae5a89cb553773b10e86a9c826f11179f">ACTLR_WFLZM_Msk</a>   (1UL << <a class="el" href="group__CMSIS__ACTLR__BITS.html#ga104112fe1d88dde49635e9b0f9530306">ACTLR_WFLZM_Pos</a>)</td></tr>
552 <tr class="memdesc:gae5a89cb553773b10e86a9c826f11179f"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: WFLZM Mask. <br /></td></tr>
553 <tr class="separator:gae5a89cb553773b10e86a9c826f11179f"><td class="memSeparator" colspan="2"> </td></tr>
554 <tr class="memitem:ga65c3c81261a2aa26022f6bb967c4e56b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#ga65c3c81261a2aa26022f6bb967c4e56b">ACTLR_L1PE_Pos</a>   2U</td></tr>
555 <tr class="memdesc:ga65c3c81261a2aa26022f6bb967c4e56b"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: L1PE Position. <br /></td></tr>
556 <tr class="separator:ga65c3c81261a2aa26022f6bb967c4e56b"><td class="memSeparator" colspan="2"> </td></tr>
557 <tr class="memitem:ga969c20495fe3e50e8c2a73454688a674"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#ga969c20495fe3e50e8c2a73454688a674">ACTLR_L1PE_Msk</a>   (1UL << <a class="el" href="group__CMSIS__ACTLR__BITS.html#ga65c3c81261a2aa26022f6bb967c4e56b">ACTLR_L1PE_Pos</a>)</td></tr>
558 <tr class="memdesc:ga969c20495fe3e50e8c2a73454688a674"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: L1PE Mask. <br /></td></tr>
559 <tr class="separator:ga969c20495fe3e50e8c2a73454688a674"><td class="memSeparator" colspan="2"> </td></tr>
560 <tr class="memitem:ga89b1a661668534177bc9679149a692ce"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#ga89b1a661668534177bc9679149a692ce">ACTLR_FW_Pos</a>   0U</td></tr>
561 <tr class="memdesc:ga89b1a661668534177bc9679149a692ce"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: FW Position. <br /></td></tr>
562 <tr class="separator:ga89b1a661668534177bc9679149a692ce"><td class="memSeparator" colspan="2"> </td></tr>
563 <tr class="memitem:ga53ea0cfa2dd5cb51d9f9de21e4d2dbf1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR__BITS.html#ga53ea0cfa2dd5cb51d9f9de21e4d2dbf1">ACTLR_FW_Msk</a>   (1UL << <a class="el" href="group__CMSIS__ACTLR__BITS.html#ga89b1a661668534177bc9679149a692ce">ACTLR_FW_Pos</a>)</td></tr>
564 <tr class="memdesc:ga53ea0cfa2dd5cb51d9f9de21e4d2dbf1"><td class="mdescLeft"> </td><td class="mdescRight">ACTLR: FW Mask. <br /></td></tr>
565 <tr class="separator:ga53ea0cfa2dd5cb51d9f9de21e4d2dbf1"><td class="memSeparator" colspan="2"> </td></tr>
566 <tr class="memitem:ga3acd342ab1e88bd4ad73f5670e7af163"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPACR__BITS.html#ga3acd342ab1e88bd4ad73f5670e7af163">CPACR_ASEDIS_Pos</a>   31U</td></tr>
567 <tr class="memdesc:ga3acd342ab1e88bd4ad73f5670e7af163"><td class="mdescLeft"> </td><td class="mdescRight">CPACR: ASEDIS Position. <br /></td></tr>
568 <tr class="separator:ga3acd342ab1e88bd4ad73f5670e7af163"><td class="memSeparator" colspan="2"> </td></tr>
569 <tr class="memitem:ga46d28804bfa370b0dd4ac520a7a67609"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPACR__BITS.html#ga46d28804bfa370b0dd4ac520a7a67609">CPACR_ASEDIS_Msk</a>   (1UL << <a class="el" href="group__CMSIS__CPACR__BITS.html#ga3acd342ab1e88bd4ad73f5670e7af163">CPACR_ASEDIS_Pos</a>)</td></tr>
570 <tr class="memdesc:ga46d28804bfa370b0dd4ac520a7a67609"><td class="mdescLeft"> </td><td class="mdescRight">CPACR: ASEDIS Mask. <br /></td></tr>
571 <tr class="separator:ga46d28804bfa370b0dd4ac520a7a67609"><td class="memSeparator" colspan="2"> </td></tr>
572 <tr class="memitem:ga6df0c4e805105285e63b0f0e992bd416"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPACR__BITS.html#ga6df0c4e805105285e63b0f0e992bd416">CPACR_D32DIS_Pos</a>   30U</td></tr>
573 <tr class="memdesc:ga6df0c4e805105285e63b0f0e992bd416"><td class="mdescLeft"> </td><td class="mdescRight">CPACR: D32DIS Position. <br /></td></tr>
574 <tr class="separator:ga6df0c4e805105285e63b0f0e992bd416"><td class="memSeparator" colspan="2"> </td></tr>
575 <tr class="memitem:ga96266eb6bf35c3c3f22718bd06b12d79"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPACR__BITS.html#ga96266eb6bf35c3c3f22718bd06b12d79">CPACR_D32DIS_Msk</a>   (1UL << <a class="el" href="group__CMSIS__CPACR__BITS.html#ga6df0c4e805105285e63b0f0e992bd416">CPACR_D32DIS_Pos</a>)</td></tr>
576 <tr class="memdesc:ga96266eb6bf35c3c3f22718bd06b12d79"><td class="mdescLeft"> </td><td class="mdescRight">CPACR: D32DIS Mask. <br /></td></tr>
577 <tr class="separator:ga96266eb6bf35c3c3f22718bd06b12d79"><td class="memSeparator" colspan="2"> </td></tr>
578 <tr class="memitem:ga6866c97020fdba42f7c287433c58d77c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPACR__BITS.html#ga6866c97020fdba42f7c287433c58d77c">CPACR_TRCDIS_Pos</a>   28U</td></tr>
579 <tr class="memdesc:ga6866c97020fdba42f7c287433c58d77c"><td class="mdescLeft"> </td><td class="mdescRight">CPACR: D32DIS Position. <br /></td></tr>
580 <tr class="separator:ga6866c97020fdba42f7c287433c58d77c"><td class="memSeparator" colspan="2"> </td></tr>
581 <tr class="memitem:gab5d6ec83339e755bd3e7eacb914edf37"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPACR__BITS.html#gab5d6ec83339e755bd3e7eacb914edf37">CPACR_TRCDIS_Msk</a>   (1UL << <a class="el" href="group__CMSIS__CPACR__BITS.html#ga6df0c4e805105285e63b0f0e992bd416">CPACR_D32DIS_Pos</a>)</td></tr>
582 <tr class="memdesc:gab5d6ec83339e755bd3e7eacb914edf37"><td class="mdescLeft"> </td><td class="mdescRight">CPACR: D32DIS Mask. <br /></td></tr>
583 <tr class="separator:gab5d6ec83339e755bd3e7eacb914edf37"><td class="memSeparator" colspan="2"> </td></tr>
584 <tr class="memitem:ga77dc035e6d16dee8f5cf53b36b86cfaf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPACR__BITS.html#ga77dc035e6d16dee8f5cf53b36b86cfaf">CPACR_CP_Pos_</a>(n)   (n*2U)</td></tr>
585 <tr class="memdesc:ga77dc035e6d16dee8f5cf53b36b86cfaf"><td class="mdescLeft"> </td><td class="mdescRight">CPACR: CPn Position. <br /></td></tr>
586 <tr class="separator:ga77dc035e6d16dee8f5cf53b36b86cfaf"><td class="memSeparator" colspan="2"> </td></tr>
587 <tr class="memitem:ga7c87723442baa681a80de8f644eda1a2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPACR__BITS.html#ga7c87723442baa681a80de8f644eda1a2">CPACR_CP_Msk_</a>(n)   (3UL << <a class="el" href="group__CMSIS__CPACR__BITS.html#ga77dc035e6d16dee8f5cf53b36b86cfaf">CPACR_CP_Pos_</a>(n))</td></tr>
588 <tr class="memdesc:ga7c87723442baa681a80de8f644eda1a2"><td class="mdescLeft"> </td><td class="mdescRight">CPACR: CPn Mask. <br /></td></tr>
589 <tr class="separator:ga7c87723442baa681a80de8f644eda1a2"><td class="memSeparator" colspan="2"> </td></tr>
590 <tr class="memitem:gabd03f590b34b809438eaa3df4af2e7db"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPACR__CP.html#gabd03f590b34b809438eaa3df4af2e7db">CPACR_CP_NA</a>   0U</td></tr>
591 <tr class="memdesc:gabd03f590b34b809438eaa3df4af2e7db"><td class="mdescLeft"> </td><td class="mdescRight">CPACR CPn field: Access denied. <br /></td></tr>
592 <tr class="separator:gabd03f590b34b809438eaa3df4af2e7db"><td class="memSeparator" colspan="2"> </td></tr>
593 <tr class="memitem:ga8602342c0bad80f3a36d3bdee7418a46"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPACR__CP.html#ga8602342c0bad80f3a36d3bdee7418a46">CPACR_CP_PL1</a>   1U</td></tr>
594 <tr class="memdesc:ga8602342c0bad80f3a36d3bdee7418a46"><td class="mdescLeft"> </td><td class="mdescRight">CPACR CPn field: Accessible from PL1 only. <br /></td></tr>
595 <tr class="separator:ga8602342c0bad80f3a36d3bdee7418a46"><td class="memSeparator" colspan="2"> </td></tr>
596 <tr class="memitem:gaeaa29f06a74fadc7245d6bd183bad11b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPACR__CP.html#gaeaa29f06a74fadc7245d6bd183bad11b">CPACR_CP_FA</a>   3U</td></tr>
597 <tr class="memdesc:gaeaa29f06a74fadc7245d6bd183bad11b"><td class="mdescLeft"> </td><td class="mdescRight">CPACR CPn field: Full access. <br /></td></tr>
598 <tr class="separator:gaeaa29f06a74fadc7245d6bd183bad11b"><td class="memSeparator" colspan="2"> </td></tr>
599 <tr class="memitem:gac1c7d8f30e77bd1fe395d6e9a5a63a3e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__DFSR__BITS.html#gac1c7d8f30e77bd1fe395d6e9a5a63a3e">DFSR_CM_Pos</a>   13U</td></tr>
600 <tr class="memdesc:gac1c7d8f30e77bd1fe395d6e9a5a63a3e"><td class="mdescLeft"> </td><td class="mdescRight">DFSR: CM Position. <br /></td></tr>
601 <tr class="separator:gac1c7d8f30e77bd1fe395d6e9a5a63a3e"><td class="memSeparator" colspan="2"> </td></tr>
602 <tr class="memitem:ga91cf285dc43beda62ae72f043e83238c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__DFSR__BITS.html#ga91cf285dc43beda62ae72f043e83238c">DFSR_CM_Msk</a>   (1UL << <a class="el" href="group__CMSIS__DFSR__BITS.html#gac1c7d8f30e77bd1fe395d6e9a5a63a3e">DFSR_CM_Pos</a>)</td></tr>
603 <tr class="memdesc:ga91cf285dc43beda62ae72f043e83238c"><td class="mdescLeft"> </td><td class="mdescRight">DFSR: CM Mask. <br /></td></tr>
604 <tr class="separator:ga91cf285dc43beda62ae72f043e83238c"><td class="memSeparator" colspan="2"> </td></tr>
605 <tr class="memitem:ga8cc8dcb1b3a971a13b0575bf9083acf5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__DFSR__BITS.html#ga8cc8dcb1b3a971a13b0575bf9083acf5">DFSR_Ext_Pos</a>   12U</td></tr>
606 <tr class="memdesc:ga8cc8dcb1b3a971a13b0575bf9083acf5"><td class="mdescLeft"> </td><td class="mdescRight">DFSR: Ext Position. <br /></td></tr>
607 <tr class="separator:ga8cc8dcb1b3a971a13b0575bf9083acf5"><td class="memSeparator" colspan="2"> </td></tr>
608 <tr class="memitem:gad3a97b4eb87f45df8ae539e59592f21b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__DFSR__BITS.html#gad3a97b4eb87f45df8ae539e59592f21b">DFSR_Ext_Msk</a>   (1UL << <a class="el" href="group__CMSIS__DFSR__BITS.html#ga8cc8dcb1b3a971a13b0575bf9083acf5">DFSR_Ext_Pos</a>)</td></tr>
609 <tr class="memdesc:gad3a97b4eb87f45df8ae539e59592f21b"><td class="mdescLeft"> </td><td class="mdescRight">DFSR: Ext Mask. <br /></td></tr>
610 <tr class="separator:gad3a97b4eb87f45df8ae539e59592f21b"><td class="memSeparator" colspan="2"> </td></tr>
611 <tr class="memitem:ga410420633e9ba47cdd1ae2d3df146866"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__DFSR__BITS.html#ga410420633e9ba47cdd1ae2d3df146866">DFSR_WnR_Pos</a>   11U</td></tr>
612 <tr class="memdesc:ga410420633e9ba47cdd1ae2d3df146866"><td class="mdescLeft"> </td><td class="mdescRight">DFSR: WnR Position. <br /></td></tr>
613 <tr class="separator:ga410420633e9ba47cdd1ae2d3df146866"><td class="memSeparator" colspan="2"> </td></tr>
614 <tr class="memitem:gabfbf482895e7620fe6727b54378c0f2a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__DFSR__BITS.html#gabfbf482895e7620fe6727b54378c0f2a">DFSR_WnR_Msk</a>   (1UL << <a class="el" href="group__CMSIS__DFSR__BITS.html#ga410420633e9ba47cdd1ae2d3df146866">DFSR_WnR_Pos</a>)</td></tr>
615 <tr class="memdesc:gabfbf482895e7620fe6727b54378c0f2a"><td class="mdescLeft"> </td><td class="mdescRight">DFSR: WnR Mask. <br /></td></tr>
616 <tr class="separator:gabfbf482895e7620fe6727b54378c0f2a"><td class="memSeparator" colspan="2"> </td></tr>
617 <tr class="memitem:ga3faee10970931cadf7ff16069ce65a1a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__DFSR__BITS.html#ga3faee10970931cadf7ff16069ce65a1a">DFSR_FS1_Pos</a>   10U</td></tr>
618 <tr class="memdesc:ga3faee10970931cadf7ff16069ce65a1a"><td class="mdescLeft"> </td><td class="mdescRight">DFSR: FS1 Position. <br /></td></tr>
619 <tr class="separator:ga3faee10970931cadf7ff16069ce65a1a"><td class="memSeparator" colspan="2"> </td></tr>
620 <tr class="memitem:ga6540a3ca5b2dcf8f81bb37fbdbe9d746"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__DFSR__BITS.html#ga6540a3ca5b2dcf8f81bb37fbdbe9d746">DFSR_FS1_Msk</a>   (1UL << <a class="el" href="group__CMSIS__DFSR__BITS.html#ga3faee10970931cadf7ff16069ce65a1a">DFSR_FS1_Pos</a>)</td></tr>
621 <tr class="memdesc:ga6540a3ca5b2dcf8f81bb37fbdbe9d746"><td class="mdescLeft"> </td><td class="mdescRight">DFSR: FS1 Mask. <br /></td></tr>
622 <tr class="separator:ga6540a3ca5b2dcf8f81bb37fbdbe9d746"><td class="memSeparator" colspan="2"> </td></tr>
623 <tr class="memitem:ga10f7b48c4f128c9be07c377bb60cfa7a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__DFSR__BITS.html#ga10f7b48c4f128c9be07c377bb60cfa7a">DFSR_LPAE_Pos</a>   9U</td></tr>
624 <tr class="memdesc:ga10f7b48c4f128c9be07c377bb60cfa7a"><td class="mdescLeft"> </td><td class="mdescRight">DFSR: LPAE Position. <br /></td></tr>
625 <tr class="separator:ga10f7b48c4f128c9be07c377bb60cfa7a"><td class="memSeparator" colspan="2"> </td></tr>
626 <tr class="memitem:ga104bfa1e333340616fdbdc804948276f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__DFSR__BITS.html#ga104bfa1e333340616fdbdc804948276f">DFSR_LPAE_Msk</a>   (1UL << <a class="el" href="group__CMSIS__DFSR__BITS.html#ga10f7b48c4f128c9be07c377bb60cfa7a">DFSR_LPAE_Pos</a>)</td></tr>
627 <tr class="memdesc:ga104bfa1e333340616fdbdc804948276f"><td class="mdescLeft"> </td><td class="mdescRight">DFSR: LPAE Mask. <br /></td></tr>
628 <tr class="separator:ga104bfa1e333340616fdbdc804948276f"><td class="memSeparator" colspan="2"> </td></tr>
629 <tr class="memitem:gac5a7afc43963dbc429792fb5a1569e15"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__DFSR__BITS.html#gac5a7afc43963dbc429792fb5a1569e15">DFSR_Domain_Pos</a>   4U</td></tr>
630 <tr class="memdesc:gac5a7afc43963dbc429792fb5a1569e15"><td class="mdescLeft"> </td><td class="mdescRight">DFSR: Domain Position. <br /></td></tr>
631 <tr class="separator:gac5a7afc43963dbc429792fb5a1569e15"><td class="memSeparator" colspan="2"> </td></tr>
632 <tr class="memitem:ga59949776e069a5af7231ef63156f17cf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__DFSR__BITS.html#ga59949776e069a5af7231ef63156f17cf">DFSR_Domain_Msk</a>   (0xFUL << <a class="el" href="group__CMSIS__DFSR__BITS.html#gac5a7afc43963dbc429792fb5a1569e15">DFSR_Domain_Pos</a>)</td></tr>
633 <tr class="memdesc:ga59949776e069a5af7231ef63156f17cf"><td class="mdescLeft"> </td><td class="mdescRight">DFSR: Domain Mask. <br /></td></tr>
634 <tr class="separator:ga59949776e069a5af7231ef63156f17cf"><td class="memSeparator" colspan="2"> </td></tr>
635 <tr class="memitem:gae5d9bc62e71693bd9dc2a84bb4c82082"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__DFSR__BITS.html#gae5d9bc62e71693bd9dc2a84bb4c82082">DFSR_FS0_Pos</a>   0U</td></tr>
636 <tr class="memdesc:gae5d9bc62e71693bd9dc2a84bb4c82082"><td class="mdescLeft"> </td><td class="mdescRight">DFSR: FS0 Position. <br /></td></tr>
637 <tr class="separator:gae5d9bc62e71693bd9dc2a84bb4c82082"><td class="memSeparator" colspan="2"> </td></tr>
638 <tr class="memitem:ga23b688e81c0378b5cd75acb53896bb5e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__DFSR__BITS.html#ga23b688e81c0378b5cd75acb53896bb5e">DFSR_FS0_Msk</a>   (0xFUL << <a class="el" href="group__CMSIS__DFSR__BITS.html#gae5d9bc62e71693bd9dc2a84bb4c82082">DFSR_FS0_Pos</a>)</td></tr>
639 <tr class="memdesc:ga23b688e81c0378b5cd75acb53896bb5e"><td class="mdescLeft"> </td><td class="mdescRight">DFSR: FS0 Mask. <br /></td></tr>
640 <tr class="separator:ga23b688e81c0378b5cd75acb53896bb5e"><td class="memSeparator" colspan="2"> </td></tr>
641 <tr class="memitem:gacb6fae1908b12c4900e2cdcc320c6c11"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__DFSR__BITS.html#gacb6fae1908b12c4900e2cdcc320c6c11">DFSR_STATUS_Pos</a>   0U</td></tr>
642 <tr class="memdesc:gacb6fae1908b12c4900e2cdcc320c6c11"><td class="mdescLeft"> </td><td class="mdescRight">DFSR: STATUS Position. <br /></td></tr>
643 <tr class="separator:gacb6fae1908b12c4900e2cdcc320c6c11"><td class="memSeparator" colspan="2"> </td></tr>
644 <tr class="memitem:ga7541052737038d737fd9fe00b9815140"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__DFSR__BITS.html#ga7541052737038d737fd9fe00b9815140">DFSR_STATUS_Msk</a>   (0x3FUL << <a class="el" href="group__CMSIS__DFSR__BITS.html#gacb6fae1908b12c4900e2cdcc320c6c11">DFSR_STATUS_Pos</a>)</td></tr>
645 <tr class="memdesc:ga7541052737038d737fd9fe00b9815140"><td class="mdescLeft"> </td><td class="mdescRight">DFSR: STATUS Mask. <br /></td></tr>
646 <tr class="separator:ga7541052737038d737fd9fe00b9815140"><td class="memSeparator" colspan="2"> </td></tr>
647 <tr class="memitem:gafb3d593ec56834b6a265744efd6340a8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__IFSR__BITS.html#gafb3d593ec56834b6a265744efd6340a8">IFSR_ExT_Pos</a>   12U</td></tr>
648 <tr class="memdesc:gafb3d593ec56834b6a265744efd6340a8"><td class="mdescLeft"> </td><td class="mdescRight">IFSR: ExT Position. <br /></td></tr>
649 <tr class="separator:gafb3d593ec56834b6a265744efd6340a8"><td class="memSeparator" colspan="2"> </td></tr>
650 <tr class="memitem:gab0083a1d82b370a7e5208e39267bda22"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__IFSR__BITS.html#gab0083a1d82b370a7e5208e39267bda22">IFSR_ExT_Msk</a>   (1UL << <a class="el" href="group__CMSIS__IFSR__BITS.html#gafb3d593ec56834b6a265744efd6340a8">IFSR_ExT_Pos</a>)</td></tr>
651 <tr class="memdesc:gab0083a1d82b370a7e5208e39267bda22"><td class="mdescLeft"> </td><td class="mdescRight">IFSR: ExT Mask. <br /></td></tr>
652 <tr class="separator:gab0083a1d82b370a7e5208e39267bda22"><td class="memSeparator" colspan="2"> </td></tr>
653 <tr class="memitem:ga9ecf4e123cfee3f0a19898a822fc0f62"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__IFSR__BITS.html#ga9ecf4e123cfee3f0a19898a822fc0f62">IFSR_FS1_Pos</a>   10U</td></tr>
654 <tr class="memdesc:ga9ecf4e123cfee3f0a19898a822fc0f62"><td class="mdescLeft"> </td><td class="mdescRight">IFSR: FS1 Position. <br /></td></tr>
655 <tr class="separator:ga9ecf4e123cfee3f0a19898a822fc0f62"><td class="memSeparator" colspan="2"> </td></tr>
656 <tr class="memitem:ga6fc93a02fbd1c968c70786a84428fca6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__IFSR__BITS.html#ga6fc93a02fbd1c968c70786a84428fca6">IFSR_FS1_Msk</a>   (1UL << <a class="el" href="group__CMSIS__IFSR__BITS.html#ga9ecf4e123cfee3f0a19898a822fc0f62">IFSR_FS1_Pos</a>)</td></tr>
657 <tr class="memdesc:ga6fc93a02fbd1c968c70786a84428fca6"><td class="mdescLeft"> </td><td class="mdescRight">IFSR: FS1 Mask. <br /></td></tr>
658 <tr class="separator:ga6fc93a02fbd1c968c70786a84428fca6"><td class="memSeparator" colspan="2"> </td></tr>
659 <tr class="memitem:gadfd49185eeb102fc69e0a0d28fd2c4a4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__IFSR__BITS.html#gadfd49185eeb102fc69e0a0d28fd2c4a4">IFSR_LPAE_Pos</a>   9U</td></tr>
660 <tr class="memdesc:gadfd49185eeb102fc69e0a0d28fd2c4a4"><td class="mdescLeft"> </td><td class="mdescRight">IFSR: LPAE Position. <br /></td></tr>
661 <tr class="separator:gadfd49185eeb102fc69e0a0d28fd2c4a4"><td class="memSeparator" colspan="2"> </td></tr>
662 <tr class="memitem:ga20639ca32a866d7b021e455b7a5d24c6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__IFSR__BITS.html#ga20639ca32a866d7b021e455b7a5d24c6">IFSR_LPAE_Msk</a>   (0x1UL << <a class="el" href="group__CMSIS__IFSR__BITS.html#gadfd49185eeb102fc69e0a0d28fd2c4a4">IFSR_LPAE_Pos</a>)</td></tr>
663 <tr class="memdesc:ga20639ca32a866d7b021e455b7a5d24c6"><td class="mdescLeft"> </td><td class="mdescRight">IFSR: LPAE Mask. <br /></td></tr>
664 <tr class="separator:ga20639ca32a866d7b021e455b7a5d24c6"><td class="memSeparator" colspan="2"> </td></tr>
665 <tr class="memitem:ga487c29da2f2d648f149c4346f3093f72"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__IFSR__BITS.html#ga487c29da2f2d648f149c4346f3093f72">IFSR_FS0_Pos</a>   0U</td></tr>
666 <tr class="memdesc:ga487c29da2f2d648f149c4346f3093f72"><td class="mdescLeft"> </td><td class="mdescRight">IFSR: FS0 Position. <br /></td></tr>
667 <tr class="separator:ga487c29da2f2d648f149c4346f3093f72"><td class="memSeparator" colspan="2"> </td></tr>
668 <tr class="memitem:gaa17676ff0276b0fe93f92010fe35f6b8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__IFSR__BITS.html#gaa17676ff0276b0fe93f92010fe35f6b8">IFSR_FS0_Msk</a>   (0xFUL << <a class="el" href="group__CMSIS__IFSR__BITS.html#ga487c29da2f2d648f149c4346f3093f72">IFSR_FS0_Pos</a>)</td></tr>
669 <tr class="memdesc:gaa17676ff0276b0fe93f92010fe35f6b8"><td class="mdescLeft"> </td><td class="mdescRight">IFSR: FS0 Mask. <br /></td></tr>
670 <tr class="separator:gaa17676ff0276b0fe93f92010fe35f6b8"><td class="memSeparator" colspan="2"> </td></tr>
671 <tr class="memitem:ga64ec6d573ec1efe1d6c36100ad1cd09d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__IFSR__BITS.html#ga64ec6d573ec1efe1d6c36100ad1cd09d">IFSR_STATUS_Pos</a>   0U</td></tr>
672 <tr class="memdesc:ga64ec6d573ec1efe1d6c36100ad1cd09d"><td class="mdescLeft"> </td><td class="mdescRight">IFSR: STATUS Position. <br /></td></tr>
673 <tr class="separator:ga64ec6d573ec1efe1d6c36100ad1cd09d"><td class="memSeparator" colspan="2"> </td></tr>
674 <tr class="memitem:gaf74c1045a32a2d4de7ea6f0dbcf0d1b3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__IFSR__BITS.html#gaf74c1045a32a2d4de7ea6f0dbcf0d1b3">IFSR_STATUS_Msk</a>   (0x3FUL << <a class="el" href="group__CMSIS__IFSR__BITS.html#ga64ec6d573ec1efe1d6c36100ad1cd09d">IFSR_STATUS_Pos</a>)</td></tr>
675 <tr class="memdesc:gaf74c1045a32a2d4de7ea6f0dbcf0d1b3"><td class="mdescLeft"> </td><td class="mdescRight">IFSR: STATUS Mask. <br /></td></tr>
676 <tr class="separator:gaf74c1045a32a2d4de7ea6f0dbcf0d1b3"><td class="memSeparator" colspan="2"> </td></tr>
677 <tr class="memitem:gaecf0a2cb278bfd27e0da4ab8126d98af"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ISR__BITS.html#gaecf0a2cb278bfd27e0da4ab8126d98af">ISR_A_Pos</a>   13U</td></tr>
678 <tr class="memdesc:gaecf0a2cb278bfd27e0da4ab8126d98af"><td class="mdescLeft"> </td><td class="mdescRight">ISR: A Position. <br /></td></tr>
679 <tr class="separator:gaecf0a2cb278bfd27e0da4ab8126d98af"><td class="memSeparator" colspan="2"> </td></tr>
680 <tr class="memitem:ga8c6d55d243da46ed7ca05c3941316c8d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ISR__BITS.html#ga8c6d55d243da46ed7ca05c3941316c8d">ISR_A_Msk</a>   (1UL << <a class="el" href="group__CMSIS__ISR__BITS.html#gaecf0a2cb278bfd27e0da4ab8126d98af">ISR_A_Pos</a>)</td></tr>
681 <tr class="memdesc:ga8c6d55d243da46ed7ca05c3941316c8d"><td class="mdescLeft"> </td><td class="mdescRight">ISR: A Mask. <br /></td></tr>
682 <tr class="separator:ga8c6d55d243da46ed7ca05c3941316c8d"><td class="memSeparator" colspan="2"> </td></tr>
683 <tr class="memitem:ga9f51d4217c1394e52f5223a6cd382136"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ISR__BITS.html#ga9f51d4217c1394e52f5223a6cd382136">ISR_I_Pos</a>   12U</td></tr>
684 <tr class="memdesc:ga9f51d4217c1394e52f5223a6cd382136"><td class="mdescLeft"> </td><td class="mdescRight">ISR: I Position. <br /></td></tr>
685 <tr class="separator:ga9f51d4217c1394e52f5223a6cd382136"><td class="memSeparator" colspan="2"> </td></tr>
686 <tr class="memitem:ga7b756c9a406d7dd0a86891656908e98c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ISR__BITS.html#ga7b756c9a406d7dd0a86891656908e98c">ISR_I_Msk</a>   (1UL << <a class="el" href="group__CMSIS__ISR__BITS.html#ga9f51d4217c1394e52f5223a6cd382136">ISR_I_Pos</a>)</td></tr>
687 <tr class="memdesc:ga7b756c9a406d7dd0a86891656908e98c"><td class="mdescLeft"> </td><td class="mdescRight">ISR: I Mask. <br /></td></tr>
688 <tr class="separator:ga7b756c9a406d7dd0a86891656908e98c"><td class="memSeparator" colspan="2"> </td></tr>
689 <tr class="memitem:gad8654422bb59e22fb7f1321eeef1b81d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ISR__BITS.html#gad8654422bb59e22fb7f1321eeef1b81d">ISR_F_Pos</a>   11U</td></tr>
690 <tr class="memdesc:gad8654422bb59e22fb7f1321eeef1b81d"><td class="mdescLeft"> </td><td class="mdescRight">ISR: F Position. <br /></td></tr>
691 <tr class="separator:gad8654422bb59e22fb7f1321eeef1b81d"><td class="memSeparator" colspan="2"> </td></tr>
692 <tr class="memitem:gac2efaf413c81afab4265515160f6700c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ISR__BITS.html#gac2efaf413c81afab4265515160f6700c">ISR_F_Msk</a>   (1UL << <a class="el" href="group__CMSIS__ISR__BITS.html#gad8654422bb59e22fb7f1321eeef1b81d">ISR_F_Pos</a>)</td></tr>
693 <tr class="memdesc:gac2efaf413c81afab4265515160f6700c"><td class="mdescLeft"> </td><td class="mdescRight">ISR: F Mask. <br /></td></tr>
694 <tr class="separator:gac2efaf413c81afab4265515160f6700c"><td class="memSeparator" colspan="2"> </td></tr>
695 <tr class="memitem:ga2c014e929b74e6ded5e89a74903ce975"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__DACR__BITS.html#ga2c014e929b74e6ded5e89a74903ce975">DACR_D_Pos_</a>(n)   (2U*n)</td></tr>
696 <tr class="memdesc:ga2c014e929b74e6ded5e89a74903ce975"><td class="mdescLeft"> </td><td class="mdescRight">DACR: Dn Position. <br /></td></tr>
697 <tr class="separator:ga2c014e929b74e6ded5e89a74903ce975"><td class="memSeparator" colspan="2"> </td></tr>
698 <tr class="memitem:ga41b90c8a7338fbe5e5b06be083ba22fe"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__DACR__BITS.html#ga41b90c8a7338fbe5e5b06be083ba22fe">DACR_D_Msk_</a>(n)   (3UL << <a class="el" href="group__CMSIS__DACR__BITS.html#ga2c014e929b74e6ded5e89a74903ce975">DACR_D_Pos_</a>(n))</td></tr>
699 <tr class="memdesc:ga41b90c8a7338fbe5e5b06be083ba22fe"><td class="mdescLeft"> </td><td class="mdescRight">DACR: Dn Mask. <br /></td></tr>
700 <tr class="separator:ga41b90c8a7338fbe5e5b06be083ba22fe"><td class="memSeparator" colspan="2"> </td></tr>
701 <tr class="memitem:ga281ebf97decb4ef4f7b1e5c4285c45ab"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__DACR__Dn.html#ga281ebf97decb4ef4f7b1e5c4285c45ab">DACR_Dn_NOACCESS</a>   0U</td></tr>
702 <tr class="memdesc:ga281ebf97decb4ef4f7b1e5c4285c45ab"><td class="mdescLeft"> </td><td class="mdescRight">DACR Dn field: No access. <br /></td></tr>
703 <tr class="separator:ga281ebf97decb4ef4f7b1e5c4285c45ab"><td class="memSeparator" colspan="2"> </td></tr>
704 <tr class="memitem:gac76e6128758cd64a9fa92487ec49441b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__DACR__Dn.html#gac76e6128758cd64a9fa92487ec49441b">DACR_Dn_CLIENT</a>   1U</td></tr>
705 <tr class="memdesc:gac76e6128758cd64a9fa92487ec49441b"><td class="mdescLeft"> </td><td class="mdescRight">DACR Dn field: Client. <br /></td></tr>
706 <tr class="separator:gac76e6128758cd64a9fa92487ec49441b"><td class="memSeparator" colspan="2"> </td></tr>
707 <tr class="memitem:gabbf27724d67055138bf7abdb651e9732"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__DACR__Dn.html#gabbf27724d67055138bf7abdb651e9732">DACR_Dn_MANAGER</a>   3U</td></tr>
708 <tr class="memdesc:gabbf27724d67055138bf7abdb651e9732"><td class="mdescLeft"> </td><td class="mdescRight">DACR Dn field: Manager. <br /></td></tr>
709 <tr class="separator:gabbf27724d67055138bf7abdb651e9732"><td class="memSeparator" colspan="2"> </td></tr>
710 <tr class="memitem:a286e3b913dbd236c7f48ea70c8821f4e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a286e3b913dbd236c7f48ea70c8821f4e">_VAL2FLD</a>(field, value)   (((uint32_t)(value) << field ## _Pos) & field ## _Msk)</td></tr>
711 <tr class="memdesc:a286e3b913dbd236c7f48ea70c8821f4e"><td class="mdescLeft"> </td><td class="mdescRight">Mask and shift a bit field value for use in a register bit range. <br /></td></tr>
712 <tr class="separator:a286e3b913dbd236c7f48ea70c8821f4e"><td class="memSeparator" colspan="2"> </td></tr>
713 <tr class="memitem:a139b6e261c981f014f386927ca4a8444"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a139b6e261c981f014f386927ca4a8444">_FLD2VAL</a>(field, value)   (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)</td></tr>
714 <tr class="memdesc:a139b6e261c981f014f386927ca4a8444"><td class="mdescLeft"> </td><td class="mdescRight">Mask and shift a register value to extract a bit filed value. <br /></td></tr>
715 <tr class="separator:a139b6e261c981f014f386927ca4a8444"><td class="memSeparator" colspan="2"> </td></tr>
716 <tr class="memitem:ga3b08fba5b9be921c8a971231f75f8764"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__L2__cache__functions.html#ga3b08fba5b9be921c8a971231f75f8764">L2C_310</a>   ((<a class="el" href="structL2C__310__TypeDef.html">L2C_310_TypeDef</a> *)L2C_310_BASE)</td></tr>
717 <tr class="memdesc:ga3b08fba5b9be921c8a971231f75f8764"><td class="mdescLeft"> </td><td class="mdescRight">L2C_310 register set access pointer. <br /></td></tr>
718 <tr class="separator:ga3b08fba5b9be921c8a971231f75f8764"><td class="memSeparator" colspan="2"> </td></tr>
719 <tr class="memitem:ga82e193c0016a9377274756b2673464a6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#ga82e193c0016a9377274756b2673464a6">GICDistributor</a>   ((<a class="el" href="structGICDistributor__Type.html">GICDistributor_Type</a> *) GIC_DISTRIBUTOR_BASE )</td></tr>
720 <tr class="memdesc:ga82e193c0016a9377274756b2673464a6"><td class="mdescLeft"> </td><td class="mdescRight">GIC Distributor register set access pointer. <br /></td></tr>
721 <tr class="separator:ga82e193c0016a9377274756b2673464a6"><td class="memSeparator" colspan="2"> </td></tr>
722 <tr class="memitem:ad5209e6ff9566012bb004b2f09d0b81f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#ad5209e6ff9566012bb004b2f09d0b81f">GICDistributor_CTLR_EnableGrp0_Pos</a>   0U</td></tr>
723 <tr class="separator:ad5209e6ff9566012bb004b2f09d0b81f"><td class="memSeparator" colspan="2"> </td></tr>
724 <tr class="memitem:a753335218b36284c4d01f51469d3a202"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a753335218b36284c4d01f51469d3a202">GICDistributor_CTLR_EnableGrp0_Msk</a>   (0x1U /*<< <a class="el" href="core__ca_8h.html#ad5209e6ff9566012bb004b2f09d0b81f">GICDistributor_CTLR_EnableGrp0_Pos</a>*/)</td></tr>
725 <tr class="separator:a753335218b36284c4d01f51469d3a202"><td class="memSeparator" colspan="2"> </td></tr>
726 <tr class="memitem:a60d6f24a53ad5a82a09caf3e7a0c5526"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a60d6f24a53ad5a82a09caf3e7a0c5526">GICDistributor_CTLR_EnableGrp0</a>(x)   (((uint32_t)(((uint32_t)(x)) /*<< <a class="el" href="core__ca_8h.html#ad5209e6ff9566012bb004b2f09d0b81f">GICDistributor_CTLR_EnableGrp0_Pos</a>*/)) & <a class="el" href="core__ca_8h.html#a753335218b36284c4d01f51469d3a202">GICDistributor_CTLR_EnableGrp0_Msk</a>)</td></tr>
727 <tr class="separator:a60d6f24a53ad5a82a09caf3e7a0c5526"><td class="memSeparator" colspan="2"> </td></tr>
728 <tr class="memitem:aff60a1c3075aa9e91504f9665ad502af"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#aff60a1c3075aa9e91504f9665ad502af">GICDistributor_CTLR_EnableGrp1_Pos</a>   1U</td></tr>
729 <tr class="separator:aff60a1c3075aa9e91504f9665ad502af"><td class="memSeparator" colspan="2"> </td></tr>
730 <tr class="memitem:a2730ca50431156282915c03a16856bb2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a2730ca50431156282915c03a16856bb2">GICDistributor_CTLR_EnableGrp1_Msk</a>   (0x1U << <a class="el" href="core__ca_8h.html#aff60a1c3075aa9e91504f9665ad502af">GICDistributor_CTLR_EnableGrp1_Pos</a>)</td></tr>
731 <tr class="separator:a2730ca50431156282915c03a16856bb2"><td class="memSeparator" colspan="2"> </td></tr>
732 <tr class="memitem:a37803802488aec1ffd64006fa52a7338"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a37803802488aec1ffd64006fa52a7338">GICDistributor_CTLR_EnableGrp1</a>(x)   (((uint32_t)(((uint32_t)(x)) << <a class="el" href="core__ca_8h.html#aff60a1c3075aa9e91504f9665ad502af">GICDistributor_CTLR_EnableGrp1_Pos</a>)) & <a class="el" href="core__ca_8h.html#a2730ca50431156282915c03a16856bb2">GICDistributor_CTLR_EnableGrp1_Msk</a>)</td></tr>
733 <tr class="separator:a37803802488aec1ffd64006fa52a7338"><td class="memSeparator" colspan="2"> </td></tr>
734 <tr class="memitem:a81f2c37daf33d78f1a329a6def5c74ef"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a81f2c37daf33d78f1a329a6def5c74ef">GICDistributor_CTLR_ARE_Pos</a>   4U</td></tr>
735 <tr class="separator:a81f2c37daf33d78f1a329a6def5c74ef"><td class="memSeparator" colspan="2"> </td></tr>
736 <tr class="memitem:a2cd6a6d7ab225eade558f73a5df30414"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a2cd6a6d7ab225eade558f73a5df30414">GICDistributor_CTLR_ARE_Msk</a>   (0x1U << <a class="el" href="core__ca_8h.html#a81f2c37daf33d78f1a329a6def5c74ef">GICDistributor_CTLR_ARE_Pos</a>)</td></tr>
737 <tr class="separator:a2cd6a6d7ab225eade558f73a5df30414"><td class="memSeparator" colspan="2"> </td></tr>
738 <tr class="memitem:aa4fd56267dab50340aba85e9a0a40636"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#aa4fd56267dab50340aba85e9a0a40636">GICDistributor_CTLR_ARE</a>(x)   (((uint32_t)(((uint32_t)(x)) << <a class="el" href="core__ca_8h.html#a81f2c37daf33d78f1a329a6def5c74ef">GICDistributor_CTLR_ARE_Pos</a>)) & <a class="el" href="core__ca_8h.html#a2cd6a6d7ab225eade558f73a5df30414">GICDistributor_CTLR_ARE_Msk</a>)</td></tr>
739 <tr class="separator:aa4fd56267dab50340aba85e9a0a40636"><td class="memSeparator" colspan="2"> </td></tr>
740 <tr class="memitem:a6fe71b805728da3adf3c7e8a4974aa1d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a6fe71b805728da3adf3c7e8a4974aa1d">GICDistributor_CTLR_DC_Pos</a>   6U</td></tr>
741 <tr class="separator:a6fe71b805728da3adf3c7e8a4974aa1d"><td class="memSeparator" colspan="2"> </td></tr>
742 <tr class="memitem:a9d0a78a3b6172c15ad1181ac916f9d39"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a9d0a78a3b6172c15ad1181ac916f9d39">GICDistributor_CTLR_DC_Msk</a>   (0x1U << <a class="el" href="core__ca_8h.html#a6fe71b805728da3adf3c7e8a4974aa1d">GICDistributor_CTLR_DC_Pos</a>)</td></tr>
743 <tr class="separator:a9d0a78a3b6172c15ad1181ac916f9d39"><td class="memSeparator" colspan="2"> </td></tr>
744 <tr class="memitem:ab62c27b779ebcf1b000ffc618e26a701"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#ab62c27b779ebcf1b000ffc618e26a701">GICDistributor_CTLR_DC</a>(x)   (((uint32_t)(((uint32_t)(x)) << <a class="el" href="core__ca_8h.html#a6fe71b805728da3adf3c7e8a4974aa1d">GICDistributor_CTLR_DC_Pos</a>)) & <a class="el" href="core__ca_8h.html#a9d0a78a3b6172c15ad1181ac916f9d39">GICDistributor_CTLR_DC_Msk</a>)</td></tr>
745 <tr class="separator:ab62c27b779ebcf1b000ffc618e26a701"><td class="memSeparator" colspan="2"> </td></tr>
746 <tr class="memitem:a199b879ac14e2c8066e46eb3daa51da3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a199b879ac14e2c8066e46eb3daa51da3">GICDistributor_CTLR_EINWF_Pos</a>   7U</td></tr>
747 <tr class="separator:a199b879ac14e2c8066e46eb3daa51da3"><td class="memSeparator" colspan="2"> </td></tr>
748 <tr class="memitem:a7e984cf330bd971739937957f551c71d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a7e984cf330bd971739937957f551c71d">GICDistributor_CTLR_EINWF_Msk</a>   (0x1U << <a class="el" href="core__ca_8h.html#a199b879ac14e2c8066e46eb3daa51da3">GICDistributor_CTLR_EINWF_Pos</a>)</td></tr>
749 <tr class="separator:a7e984cf330bd971739937957f551c71d"><td class="memSeparator" colspan="2"> </td></tr>
750 <tr class="memitem:a4bbd88a0c4f83a49680cb45fc43fcd8b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a4bbd88a0c4f83a49680cb45fc43fcd8b">GICDistributor_CTLR_EINWF</a>(x)   (((uint32_t)(((uint32_t)(x)) << <a class="el" href="core__ca_8h.html#a199b879ac14e2c8066e46eb3daa51da3">GICDistributor_CTLR_EINWF_Pos</a>)) & <a class="el" href="core__ca_8h.html#a7e984cf330bd971739937957f551c71d">GICDistributor_CTLR_EINWF_Msk</a>)</td></tr>
751 <tr class="separator:a4bbd88a0c4f83a49680cb45fc43fcd8b"><td class="memSeparator" colspan="2"> </td></tr>
752 <tr class="memitem:a4432e051814aedccbc1dc83421b7f386"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a4432e051814aedccbc1dc83421b7f386">GICDistributor_CTLR_RWP_Pos</a>   31U</td></tr>
753 <tr class="separator:a4432e051814aedccbc1dc83421b7f386"><td class="memSeparator" colspan="2"> </td></tr>
754 <tr class="memitem:a0b756d72f4e78786290aff157b3862de"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a0b756d72f4e78786290aff157b3862de">GICDistributor_CTLR_RWP_Msk</a>   (0x1U << <a class="el" href="core__ca_8h.html#a4432e051814aedccbc1dc83421b7f386">GICDistributor_CTLR_RWP_Pos</a>)</td></tr>
755 <tr class="separator:a0b756d72f4e78786290aff157b3862de"><td class="memSeparator" colspan="2"> </td></tr>
756 <tr class="memitem:a41778c5267d09a031f23a13e98c4f9eb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a41778c5267d09a031f23a13e98c4f9eb">GICDistributor_CTLR_RWP</a>(x)   (((uint32_t)(((uint32_t)(x)) << <a class="el" href="core__ca_8h.html#a4432e051814aedccbc1dc83421b7f386">GICDistributor_CTLR_RWP_Pos</a>)) & <a class="el" href="core__ca_8h.html#a0b756d72f4e78786290aff157b3862de">GICDistributor_CTLR_RWP_Msk</a>)</td></tr>
757 <tr class="separator:a41778c5267d09a031f23a13e98c4f9eb"><td class="memSeparator" colspan="2"> </td></tr>
758 <tr class="memitem:afca2b1421a2f881e45cc8925dc22a9bf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#afca2b1421a2f881e45cc8925dc22a9bf">GICDistributor_TYPER_ITLinesNumber_Pos</a>   0U</td></tr>
759 <tr class="separator:afca2b1421a2f881e45cc8925dc22a9bf"><td class="memSeparator" colspan="2"> </td></tr>
760 <tr class="memitem:ad1298a5af707fdc4a9aa5ae7a311f326"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#ad1298a5af707fdc4a9aa5ae7a311f326">GICDistributor_TYPER_ITLinesNumber_Msk</a>   (0x1FU /*<< <a class="el" href="core__ca_8h.html#afca2b1421a2f881e45cc8925dc22a9bf">GICDistributor_TYPER_ITLinesNumber_Pos</a>*/)</td></tr>
761 <tr class="separator:ad1298a5af707fdc4a9aa5ae7a311f326"><td class="memSeparator" colspan="2"> </td></tr>
762 <tr class="memitem:a54970661ead25e94edb829e2e369a665"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a54970661ead25e94edb829e2e369a665">GICDistributor_TYPER_ITLinesNumber</a>(x)   (((uint32_t)(((uint32_t)(x)) /*<< <a class="el" href="core__ca_8h.html#afca2b1421a2f881e45cc8925dc22a9bf">GICDistributor_TYPER_ITLinesNumber_Pos</a>*/)) & GICDistributor_CTLR_ITLinesNumber_Msk)</td></tr>
763 <tr class="separator:a54970661ead25e94edb829e2e369a665"><td class="memSeparator" colspan="2"> </td></tr>
764 <tr class="memitem:a75ed96a2761b78a89e74d324d5584142"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a75ed96a2761b78a89e74d324d5584142">GICDistributor_TYPER_CPUNumber_Pos</a>   5U</td></tr>
765 <tr class="separator:a75ed96a2761b78a89e74d324d5584142"><td class="memSeparator" colspan="2"> </td></tr>
766 <tr class="memitem:a7a299859f30b505dcfe18390acca30ba"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a7a299859f30b505dcfe18390acca30ba">GICDistributor_TYPER_CPUNumber_Msk</a>   (0x7U << <a class="el" href="core__ca_8h.html#a75ed96a2761b78a89e74d324d5584142">GICDistributor_TYPER_CPUNumber_Pos</a>)</td></tr>
767 <tr class="separator:a7a299859f30b505dcfe18390acca30ba"><td class="memSeparator" colspan="2"> </td></tr>
768 <tr class="memitem:a9f26592b70ad969b7ced5cc787d07cdb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a9f26592b70ad969b7ced5cc787d07cdb">GICDistributor_TYPER_CPUNumber</a>(x)   (((uint32_t)(((uint32_t)(x)) << <a class="el" href="core__ca_8h.html#a75ed96a2761b78a89e74d324d5584142">GICDistributor_TYPER_CPUNumber_Pos</a>)) & <a class="el" href="core__ca_8h.html#a7a299859f30b505dcfe18390acca30ba">GICDistributor_TYPER_CPUNumber_Msk</a>)</td></tr>
769 <tr class="separator:a9f26592b70ad969b7ced5cc787d07cdb"><td class="memSeparator" colspan="2"> </td></tr>
770 <tr class="memitem:a23ead3c0a646bec5a3ef37a746bc636b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a23ead3c0a646bec5a3ef37a746bc636b">GICDistributor_TYPER_SecurityExtn_Pos</a>   10U</td></tr>
771 <tr class="separator:a23ead3c0a646bec5a3ef37a746bc636b"><td class="memSeparator" colspan="2"> </td></tr>
772 <tr class="memitem:ae79bcab413026c129df5b1d256439137"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#ae79bcab413026c129df5b1d256439137">GICDistributor_TYPER_SecurityExtn_Msk</a>   (0x1U << <a class="el" href="core__ca_8h.html#a23ead3c0a646bec5a3ef37a746bc636b">GICDistributor_TYPER_SecurityExtn_Pos</a>)</td></tr>
773 <tr class="separator:ae79bcab413026c129df5b1d256439137"><td class="memSeparator" colspan="2"> </td></tr>
774 <tr class="memitem:a0be7c527f9d5caa531c0f14363bf0c95"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a0be7c527f9d5caa531c0f14363bf0c95">GICDistributor_TYPER_SecurityExtn</a>(x)   (((uint32_t)(((uint32_t)(x)) << <a class="el" href="core__ca_8h.html#a23ead3c0a646bec5a3ef37a746bc636b">GICDistributor_TYPER_SecurityExtn_Pos</a>)) & <a class="el" href="core__ca_8h.html#ae79bcab413026c129df5b1d256439137">GICDistributor_TYPER_SecurityExtn_Msk</a>)</td></tr>
775 <tr class="separator:a0be7c527f9d5caa531c0f14363bf0c95"><td class="memSeparator" colspan="2"> </td></tr>
776 <tr class="memitem:a6aa6a3afd05d1e914eca81a0f633c282"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a6aa6a3afd05d1e914eca81a0f633c282">GICDistributor_TYPER_LSPI_Pos</a>   11U</td></tr>
777 <tr class="separator:a6aa6a3afd05d1e914eca81a0f633c282"><td class="memSeparator" colspan="2"> </td></tr>
778 <tr class="memitem:a4a869c9815cef6b3d9d96517d00b0f6d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a4a869c9815cef6b3d9d96517d00b0f6d">GICDistributor_TYPER_LSPI_Msk</a>   (0x1FU << <a class="el" href="core__ca_8h.html#a6aa6a3afd05d1e914eca81a0f633c282">GICDistributor_TYPER_LSPI_Pos</a>)</td></tr>
779 <tr class="separator:a4a869c9815cef6b3d9d96517d00b0f6d"><td class="memSeparator" colspan="2"> </td></tr>
780 <tr class="memitem:a0a58d0f567826aa548949f17474686c0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a0a58d0f567826aa548949f17474686c0">GICDistributor_TYPER_LSPI</a>(x)   (((uint32_t)(((uint32_t)(x)) << <a class="el" href="core__ca_8h.html#a6aa6a3afd05d1e914eca81a0f633c282">GICDistributor_TYPER_LSPI_Pos</a>)) & <a class="el" href="core__ca_8h.html#a4a869c9815cef6b3d9d96517d00b0f6d">GICDistributor_TYPER_LSPI_Msk</a>)</td></tr>
781 <tr class="separator:a0a58d0f567826aa548949f17474686c0"><td class="memSeparator" colspan="2"> </td></tr>
782 <tr class="memitem:ad5cb2a02c6484a02d8599a4eec83cdeb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#ad5cb2a02c6484a02d8599a4eec83cdeb">GICDistributor_IIDR_Implementer_Pos</a>   0U</td></tr>
783 <tr class="separator:ad5cb2a02c6484a02d8599a4eec83cdeb"><td class="memSeparator" colspan="2"> </td></tr>
784 <tr class="memitem:af6cf5679673b9e21f29e9d3e4cf0096f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#af6cf5679673b9e21f29e9d3e4cf0096f">GICDistributor_IIDR_Implementer_Msk</a>   (0xFFFU /*<< <a class="el" href="core__ca_8h.html#ad5cb2a02c6484a02d8599a4eec83cdeb">GICDistributor_IIDR_Implementer_Pos</a>*/)</td></tr>
785 <tr class="separator:af6cf5679673b9e21f29e9d3e4cf0096f"><td class="memSeparator" colspan="2"> </td></tr>
786 <tr class="memitem:a1df00605bff4fecab35a378bcdee277f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a1df00605bff4fecab35a378bcdee277f">GICDistributor_IIDR_Implementer</a>(x)   (((uint32_t)(((uint32_t)(x)) /*<< <a class="el" href="core__ca_8h.html#ad5cb2a02c6484a02d8599a4eec83cdeb">GICDistributor_IIDR_Implementer_Pos</a>*/)) & <a class="el" href="core__ca_8h.html#af6cf5679673b9e21f29e9d3e4cf0096f">GICDistributor_IIDR_Implementer_Msk</a>)</td></tr>
787 <tr class="separator:a1df00605bff4fecab35a378bcdee277f"><td class="memSeparator" colspan="2"> </td></tr>
788 <tr class="memitem:af12891c46bd7555919f5df7771eadb09"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#af12891c46bd7555919f5df7771eadb09">GICDistributor_IIDR_Revision_Pos</a>   12U</td></tr>
789 <tr class="separator:af12891c46bd7555919f5df7771eadb09"><td class="memSeparator" colspan="2"> </td></tr>
790 <tr class="memitem:aaa5816799e45c7aaf832c847c4b333ba"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#aaa5816799e45c7aaf832c847c4b333ba">GICDistributor_IIDR_Revision_Msk</a>   (0xFU << <a class="el" href="core__ca_8h.html#af12891c46bd7555919f5df7771eadb09">GICDistributor_IIDR_Revision_Pos</a>)</td></tr>
791 <tr class="separator:aaa5816799e45c7aaf832c847c4b333ba"><td class="memSeparator" colspan="2"> </td></tr>
792 <tr class="memitem:ab7bc3dde66b114b7d20c672e108d9386"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#ab7bc3dde66b114b7d20c672e108d9386">GICDistributor_IIDR_Revision</a>(x)   (((uint32_t)(((uint32_t)(x)) << <a class="el" href="core__ca_8h.html#af12891c46bd7555919f5df7771eadb09">GICDistributor_IIDR_Revision_Pos</a>)) & <a class="el" href="core__ca_8h.html#aaa5816799e45c7aaf832c847c4b333ba">GICDistributor_IIDR_Revision_Msk</a>)</td></tr>
793 <tr class="separator:ab7bc3dde66b114b7d20c672e108d9386"><td class="memSeparator" colspan="2"> </td></tr>
794 <tr class="memitem:ab7a79131c7af76dba9bbecd15d4e2117"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#ab7a79131c7af76dba9bbecd15d4e2117">GICDistributor_IIDR_Variant_Pos</a>   16U</td></tr>
795 <tr class="separator:ab7a79131c7af76dba9bbecd15d4e2117"><td class="memSeparator" colspan="2"> </td></tr>
796 <tr class="memitem:ab0d681a61eb8013e4216392306d6c70b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#ab0d681a61eb8013e4216392306d6c70b">GICDistributor_IIDR_Variant_Msk</a>   (0xFU << <a class="el" href="core__ca_8h.html#ab7a79131c7af76dba9bbecd15d4e2117">GICDistributor_IIDR_Variant_Pos</a>)</td></tr>
797 <tr class="separator:ab0d681a61eb8013e4216392306d6c70b"><td class="memSeparator" colspan="2"> </td></tr>
798 <tr class="memitem:a8380fa71d0da5db1773adacfade1a07b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a8380fa71d0da5db1773adacfade1a07b">GICDistributor_IIDR_Variant</a>(x)   (((uint32_t)(((uint32_t)(x)) << <a class="el" href="core__ca_8h.html#ab7a79131c7af76dba9bbecd15d4e2117">GICDistributor_IIDR_Variant_Pos</a>)) & <a class="el" href="core__ca_8h.html#ab0d681a61eb8013e4216392306d6c70b">GICDistributor_IIDR_Variant_Msk</a>)</td></tr>
799 <tr class="separator:a8380fa71d0da5db1773adacfade1a07b"><td class="memSeparator" colspan="2"> </td></tr>
800 <tr class="memitem:ab833f27680c28ec66b0fb9c00765b941"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#ab833f27680c28ec66b0fb9c00765b941">GICDistributor_IIDR_ProductID_Pos</a>   24U</td></tr>
801 <tr class="separator:ab833f27680c28ec66b0fb9c00765b941"><td class="memSeparator" colspan="2"> </td></tr>
802 <tr class="memitem:a8e6d7553302e4326de3b89cc38e7538f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a8e6d7553302e4326de3b89cc38e7538f">GICDistributor_IIDR_ProductID_Msk</a>   (0xFFU << <a class="el" href="core__ca_8h.html#ab833f27680c28ec66b0fb9c00765b941">GICDistributor_IIDR_ProductID_Pos</a>)</td></tr>
803 <tr class="separator:a8e6d7553302e4326de3b89cc38e7538f"><td class="memSeparator" colspan="2"> </td></tr>
804 <tr class="memitem:a3ef98229da161c0438791171919222c2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a3ef98229da161c0438791171919222c2">GICDistributor_IIDR_ProductID</a>(x)   (((uint32_t)(((uint32_t)(x)) << <a class="el" href="core__ca_8h.html#ab833f27680c28ec66b0fb9c00765b941">GICDistributor_IIDR_ProductID_Pos</a>)) & <a class="el" href="core__ca_8h.html#a8e6d7553302e4326de3b89cc38e7538f">GICDistributor_IIDR_ProductID_Msk</a>)</td></tr>
805 <tr class="separator:a3ef98229da161c0438791171919222c2"><td class="memSeparator" colspan="2"> </td></tr>
806 <tr class="memitem:a6b3d0d43717045928b96ce9c8e76493d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a6b3d0d43717045928b96ce9c8e76493d">GICDistributor_STATUSR_RRD_Pos</a>   0U</td></tr>
807 <tr class="separator:a6b3d0d43717045928b96ce9c8e76493d"><td class="memSeparator" colspan="2"> </td></tr>
808 <tr class="memitem:aa8bef863ded4eccc540df63bb9409b66"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#aa8bef863ded4eccc540df63bb9409b66">GICDistributor_STATUSR_RRD_Msk</a>   (0x1U /*<< <a class="el" href="core__ca_8h.html#a6b3d0d43717045928b96ce9c8e76493d">GICDistributor_STATUSR_RRD_Pos</a>*/)</td></tr>
809 <tr class="separator:aa8bef863ded4eccc540df63bb9409b66"><td class="memSeparator" colspan="2"> </td></tr>
810 <tr class="memitem:a44b7dd5f0ba7bc48c66c2b09ec38f3b9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a44b7dd5f0ba7bc48c66c2b09ec38f3b9">GICDistributor_STATUSR_RRD</a>(x)   (((uint32_t)(((uint32_t)(x)) /*<< <a class="el" href="core__ca_8h.html#a6b3d0d43717045928b96ce9c8e76493d">GICDistributor_STATUSR_RRD_Pos</a>*/)) & <a class="el" href="core__ca_8h.html#aa8bef863ded4eccc540df63bb9409b66">GICDistributor_STATUSR_RRD_Msk</a>)</td></tr>
811 <tr class="separator:a44b7dd5f0ba7bc48c66c2b09ec38f3b9"><td class="memSeparator" colspan="2"> </td></tr>
812 <tr class="memitem:a445ce8828d51d1e51fd2ee7220d80ef7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a445ce8828d51d1e51fd2ee7220d80ef7">GICDistributor_STATUSR_WRD_Pos</a>   1U</td></tr>
813 <tr class="separator:a445ce8828d51d1e51fd2ee7220d80ef7"><td class="memSeparator" colspan="2"> </td></tr>
814 <tr class="memitem:a4918f67f256f60199aab4aea51641ff4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a4918f67f256f60199aab4aea51641ff4">GICDistributor_STATUSR_WRD_Msk</a>   (0x1U << <a class="el" href="core__ca_8h.html#a445ce8828d51d1e51fd2ee7220d80ef7">GICDistributor_STATUSR_WRD_Pos</a>)</td></tr>
815 <tr class="separator:a4918f67f256f60199aab4aea51641ff4"><td class="memSeparator" colspan="2"> </td></tr>
816 <tr class="memitem:a97af8de41d50552933bde33d37b45501"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a97af8de41d50552933bde33d37b45501">GICDistributor_STATUSR_WRD</a>(x)   (((uint32_t)(((uint32_t)(x)) << <a class="el" href="core__ca_8h.html#a445ce8828d51d1e51fd2ee7220d80ef7">GICDistributor_STATUSR_WRD_Pos</a>)) & <a class="el" href="core__ca_8h.html#a4918f67f256f60199aab4aea51641ff4">GICDistributor_STATUSR_WRD_Msk</a>)</td></tr>
817 <tr class="separator:a97af8de41d50552933bde33d37b45501"><td class="memSeparator" colspan="2"> </td></tr>
818 <tr class="memitem:a770b3e754d28bfe33264925f982601d3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a770b3e754d28bfe33264925f982601d3">GICDistributor_STATUSR_RWOD_Pos</a>   2U</td></tr>
819 <tr class="separator:a770b3e754d28bfe33264925f982601d3"><td class="memSeparator" colspan="2"> </td></tr>
820 <tr class="memitem:aa118bf40ce6c4afcfe0d7f5d1962e3d9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#aa118bf40ce6c4afcfe0d7f5d1962e3d9">GICDistributor_STATUSR_RWOD_Msk</a>   (0x1U << <a class="el" href="core__ca_8h.html#a770b3e754d28bfe33264925f982601d3">GICDistributor_STATUSR_RWOD_Pos</a>)</td></tr>
821 <tr class="separator:aa118bf40ce6c4afcfe0d7f5d1962e3d9"><td class="memSeparator" colspan="2"> </td></tr>
822 <tr class="memitem:ad5e6e2461927af5b913ae150531cba55"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#ad5e6e2461927af5b913ae150531cba55">GICDistributor_STATUSR_RWOD</a>(x)   (((uint32_t)(((uint32_t)(x)) << <a class="el" href="core__ca_8h.html#a770b3e754d28bfe33264925f982601d3">GICDistributor_STATUSR_RWOD_Pos</a>)) & <a class="el" href="core__ca_8h.html#aa118bf40ce6c4afcfe0d7f5d1962e3d9">GICDistributor_STATUSR_RWOD_Msk</a>)</td></tr>
823 <tr class="separator:ad5e6e2461927af5b913ae150531cba55"><td class="memSeparator" colspan="2"> </td></tr>
824 <tr class="memitem:aa10fb1346557f4a47cba190a8e1e5276"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#aa10fb1346557f4a47cba190a8e1e5276">GICDistributor_STATUSR_WROD_Pos</a>   3U</td></tr>
825 <tr class="separator:aa10fb1346557f4a47cba190a8e1e5276"><td class="memSeparator" colspan="2"> </td></tr>
826 <tr class="memitem:a3ebeda889d892922823097d05234498b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a3ebeda889d892922823097d05234498b">GICDistributor_STATUSR_WROD_Msk</a>   (0x1U << <a class="el" href="core__ca_8h.html#aa10fb1346557f4a47cba190a8e1e5276">GICDistributor_STATUSR_WROD_Pos</a>)</td></tr>
827 <tr class="separator:a3ebeda889d892922823097d05234498b"><td class="memSeparator" colspan="2"> </td></tr>
828 <tr class="memitem:a83dfa2f07a25812301dceeac8632257e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a83dfa2f07a25812301dceeac8632257e">GICDistributor_STATUSR_WROD</a>(x)   (((uint32_t)(((uint32_t)(x)) << <a class="el" href="core__ca_8h.html#aa10fb1346557f4a47cba190a8e1e5276">GICDistributor_STATUSR_WROD_Pos</a>)) & <a class="el" href="core__ca_8h.html#a3ebeda889d892922823097d05234498b">GICDistributor_STATUSR_WROD_Msk</a>)</td></tr>
829 <tr class="separator:a83dfa2f07a25812301dceeac8632257e"><td class="memSeparator" colspan="2"> </td></tr>
830 <tr class="memitem:aa934ee036ef12831d8af1045d89d5098"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#aa934ee036ef12831d8af1045d89d5098">GICDistributor_SETSPI_NSR_INTID_Pos</a>   0U</td></tr>
831 <tr class="separator:aa934ee036ef12831d8af1045d89d5098"><td class="memSeparator" colspan="2"> </td></tr>
832 <tr class="memitem:ab953cf9ca1e33ad5711f00bac17a70e2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#ab953cf9ca1e33ad5711f00bac17a70e2">GICDistributor_SETSPI_NSR_INTID_Msk</a>   (0x3FFU /*<< <a class="el" href="core__ca_8h.html#aa934ee036ef12831d8af1045d89d5098">GICDistributor_SETSPI_NSR_INTID_Pos</a>*/)</td></tr>
833 <tr class="separator:ab953cf9ca1e33ad5711f00bac17a70e2"><td class="memSeparator" colspan="2"> </td></tr>
834 <tr class="memitem:ad32219138870f7dd63a0bc211f7fcc58"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#ad32219138870f7dd63a0bc211f7fcc58">GICDistributor_SETSPI_NSR_INTID</a>(x)   (((uint32_t)(((uint32_t)(x)) /*<< <a class="el" href="core__ca_8h.html#aa934ee036ef12831d8af1045d89d5098">GICDistributor_SETSPI_NSR_INTID_Pos</a>*/)) & <a class="el" href="core__ca_8h.html#ab953cf9ca1e33ad5711f00bac17a70e2">GICDistributor_SETSPI_NSR_INTID_Msk</a>)</td></tr>
835 <tr class="separator:ad32219138870f7dd63a0bc211f7fcc58"><td class="memSeparator" colspan="2"> </td></tr>
836 <tr class="memitem:a9a22d0d7c3a9201db3450b6e6f903990"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a9a22d0d7c3a9201db3450b6e6f903990">GICDistributor_CLRSPI_NSR_INTID_Pos</a>   0U</td></tr>
837 <tr class="separator:a9a22d0d7c3a9201db3450b6e6f903990"><td class="memSeparator" colspan="2"> </td></tr>
838 <tr class="memitem:a7bb3492a25e6309a18464dca7135e58f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a7bb3492a25e6309a18464dca7135e58f">GICDistributor_CLRSPI_NSR_INTID_Msk</a>   (0x3FFU /*<< <a class="el" href="core__ca_8h.html#a9a22d0d7c3a9201db3450b6e6f903990">GICDistributor_CLRSPI_NSR_INTID_Pos</a>*/)</td></tr>
839 <tr class="separator:a7bb3492a25e6309a18464dca7135e58f"><td class="memSeparator" colspan="2"> </td></tr>
840 <tr class="memitem:aeb357573357d37d881975de18f0e0b95"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#aeb357573357d37d881975de18f0e0b95">GICDistributor_CLRSPI_NSR_INTID</a>(x)   (((uint32_t)(((uint32_t)(x)) /*<< <a class="el" href="core__ca_8h.html#a9a22d0d7c3a9201db3450b6e6f903990">GICDistributor_CLRSPI_NSR_INTID_Pos</a>*/)) & <a class="el" href="core__ca_8h.html#a7bb3492a25e6309a18464dca7135e58f">GICDistributor_CLRSPI_NSR_INTID_Msk</a>)</td></tr>
841 <tr class="separator:aeb357573357d37d881975de18f0e0b95"><td class="memSeparator" colspan="2"> </td></tr>
842 <tr class="memitem:ae77f1bf2954b62ee958857a8da665c08"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#ae77f1bf2954b62ee958857a8da665c08">GICDistributor_SETSPI_SR_INTID_Pos</a>   0U</td></tr>
843 <tr class="separator:ae77f1bf2954b62ee958857a8da665c08"><td class="memSeparator" colspan="2"> </td></tr>
844 <tr class="memitem:aa6d470044e50683356814e998a886c50"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#aa6d470044e50683356814e998a886c50">GICDistributor_SETSPI_SR_INTID_Msk</a>   (0x3FFU /*<< <a class="el" href="core__ca_8h.html#ae77f1bf2954b62ee958857a8da665c08">GICDistributor_SETSPI_SR_INTID_Pos</a>*/)</td></tr>
845 <tr class="separator:aa6d470044e50683356814e998a886c50"><td class="memSeparator" colspan="2"> </td></tr>
846 <tr class="memitem:aa54f4703869cef1a5cba0b0e0c45d120"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#aa54f4703869cef1a5cba0b0e0c45d120">GICDistributor_SETSPI_SR_INTID</a>(x)   (((uint32_t)(((uint32_t)(x)) /*<< <a class="el" href="core__ca_8h.html#ae77f1bf2954b62ee958857a8da665c08">GICDistributor_SETSPI_SR_INTID_Pos</a>*/)) & <a class="el" href="core__ca_8h.html#aa6d470044e50683356814e998a886c50">GICDistributor_SETSPI_SR_INTID_Msk</a>)</td></tr>
847 <tr class="separator:aa54f4703869cef1a5cba0b0e0c45d120"><td class="memSeparator" colspan="2"> </td></tr>
848 <tr class="memitem:a7d6ddee654f6cdbba19948b3cc160ba5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a7d6ddee654f6cdbba19948b3cc160ba5">GICDistributor_CLRSPI_SR_INTID_Pos</a>   0U</td></tr>
849 <tr class="separator:a7d6ddee654f6cdbba19948b3cc160ba5"><td class="memSeparator" colspan="2"> </td></tr>
850 <tr class="memitem:a8ef78b7979f3b007c9fba55faae15f78"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a8ef78b7979f3b007c9fba55faae15f78">GICDistributor_CLRSPI_SR_INTID_Msk</a>   (0x3FFU /*<< <a class="el" href="core__ca_8h.html#a7d6ddee654f6cdbba19948b3cc160ba5">GICDistributor_CLRSPI_SR_INTID_Pos</a>*/)</td></tr>
851 <tr class="separator:a8ef78b7979f3b007c9fba55faae15f78"><td class="memSeparator" colspan="2"> </td></tr>
852 <tr class="memitem:a75c8afc3bee11acef651f89458683d50"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a75c8afc3bee11acef651f89458683d50">GICDistributor_CLRSPI_SR_INTID</a>(x)   (((uint32_t)(((uint32_t)(x)) /*<< <a class="el" href="core__ca_8h.html#a7d6ddee654f6cdbba19948b3cc160ba5">GICDistributor_CLRSPI_SR_INTID_Pos</a>*/)) & <a class="el" href="core__ca_8h.html#a8ef78b7979f3b007c9fba55faae15f78">GICDistributor_CLRSPI_SR_INTID_Msk</a>)</td></tr>
853 <tr class="separator:a75c8afc3bee11acef651f89458683d50"><td class="memSeparator" colspan="2"> </td></tr>
854 <tr class="memitem:a28353192a0298bd7f35648df54839029"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a28353192a0298bd7f35648df54839029">GICDistributor_ITARGETSR_CPU0_Pos</a>   0U</td></tr>
855 <tr class="separator:a28353192a0298bd7f35648df54839029"><td class="memSeparator" colspan="2"> </td></tr>
856 <tr class="memitem:a56fcab6b4afdd0998d8cbd351b060a42"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a56fcab6b4afdd0998d8cbd351b060a42">GICDistributor_ITARGETSR_CPU0_Msk</a>   (0x1U /*<< <a class="el" href="core__ca_8h.html#a28353192a0298bd7f35648df54839029">GICDistributor_ITARGETSR_CPU0_Pos</a>*/)</td></tr>
857 <tr class="separator:a56fcab6b4afdd0998d8cbd351b060a42"><td class="memSeparator" colspan="2"> </td></tr>
858 <tr class="memitem:a276be33ef8d9aeecda6e1290400b0a2e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a276be33ef8d9aeecda6e1290400b0a2e">GICDistributor_ITARGETSR_CPU0</a>(x)   (((uint8_t)(((uint8_t)(x)) /*<< <a class="el" href="core__ca_8h.html#a28353192a0298bd7f35648df54839029">GICDistributor_ITARGETSR_CPU0_Pos</a>*/)) & <a class="el" href="core__ca_8h.html#a56fcab6b4afdd0998d8cbd351b060a42">GICDistributor_ITARGETSR_CPU0_Msk</a>)</td></tr>
859 <tr class="separator:a276be33ef8d9aeecda6e1290400b0a2e"><td class="memSeparator" colspan="2"> </td></tr>
860 <tr class="memitem:ac2d3fd8843c99b7b634e390e756e2bbd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#ac2d3fd8843c99b7b634e390e756e2bbd">GICDistributor_ITARGETSR_CPU1_Pos</a>   1U</td></tr>
861 <tr class="separator:ac2d3fd8843c99b7b634e390e756e2bbd"><td class="memSeparator" colspan="2"> </td></tr>
862 <tr class="memitem:a02f1660e91258f435ad519c577b43014"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a02f1660e91258f435ad519c577b43014">GICDistributor_ITARGETSR_CPU1_Msk</a>   (0x1U << <a class="el" href="core__ca_8h.html#ac2d3fd8843c99b7b634e390e756e2bbd">GICDistributor_ITARGETSR_CPU1_Pos</a>)</td></tr>
863 <tr class="separator:a02f1660e91258f435ad519c577b43014"><td class="memSeparator" colspan="2"> </td></tr>
864 <tr class="memitem:a683207ddcab7bc574b8bb3cb2f12eed8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a683207ddcab7bc574b8bb3cb2f12eed8">GICDistributor_ITARGETSR_CPU1</a>(x)   (((uint8_t)(((uint8_t)(x)) << <a class="el" href="core__ca_8h.html#ac2d3fd8843c99b7b634e390e756e2bbd">GICDistributor_ITARGETSR_CPU1_Pos</a>)) & <a class="el" href="core__ca_8h.html#a02f1660e91258f435ad519c577b43014">GICDistributor_ITARGETSR_CPU1_Msk</a>)</td></tr>
865 <tr class="separator:a683207ddcab7bc574b8bb3cb2f12eed8"><td class="memSeparator" colspan="2"> </td></tr>
866 <tr class="memitem:a8a9407956d72af2b4b697a5184a0fae0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a8a9407956d72af2b4b697a5184a0fae0">GICDistributor_ITARGETSR_CPU2_Pos</a>   2U</td></tr>
867 <tr class="separator:a8a9407956d72af2b4b697a5184a0fae0"><td class="memSeparator" colspan="2"> </td></tr>
868 <tr class="memitem:ad50526ede6080c3df2af103d43ec969a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#ad50526ede6080c3df2af103d43ec969a">GICDistributor_ITARGETSR_CPU2_Msk</a>   (0x1U << <a class="el" href="core__ca_8h.html#a8a9407956d72af2b4b697a5184a0fae0">GICDistributor_ITARGETSR_CPU2_Pos</a>)</td></tr>
869 <tr class="separator:ad50526ede6080c3df2af103d43ec969a"><td class="memSeparator" colspan="2"> </td></tr>
870 <tr class="memitem:a04bb8c24598b4b9720e1408264129400"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a04bb8c24598b4b9720e1408264129400">GICDistributor_ITARGETSR_CPU2</a>(x)   (((uint8_t)(((uint8_t)(x)) << <a class="el" href="core__ca_8h.html#a8a9407956d72af2b4b697a5184a0fae0">GICDistributor_ITARGETSR_CPU2_Pos</a>)) & <a class="el" href="core__ca_8h.html#ad50526ede6080c3df2af103d43ec969a">GICDistributor_ITARGETSR_CPU2_Msk</a>)</td></tr>
871 <tr class="separator:a04bb8c24598b4b9720e1408264129400"><td class="memSeparator" colspan="2"> </td></tr>
872 <tr class="memitem:a26635639563b054f6cd5a6862a2f2a61"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a26635639563b054f6cd5a6862a2f2a61">GICDistributor_ITARGETSR_CPU3_Pos</a>   3U</td></tr>
873 <tr class="separator:a26635639563b054f6cd5a6862a2f2a61"><td class="memSeparator" colspan="2"> </td></tr>
874 <tr class="memitem:ac15f36682e23f172e51fded30108d2f6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#ac15f36682e23f172e51fded30108d2f6">GICDistributor_ITARGETSR_CPU3_Msk</a>   (0x1U << <a class="el" href="core__ca_8h.html#a26635639563b054f6cd5a6862a2f2a61">GICDistributor_ITARGETSR_CPU3_Pos</a>)</td></tr>
875 <tr class="separator:ac15f36682e23f172e51fded30108d2f6"><td class="memSeparator" colspan="2"> </td></tr>
876 <tr class="memitem:a2724b8078bf97c07e50c9a8919024cf6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a2724b8078bf97c07e50c9a8919024cf6">GICDistributor_ITARGETSR_CPU3</a>(x)   (((uint8_t)(((uint8_t)(x)) << <a class="el" href="core__ca_8h.html#a26635639563b054f6cd5a6862a2f2a61">GICDistributor_ITARGETSR_CPU3_Pos</a>)) & <a class="el" href="core__ca_8h.html#ac15f36682e23f172e51fded30108d2f6">GICDistributor_ITARGETSR_CPU3_Msk</a>)</td></tr>
877 <tr class="separator:a2724b8078bf97c07e50c9a8919024cf6"><td class="memSeparator" colspan="2"> </td></tr>
878 <tr class="memitem:ae25a0b0c07d793d2d8ad4685f5d9acc2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#ae25a0b0c07d793d2d8ad4685f5d9acc2">GICDistributor_ITARGETSR_CPU4_Pos</a>   4U</td></tr>
879 <tr class="separator:ae25a0b0c07d793d2d8ad4685f5d9acc2"><td class="memSeparator" colspan="2"> </td></tr>
880 <tr class="memitem:a18a2390a599afb731cef504dc79d1505"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a18a2390a599afb731cef504dc79d1505">GICDistributor_ITARGETSR_CPU4_Msk</a>   (0x1U << <a class="el" href="core__ca_8h.html#ae25a0b0c07d793d2d8ad4685f5d9acc2">GICDistributor_ITARGETSR_CPU4_Pos</a>)</td></tr>
881 <tr class="separator:a18a2390a599afb731cef504dc79d1505"><td class="memSeparator" colspan="2"> </td></tr>
882 <tr class="memitem:aaffea378b3e1c322658d5605e1c109e6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#aaffea378b3e1c322658d5605e1c109e6">GICDistributor_ITARGETSR_CPU4</a>(x)   (((uint8_t)(((uint8_t)(x)) << <a class="el" href="core__ca_8h.html#ae25a0b0c07d793d2d8ad4685f5d9acc2">GICDistributor_ITARGETSR_CPU4_Pos</a>)) & <a class="el" href="core__ca_8h.html#a18a2390a599afb731cef504dc79d1505">GICDistributor_ITARGETSR_CPU4_Msk</a>)</td></tr>
883 <tr class="separator:aaffea378b3e1c322658d5605e1c109e6"><td class="memSeparator" colspan="2"> </td></tr>
884 <tr class="memitem:acae2c190f3999809e0d916b77d8bf95a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#acae2c190f3999809e0d916b77d8bf95a">GICDistributor_ITARGETSR_CPU5_Pos</a>   5U</td></tr>
885 <tr class="separator:acae2c190f3999809e0d916b77d8bf95a"><td class="memSeparator" colspan="2"> </td></tr>
886 <tr class="memitem:ac814c6b67a080ea70ef020c3a21b0e20"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#ac814c6b67a080ea70ef020c3a21b0e20">GICDistributor_ITARGETSR_CPU5_Msk</a>   (0x1U << <a class="el" href="core__ca_8h.html#acae2c190f3999809e0d916b77d8bf95a">GICDistributor_ITARGETSR_CPU5_Pos</a>)</td></tr>
887 <tr class="separator:ac814c6b67a080ea70ef020c3a21b0e20"><td class="memSeparator" colspan="2"> </td></tr>
888 <tr class="memitem:ac99060fe12c7fd70e3c3c8452daa5302"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#ac99060fe12c7fd70e3c3c8452daa5302">GICDistributor_ITARGETSR_CPU5</a>(x)   (((uint8_t)(((uint8_t)(x)) << <a class="el" href="core__ca_8h.html#acae2c190f3999809e0d916b77d8bf95a">GICDistributor_ITARGETSR_CPU5_Pos</a>)) & <a class="el" href="core__ca_8h.html#ac814c6b67a080ea70ef020c3a21b0e20">GICDistributor_ITARGETSR_CPU5_Msk</a>)</td></tr>
889 <tr class="separator:ac99060fe12c7fd70e3c3c8452daa5302"><td class="memSeparator" colspan="2"> </td></tr>
890 <tr class="memitem:aab6a80042fd995785ff18e4f996716c2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#aab6a80042fd995785ff18e4f996716c2">GICDistributor_ITARGETSR_CPU6_Pos</a>   6U</td></tr>
891 <tr class="separator:aab6a80042fd995785ff18e4f996716c2"><td class="memSeparator" colspan="2"> </td></tr>
892 <tr class="memitem:a0d9fa1b53101815feaebc4a5943e1d4c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a0d9fa1b53101815feaebc4a5943e1d4c">GICDistributor_ITARGETSR_CPU6_Msk</a>   (0x1U << <a class="el" href="core__ca_8h.html#aab6a80042fd995785ff18e4f996716c2">GICDistributor_ITARGETSR_CPU6_Pos</a>)</td></tr>
893 <tr class="separator:a0d9fa1b53101815feaebc4a5943e1d4c"><td class="memSeparator" colspan="2"> </td></tr>
894 <tr class="memitem:a48202cd0ad1df93721da27716f35ab99"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a48202cd0ad1df93721da27716f35ab99">GICDistributor_ITARGETSR_CPU6</a>(x)   (((uint8_t)(((uint8_t)(x)) << <a class="el" href="core__ca_8h.html#aab6a80042fd995785ff18e4f996716c2">GICDistributor_ITARGETSR_CPU6_Pos</a>)) & <a class="el" href="core__ca_8h.html#a0d9fa1b53101815feaebc4a5943e1d4c">GICDistributor_ITARGETSR_CPU6_Msk</a>)</td></tr>
895 <tr class="separator:a48202cd0ad1df93721da27716f35ab99"><td class="memSeparator" colspan="2"> </td></tr>
896 <tr class="memitem:ab8de7f026a09862a180421168128db75"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#ab8de7f026a09862a180421168128db75">GICDistributor_ITARGETSR_CPU7_Pos</a>   7U</td></tr>
897 <tr class="separator:ab8de7f026a09862a180421168128db75"><td class="memSeparator" colspan="2"> </td></tr>
898 <tr class="memitem:aefbae4dd8686f09a13ac74db57d27a6f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#aefbae4dd8686f09a13ac74db57d27a6f">GICDistributor_ITARGETSR_CPU7_Msk</a>   (0x1U << <a class="el" href="core__ca_8h.html#ab8de7f026a09862a180421168128db75">GICDistributor_ITARGETSR_CPU7_Pos</a>)</td></tr>
899 <tr class="separator:aefbae4dd8686f09a13ac74db57d27a6f"><td class="memSeparator" colspan="2"> </td></tr>
900 <tr class="memitem:aa1026673480067f6c33069bf555bee9a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#aa1026673480067f6c33069bf555bee9a">GICDistributor_ITARGETSR_CPU7</a>(x)   (((uint8_t)(((uint8_t)(x)) << <a class="el" href="core__ca_8h.html#ab8de7f026a09862a180421168128db75">GICDistributor_ITARGETSR_CPU7_Pos</a>)) & <a class="el" href="core__ca_8h.html#aefbae4dd8686f09a13ac74db57d27a6f">GICDistributor_ITARGETSR_CPU7_Msk</a>)</td></tr>
901 <tr class="separator:aa1026673480067f6c33069bf555bee9a"><td class="memSeparator" colspan="2"> </td></tr>
902 <tr class="memitem:ae1dd9d68a6bf8a6c9025ae7279fedae6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#ae1dd9d68a6bf8a6c9025ae7279fedae6">GICDistributor_SGIR_INTID_Pos</a>   0U</td></tr>
903 <tr class="separator:ae1dd9d68a6bf8a6c9025ae7279fedae6"><td class="memSeparator" colspan="2"> </td></tr>
904 <tr class="memitem:aeb93cabf664375c4213402cbc85d2c44"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#aeb93cabf664375c4213402cbc85d2c44">GICDistributor_SGIR_INTID_Msk</a>   (0x7U /*<< <a class="el" href="core__ca_8h.html#ae1dd9d68a6bf8a6c9025ae7279fedae6">GICDistributor_SGIR_INTID_Pos</a>*/)</td></tr>
905 <tr class="separator:aeb93cabf664375c4213402cbc85d2c44"><td class="memSeparator" colspan="2"> </td></tr>
906 <tr class="memitem:aa45326a8811c425d0ea6bedd1936444c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#aa45326a8811c425d0ea6bedd1936444c">GICDistributor_SGIR_INTID</a>(x)   (((uint32_t)(((uint32_t)(x)) /*<< <a class="el" href="core__ca_8h.html#ae1dd9d68a6bf8a6c9025ae7279fedae6">GICDistributor_SGIR_INTID_Pos</a>*/)) & <a class="el" href="core__ca_8h.html#aeb93cabf664375c4213402cbc85d2c44">GICDistributor_SGIR_INTID_Msk</a>)</td></tr>
907 <tr class="separator:aa45326a8811c425d0ea6bedd1936444c"><td class="memSeparator" colspan="2"> </td></tr>
908 <tr class="memitem:a24cd5de9c2639ea81ef62500a3cbe8ad"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a24cd5de9c2639ea81ef62500a3cbe8ad">GICDistributor_SGIR_NSATT_Pos</a>   15U</td></tr>
909 <tr class="separator:a24cd5de9c2639ea81ef62500a3cbe8ad"><td class="memSeparator" colspan="2"> </td></tr>
910 <tr class="memitem:a99afa06bfe662185b91c004719979f4f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a99afa06bfe662185b91c004719979f4f">GICDistributor_SGIR_NSATT_Msk</a>   (0x1U << <a class="el" href="core__ca_8h.html#a24cd5de9c2639ea81ef62500a3cbe8ad">GICDistributor_SGIR_NSATT_Pos</a>)</td></tr>
911 <tr class="separator:a99afa06bfe662185b91c004719979f4f"><td class="memSeparator" colspan="2"> </td></tr>
912 <tr class="memitem:ac2aff3b2b284d922e23a14dde8c91689"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#ac2aff3b2b284d922e23a14dde8c91689">GICDistributor_SGIR_NSATT</a>(x)   (((uint32_t)(((uint32_t)(x)) << <a class="el" href="core__ca_8h.html#a24cd5de9c2639ea81ef62500a3cbe8ad">GICDistributor_SGIR_NSATT_Pos</a>)) & <a class="el" href="core__ca_8h.html#a99afa06bfe662185b91c004719979f4f">GICDistributor_SGIR_NSATT_Msk</a>)</td></tr>
913 <tr class="separator:ac2aff3b2b284d922e23a14dde8c91689"><td class="memSeparator" colspan="2"> </td></tr>
914 <tr class="memitem:a981be1c459eaa484ad6f46de18e959c8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a981be1c459eaa484ad6f46de18e959c8">GICDistributor_SGIR_CPUTargetList_Pos</a>   16U</td></tr>
915 <tr class="separator:a981be1c459eaa484ad6f46de18e959c8"><td class="memSeparator" colspan="2"> </td></tr>
916 <tr class="memitem:a4b5c793fb6ace02cabc6afe09dce6af7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a4b5c793fb6ace02cabc6afe09dce6af7">GICDistributor_SGIR_CPUTargetList_Msk</a>   (0xFFU << <a class="el" href="core__ca_8h.html#a981be1c459eaa484ad6f46de18e959c8">GICDistributor_SGIR_CPUTargetList_Pos</a>)</td></tr>
917 <tr class="separator:a4b5c793fb6ace02cabc6afe09dce6af7"><td class="memSeparator" colspan="2"> </td></tr>
918 <tr class="memitem:a96fab5404da27e765c6e7c917674f5ae"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a96fab5404da27e765c6e7c917674f5ae">GICDistributor_SGIR_CPUTargetList</a>(x)   (((uint32_t)(((uint32_t)(x)) << <a class="el" href="core__ca_8h.html#a981be1c459eaa484ad6f46de18e959c8">GICDistributor_SGIR_CPUTargetList_Pos</a>)) & <a class="el" href="core__ca_8h.html#a4b5c793fb6ace02cabc6afe09dce6af7">GICDistributor_SGIR_CPUTargetList_Msk</a>)</td></tr>
919 <tr class="separator:a96fab5404da27e765c6e7c917674f5ae"><td class="memSeparator" colspan="2"> </td></tr>
920 <tr class="memitem:ac6d41353e1f46a74d007f75049c3571c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#ac6d41353e1f46a74d007f75049c3571c">GICDistributor_SGIR_TargetFilterList_Pos</a>   24U</td></tr>
921 <tr class="separator:ac6d41353e1f46a74d007f75049c3571c"><td class="memSeparator" colspan="2"> </td></tr>
922 <tr class="memitem:afef4f1a483835c535630dcd02c1640b4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#afef4f1a483835c535630dcd02c1640b4">GICDistributor_SGIR_TargetFilterList_Msk</a>   (0x3U << <a class="el" href="core__ca_8h.html#ac6d41353e1f46a74d007f75049c3571c">GICDistributor_SGIR_TargetFilterList_Pos</a>)</td></tr>
923 <tr class="separator:afef4f1a483835c535630dcd02c1640b4"><td class="memSeparator" colspan="2"> </td></tr>
924 <tr class="memitem:a503b7a0ad26672fdb87577162624c920"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a503b7a0ad26672fdb87577162624c920">GICDistributor_SGIR_TargetFilterList</a>(x)   (((uint32_t)(((uint32_t)(x)) << <a class="el" href="core__ca_8h.html#ac6d41353e1f46a74d007f75049c3571c">GICDistributor_SGIR_TargetFilterList_Pos</a>)) & <a class="el" href="core__ca_8h.html#afef4f1a483835c535630dcd02c1640b4">GICDistributor_SGIR_TargetFilterList_Msk</a>)</td></tr>
925 <tr class="separator:a503b7a0ad26672fdb87577162624c920"><td class="memSeparator" colspan="2"> </td></tr>
926 <tr class="memitem:ac400154f3e091ce5c0c04099349be036"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#ac400154f3e091ce5c0c04099349be036">GICDistributor_IROUTER_Aff0_Pos</a>   0UL</td></tr>
927 <tr class="separator:ac400154f3e091ce5c0c04099349be036"><td class="memSeparator" colspan="2"> </td></tr>
928 <tr class="memitem:a7154061efbf0bc6e0604788f3c8aade0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a7154061efbf0bc6e0604788f3c8aade0">GICDistributor_IROUTER_Aff0_Msk</a>   (0xFFUL /*<< <a class="el" href="core__ca_8h.html#ac400154f3e091ce5c0c04099349be036">GICDistributor_IROUTER_Aff0_Pos</a>*/)</td></tr>
929 <tr class="separator:a7154061efbf0bc6e0604788f3c8aade0"><td class="memSeparator" colspan="2"> </td></tr>
930 <tr class="memitem:a0fedb67ce7387bdf6003d4f8c9b2c3ae"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a0fedb67ce7387bdf6003d4f8c9b2c3ae">GICDistributor_IROUTER_Aff0</a>(x)   (((uint64_t)(((uint64_t)(x)) /*<< <a class="el" href="core__ca_8h.html#ac400154f3e091ce5c0c04099349be036">GICDistributor_IROUTER_Aff0_Pos</a>*/)) & <a class="el" href="core__ca_8h.html#a7154061efbf0bc6e0604788f3c8aade0">GICDistributor_IROUTER_Aff0_Msk</a>)</td></tr>
931 <tr class="separator:a0fedb67ce7387bdf6003d4f8c9b2c3ae"><td class="memSeparator" colspan="2"> </td></tr>
932 <tr class="memitem:a094d1737af75fe96cc48ec6f54876b73"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a094d1737af75fe96cc48ec6f54876b73">GICDistributor_IROUTER_Aff1_Pos</a>   8UL</td></tr>
933 <tr class="separator:a094d1737af75fe96cc48ec6f54876b73"><td class="memSeparator" colspan="2"> </td></tr>
934 <tr class="memitem:a1cb898980f65b989eb7010d27ca9d5a7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a1cb898980f65b989eb7010d27ca9d5a7">GICDistributor_IROUTER_Aff1_Msk</a>   (0xFFUL << <a class="el" href="core__ca_8h.html#a094d1737af75fe96cc48ec6f54876b73">GICDistributor_IROUTER_Aff1_Pos</a>)</td></tr>
935 <tr class="separator:a1cb898980f65b989eb7010d27ca9d5a7"><td class="memSeparator" colspan="2"> </td></tr>
936 <tr class="memitem:a6e35d64ab673e292bb88f6dc12172cec"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a6e35d64ab673e292bb88f6dc12172cec">GICDistributor_IROUTER_Aff1</a>(x)   (((uint64_t)(((uint64_t)(x)) << <a class="el" href="core__ca_8h.html#a094d1737af75fe96cc48ec6f54876b73">GICDistributor_IROUTER_Aff1_Pos</a>)) & <a class="el" href="core__ca_8h.html#a1cb898980f65b989eb7010d27ca9d5a7">GICDistributor_IROUTER_Aff1_Msk</a>)</td></tr>
937 <tr class="separator:a6e35d64ab673e292bb88f6dc12172cec"><td class="memSeparator" colspan="2"> </td></tr>
938 <tr class="memitem:a3b74de8f0df7bb175a81e0d397039242"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a3b74de8f0df7bb175a81e0d397039242">GICDistributor_IROUTER_Aff2_Pos</a>   16UL</td></tr>
939 <tr class="separator:a3b74de8f0df7bb175a81e0d397039242"><td class="memSeparator" colspan="2"> </td></tr>
940 <tr class="memitem:a52f6253031637bf0259b84e0e227509b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a52f6253031637bf0259b84e0e227509b">GICDistributor_IROUTER_Aff2_Msk</a>   (0xFFUL << <a class="el" href="core__ca_8h.html#a3b74de8f0df7bb175a81e0d397039242">GICDistributor_IROUTER_Aff2_Pos</a>)</td></tr>
941 <tr class="separator:a52f6253031637bf0259b84e0e227509b"><td class="memSeparator" colspan="2"> </td></tr>
942 <tr class="memitem:acc0b09a1d0d8dfbc745a0d3fe1619f8d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#acc0b09a1d0d8dfbc745a0d3fe1619f8d">GICDistributor_IROUTER_Aff2</a>(x)   (((uint64_t)(((uint64_t)(x)) << <a class="el" href="core__ca_8h.html#a3b74de8f0df7bb175a81e0d397039242">GICDistributor_IROUTER_Aff2_Pos</a>)) & <a class="el" href="core__ca_8h.html#a52f6253031637bf0259b84e0e227509b">GICDistributor_IROUTER_Aff2_Msk</a>)</td></tr>
943 <tr class="separator:acc0b09a1d0d8dfbc745a0d3fe1619f8d"><td class="memSeparator" colspan="2"> </td></tr>
944 <tr class="memitem:a622e872ac3a47cd90d1a7154d123abea"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a622e872ac3a47cd90d1a7154d123abea">GICDistributor_IROUTER_IRM_Pos</a>   31UL</td></tr>
945 <tr class="separator:a622e872ac3a47cd90d1a7154d123abea"><td class="memSeparator" colspan="2"> </td></tr>
946 <tr class="memitem:a4cec345b240a7e84c6624e153b97b4d6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a4cec345b240a7e84c6624e153b97b4d6">GICDistributor_IROUTER_IRM_Msk</a>   (0xFFUL << <a class="el" href="core__ca_8h.html#a622e872ac3a47cd90d1a7154d123abea">GICDistributor_IROUTER_IRM_Pos</a>)</td></tr>
947 <tr class="separator:a4cec345b240a7e84c6624e153b97b4d6"><td class="memSeparator" colspan="2"> </td></tr>
948 <tr class="memitem:a5d3044d648a99a8611ace4afc0590979"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a5d3044d648a99a8611ace4afc0590979">GICDistributor_IROUTER_IRM</a>(x)   (((uint64_t)(((uint64_t)(x)) << <a class="el" href="core__ca_8h.html#a622e872ac3a47cd90d1a7154d123abea">GICDistributor_IROUTER_IRM_Pos</a>)) & <a class="el" href="core__ca_8h.html#a4cec345b240a7e84c6624e153b97b4d6">GICDistributor_IROUTER_IRM_Msk</a>)</td></tr>
949 <tr class="separator:a5d3044d648a99a8611ace4afc0590979"><td class="memSeparator" colspan="2"> </td></tr>
950 <tr class="memitem:ac13830edd01d66e99f92ee103cb04d1f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#ac13830edd01d66e99f92ee103cb04d1f">GICDistributor_IROUTER_Aff3_Pos</a>   32UL</td></tr>
951 <tr class="separator:ac13830edd01d66e99f92ee103cb04d1f"><td class="memSeparator" colspan="2"> </td></tr>
952 <tr class="memitem:a51a1800358ad5c1f752e49c39cd9e830"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a51a1800358ad5c1f752e49c39cd9e830">GICDistributor_IROUTER_Aff3_Msk</a>   (0xFFUL << <a class="el" href="core__ca_8h.html#ac13830edd01d66e99f92ee103cb04d1f">GICDistributor_IROUTER_Aff3_Pos</a>)</td></tr>
953 <tr class="separator:a51a1800358ad5c1f752e49c39cd9e830"><td class="memSeparator" colspan="2"> </td></tr>
954 <tr class="memitem:ad1418cd587ed92264e68c2cbbc18ea2e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#ad1418cd587ed92264e68c2cbbc18ea2e">GICDistributor_IROUTER_Aff3</a>(x)   (((uint64_t)(((uint64_t)(x)) << <a class="el" href="core__ca_8h.html#ac13830edd01d66e99f92ee103cb04d1f">GICDistributor_IROUTER_Aff3_Pos</a>)) & <a class="el" href="core__ca_8h.html#a51a1800358ad5c1f752e49c39cd9e830">GICDistributor_IROUTER_Aff3_Msk</a>)</td></tr>
955 <tr class="separator:ad1418cd587ed92264e68c2cbbc18ea2e"><td class="memSeparator" colspan="2"> </td></tr>
956 <tr class="memitem:ga31a083dbdc5cb84178dbf184286180e3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#ga31a083dbdc5cb84178dbf184286180e3">GICInterface</a>   ((<a class="el" href="structGICInterface__Type.html">GICInterface_Type</a> *) GIC_INTERFACE_BASE )</td></tr>
957 <tr class="memdesc:ga31a083dbdc5cb84178dbf184286180e3"><td class="mdescLeft"> </td><td class="mdescRight">GIC Interface register set access pointer. <br /></td></tr>
958 <tr class="separator:ga31a083dbdc5cb84178dbf184286180e3"><td class="memSeparator" colspan="2"> </td></tr>
959 <tr class="memitem:a23a54215a53eac983daab61b98a42dac"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a23a54215a53eac983daab61b98a42dac">GICInterface_CTLR_Enable_Pos</a>   0U</td></tr>
960 <tr class="separator:a23a54215a53eac983daab61b98a42dac"><td class="memSeparator" colspan="2"> </td></tr>
961 <tr class="memitem:a5b7bfcdc714a0f56aabe7aada107c0b0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a5b7bfcdc714a0f56aabe7aada107c0b0">GICInterface_CTLR_Enable_Msk</a>   (0x1U /*<< <a class="el" href="core__ca_8h.html#a23a54215a53eac983daab61b98a42dac">GICInterface_CTLR_Enable_Pos</a>*/)</td></tr>
962 <tr class="separator:a5b7bfcdc714a0f56aabe7aada107c0b0"><td class="memSeparator" colspan="2"> </td></tr>
963 <tr class="memitem:aaa6e31976be4c7fd0712873df95ff76e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#aaa6e31976be4c7fd0712873df95ff76e">GICInterface_CTLR_Enable</a>(x)   (((uint32_t)(((uint32_t)(x)) /*<< <a class="el" href="core__ca_8h.html#a23a54215a53eac983daab61b98a42dac">GICInterface_CTLR_Enable_Pos</a>*/)) & <a class="el" href="core__ca_8h.html#a5b7bfcdc714a0f56aabe7aada107c0b0">GICInterface_CTLR_Enable_Msk</a>)</td></tr>
964 <tr class="separator:aaa6e31976be4c7fd0712873df95ff76e"><td class="memSeparator" colspan="2"> </td></tr>
965 <tr class="memitem:a71c3b07764634704decda87508d302aa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a71c3b07764634704decda87508d302aa">GICInterface_PMR_Priority_Pos</a>   0U</td></tr>
966 <tr class="separator:a71c3b07764634704decda87508d302aa"><td class="memSeparator" colspan="2"> </td></tr>
967 <tr class="memitem:af4e6f38664b7a24008df71779e53b628"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#af4e6f38664b7a24008df71779e53b628">GICInterface_PMR_Priority_Msk</a>   (0xFFU /*<< <a class="el" href="core__ca_8h.html#a71c3b07764634704decda87508d302aa">GICInterface_PMR_Priority_Pos</a>*/)</td></tr>
968 <tr class="separator:af4e6f38664b7a24008df71779e53b628"><td class="memSeparator" colspan="2"> </td></tr>
969 <tr class="memitem:a149d248020f9bb305a8f98dbe22d683f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a149d248020f9bb305a8f98dbe22d683f">GICInterface_PMR_Priority</a>(x)   (((uint32_t)(((uint32_t)(x)) /*<< <a class="el" href="core__ca_8h.html#a71c3b07764634704decda87508d302aa">GICInterface_PMR_Priority_Pos</a>*/)) & <a class="el" href="core__ca_8h.html#af4e6f38664b7a24008df71779e53b628">GICInterface_PMR_Priority_Msk</a>)</td></tr>
970 <tr class="separator:a149d248020f9bb305a8f98dbe22d683f"><td class="memSeparator" colspan="2"> </td></tr>
971 <tr class="memitem:ab1be8491d3c5f996d484e4664a24ed53"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#ab1be8491d3c5f996d484e4664a24ed53">GICInterface_BPR_Binary_Point_Pos</a>   0U</td></tr>
972 <tr class="separator:ab1be8491d3c5f996d484e4664a24ed53"><td class="memSeparator" colspan="2"> </td></tr>
973 <tr class="memitem:a77e90d30a84d26f405b3fc6e7000370c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a77e90d30a84d26f405b3fc6e7000370c">GICInterface_BPR_Binary_Point_Msk</a>   (0x7U /*<< <a class="el" href="core__ca_8h.html#ab1be8491d3c5f996d484e4664a24ed53">GICInterface_BPR_Binary_Point_Pos</a>*/)</td></tr>
974 <tr class="separator:a77e90d30a84d26f405b3fc6e7000370c"><td class="memSeparator" colspan="2"> </td></tr>
975 <tr class="memitem:a4ebcb87bed742c0b28d08f5c668f9033"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a4ebcb87bed742c0b28d08f5c668f9033">GICInterface_BPR_Binary_Point</a>(x)   (((uint32_t)(((uint32_t)(x)) /*<< <a class="el" href="core__ca_8h.html#ab1be8491d3c5f996d484e4664a24ed53">GICInterface_BPR_Binary_Point_Pos</a>*/)) & <a class="el" href="core__ca_8h.html#a77e90d30a84d26f405b3fc6e7000370c">GICInterface_BPR_Binary_Point_Msk</a>)</td></tr>
976 <tr class="separator:a4ebcb87bed742c0b28d08f5c668f9033"><td class="memSeparator" colspan="2"> </td></tr>
977 <tr class="memitem:a25b2030f094c7c5e61fb60f7ab537a29"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a25b2030f094c7c5e61fb60f7ab537a29">GICInterface_IAR_INTID_Pos</a>   0U</td></tr>
978 <tr class="separator:a25b2030f094c7c5e61fb60f7ab537a29"><td class="memSeparator" colspan="2"> </td></tr>
979 <tr class="memitem:a65c7a27d6678c414fbad22c0a0bee56e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a65c7a27d6678c414fbad22c0a0bee56e">GICInterface_IAR_INTID_Msk</a>   (0xFFFFFFU /*<< <a class="el" href="core__ca_8h.html#a25b2030f094c7c5e61fb60f7ab537a29">GICInterface_IAR_INTID_Pos</a>*/)</td></tr>
980 <tr class="separator:a65c7a27d6678c414fbad22c0a0bee56e"><td class="memSeparator" colspan="2"> </td></tr>
981 <tr class="memitem:a83cfd1ed557e7d19c3ff09b13d1bc63c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a83cfd1ed557e7d19c3ff09b13d1bc63c">GICInterface_IAR_INTID</a>(x)   (((uint32_t)(((uint32_t)(x)) /*<< <a class="el" href="core__ca_8h.html#a25b2030f094c7c5e61fb60f7ab537a29">GICInterface_IAR_INTID_Pos</a>*/)) & <a class="el" href="core__ca_8h.html#a65c7a27d6678c414fbad22c0a0bee56e">GICInterface_IAR_INTID_Msk</a>)</td></tr>
982 <tr class="separator:a83cfd1ed557e7d19c3ff09b13d1bc63c"><td class="memSeparator" colspan="2"> </td></tr>
983 <tr class="memitem:a101da35ef97f5bdf0593fbf1f8a7335c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a101da35ef97f5bdf0593fbf1f8a7335c">GICInterface_EOIR_INTID_Pos</a>   0U</td></tr>
984 <tr class="separator:a101da35ef97f5bdf0593fbf1f8a7335c"><td class="memSeparator" colspan="2"> </td></tr>
985 <tr class="memitem:a31d46bd478e4cff2c41ddd86f1c2151a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a31d46bd478e4cff2c41ddd86f1c2151a">GICInterface_EOIR_INTID_Msk</a>   (0xFFFFFFU /*<< <a class="el" href="core__ca_8h.html#a101da35ef97f5bdf0593fbf1f8a7335c">GICInterface_EOIR_INTID_Pos</a>*/)</td></tr>
986 <tr class="separator:a31d46bd478e4cff2c41ddd86f1c2151a"><td class="memSeparator" colspan="2"> </td></tr>
987 <tr class="memitem:af92688869c3fe1172bd2be443cd42f74"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#af92688869c3fe1172bd2be443cd42f74">GICInterface_EOIR_INTID</a>(x)   (((uint32_t)(((uint32_t)(x)) /*<< <a class="el" href="core__ca_8h.html#a101da35ef97f5bdf0593fbf1f8a7335c">GICInterface_EOIR_INTID_Pos</a>*/)) & <a class="el" href="core__ca_8h.html#a31d46bd478e4cff2c41ddd86f1c2151a">GICInterface_EOIR_INTID_Msk</a>)</td></tr>
988 <tr class="separator:af92688869c3fe1172bd2be443cd42f74"><td class="memSeparator" colspan="2"> </td></tr>
989 <tr class="memitem:ad3081f7f2410d2895c727e6d11d53253"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#ad3081f7f2410d2895c727e6d11d53253">GICInterface_RPR_INTID_Pos</a>   0U</td></tr>
990 <tr class="separator:ad3081f7f2410d2895c727e6d11d53253"><td class="memSeparator" colspan="2"> </td></tr>
991 <tr class="memitem:aee1baadc46e37df107730db62340824f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#aee1baadc46e37df107730db62340824f">GICInterface_RPR_INTID_Msk</a>   (0xFFU /*<< <a class="el" href="core__ca_8h.html#ad3081f7f2410d2895c727e6d11d53253">GICInterface_RPR_INTID_Pos</a>*/)</td></tr>
992 <tr class="separator:aee1baadc46e37df107730db62340824f"><td class="memSeparator" colspan="2"> </td></tr>
993 <tr class="memitem:a3b85565c9bdf010acc15523073aa1789"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a3b85565c9bdf010acc15523073aa1789">GICInterface_RPR_INTID</a>(x)   (((uint32_t)(((uint32_t)(x)) /*<< <a class="el" href="core__ca_8h.html#ad3081f7f2410d2895c727e6d11d53253">GICInterface_RPR_INTID_Pos</a>*/)) & <a class="el" href="core__ca_8h.html#aee1baadc46e37df107730db62340824f">GICInterface_RPR_INTID_Msk</a>)</td></tr>
994 <tr class="separator:a3b85565c9bdf010acc15523073aa1789"><td class="memSeparator" colspan="2"> </td></tr>
995 <tr class="memitem:a0951b34200d0d4b1cd18dd8cc9af1224"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a0951b34200d0d4b1cd18dd8cc9af1224">GICInterface_HPPIR_INTID_Pos</a>   0U</td></tr>
996 <tr class="separator:a0951b34200d0d4b1cd18dd8cc9af1224"><td class="memSeparator" colspan="2"> </td></tr>
997 <tr class="memitem:a26f9cea29872fdd172ce51c210e72235"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a26f9cea29872fdd172ce51c210e72235">GICInterface_HPPIR_INTID_Msk</a>   (0xFFFFFFU /*<< <a class="el" href="core__ca_8h.html#a0951b34200d0d4b1cd18dd8cc9af1224">GICInterface_HPPIR_INTID_Pos</a>*/)</td></tr>
998 <tr class="separator:a26f9cea29872fdd172ce51c210e72235"><td class="memSeparator" colspan="2"> </td></tr>
999 <tr class="memitem:a38b60af419b00e92185a98a09d82d562"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a38b60af419b00e92185a98a09d82d562">GICInterface_HPPIR_INTID</a>(x)   (((uint32_t)(((uint32_t)(x)) /*<< <a class="el" href="core__ca_8h.html#a0951b34200d0d4b1cd18dd8cc9af1224">GICInterface_HPPIR_INTID_Pos</a>*/)) & <a class="el" href="core__ca_8h.html#a26f9cea29872fdd172ce51c210e72235">GICInterface_HPPIR_INTID_Msk</a>)</td></tr>
1000 <tr class="separator:a38b60af419b00e92185a98a09d82d562"><td class="memSeparator" colspan="2"> </td></tr>
1001 <tr class="memitem:a807965f59441878b51ff6d29b6354b68"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a807965f59441878b51ff6d29b6354b68">GICInterface_ABPR_Binary_Point_Pos</a>   0U</td></tr>
1002 <tr class="separator:a807965f59441878b51ff6d29b6354b68"><td class="memSeparator" colspan="2"> </td></tr>
1003 <tr class="memitem:a5af342deca8701354f1bf9eccd08f28f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a5af342deca8701354f1bf9eccd08f28f">GICInterface_ABPR_Binary_Point_Msk</a>   (0x7U /*<< <a class="el" href="core__ca_8h.html#a807965f59441878b51ff6d29b6354b68">GICInterface_ABPR_Binary_Point_Pos</a>*/)</td></tr>
1004 <tr class="separator:a5af342deca8701354f1bf9eccd08f28f"><td class="memSeparator" colspan="2"> </td></tr>
1005 <tr class="memitem:a1134babb25c7f194a2381206afc550e6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a1134babb25c7f194a2381206afc550e6">GICInterface_ABPR_Binary_Point</a>(x)   (((uint32_t)(((uint32_t)(x)) /*<< <a class="el" href="core__ca_8h.html#a807965f59441878b51ff6d29b6354b68">GICInterface_ABPR_Binary_Point_Pos</a>*/)) & <a class="el" href="core__ca_8h.html#a5af342deca8701354f1bf9eccd08f28f">GICInterface_ABPR_Binary_Point_Msk</a>)</td></tr>
1006 <tr class="separator:a1134babb25c7f194a2381206afc550e6"><td class="memSeparator" colspan="2"> </td></tr>
1007 <tr class="memitem:aefdcb304363aa42cc311e7a8fc4d0c29"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#aefdcb304363aa42cc311e7a8fc4d0c29">GICInterface_AIAR_INTID_Pos</a>   0U</td></tr>
1008 <tr class="separator:aefdcb304363aa42cc311e7a8fc4d0c29"><td class="memSeparator" colspan="2"> </td></tr>
1009 <tr class="memitem:a4eca545aea443243d25859b358d15260"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a4eca545aea443243d25859b358d15260">GICInterface_AIAR_INTID_Msk</a>   (0xFFFFFFU /*<< <a class="el" href="core__ca_8h.html#aefdcb304363aa42cc311e7a8fc4d0c29">GICInterface_AIAR_INTID_Pos</a>*/)</td></tr>
1010 <tr class="separator:a4eca545aea443243d25859b358d15260"><td class="memSeparator" colspan="2"> </td></tr>
1011 <tr class="memitem:aa808951562f71c5094c5283ae88a8f9b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#aa808951562f71c5094c5283ae88a8f9b">GICInterface_AIAR_INTID</a>(x)   (((uint32_t)(((uint32_t)(x)) /*<< <a class="el" href="core__ca_8h.html#aefdcb304363aa42cc311e7a8fc4d0c29">GICInterface_AIAR_INTID_Pos</a>*/)) & <a class="el" href="core__ca_8h.html#a4eca545aea443243d25859b358d15260">GICInterface_AIAR_INTID_Msk</a>)</td></tr>
1012 <tr class="separator:aa808951562f71c5094c5283ae88a8f9b"><td class="memSeparator" colspan="2"> </td></tr>
1013 <tr class="memitem:acb9124edf6d65fbf428b913c9e4fd892"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#acb9124edf6d65fbf428b913c9e4fd892">GICInterface_AEOIR_INTID_Pos</a>   0U</td></tr>
1014 <tr class="separator:acb9124edf6d65fbf428b913c9e4fd892"><td class="memSeparator" colspan="2"> </td></tr>
1015 <tr class="memitem:a41906ea8e42bcc5b7925863a0c01379b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a41906ea8e42bcc5b7925863a0c01379b">GICInterface_AEOIR_INTID_Msk</a>   (0xFFFFFFU /*<< <a class="el" href="core__ca_8h.html#acb9124edf6d65fbf428b913c9e4fd892">GICInterface_AEOIR_INTID_Pos</a>*/)</td></tr>
1016 <tr class="separator:a41906ea8e42bcc5b7925863a0c01379b"><td class="memSeparator" colspan="2"> </td></tr>
1017 <tr class="memitem:a04f1bd42fd08721ec7a327936298d80c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a04f1bd42fd08721ec7a327936298d80c">GICInterface_AEOIR_INTID</a>(x)   (((uint32_t)(((uint32_t)(x)) /*<< <a class="el" href="core__ca_8h.html#acb9124edf6d65fbf428b913c9e4fd892">GICInterface_AEOIR_INTID_Pos</a>*/)) & <a class="el" href="core__ca_8h.html#a41906ea8e42bcc5b7925863a0c01379b">GICInterface_AEOIR_INTID_Msk</a>)</td></tr>
1018 <tr class="separator:a04f1bd42fd08721ec7a327936298d80c"><td class="memSeparator" colspan="2"> </td></tr>
1019 <tr class="memitem:a09b44c6effd3209e5d87251d8bcb4e71"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a09b44c6effd3209e5d87251d8bcb4e71">GICInterface_AHPPIR_INTID_Pos</a>   0U</td></tr>
1020 <tr class="separator:a09b44c6effd3209e5d87251d8bcb4e71"><td class="memSeparator" colspan="2"> </td></tr>
1021 <tr class="memitem:a7edb7a7eef0400b3fb96adc814c93621"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a7edb7a7eef0400b3fb96adc814c93621">GICInterface_AHPPIR_INTID_Msk</a>   (0xFFFFFFU /*<< <a class="el" href="core__ca_8h.html#a09b44c6effd3209e5d87251d8bcb4e71">GICInterface_AHPPIR_INTID_Pos</a>*/)</td></tr>
1022 <tr class="separator:a7edb7a7eef0400b3fb96adc814c93621"><td class="memSeparator" colspan="2"> </td></tr>
1023 <tr class="memitem:abf052e1e08eb339e1bb04f624d0c40d4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#abf052e1e08eb339e1bb04f624d0c40d4">GICInterface_AHPPIR_INTID</a>(x)   (((uint32_t)(((uint32_t)(x)) /*<< <a class="el" href="core__ca_8h.html#a09b44c6effd3209e5d87251d8bcb4e71">GICInterface_AHPPIR_INTID_Pos</a>*/)) & <a class="el" href="core__ca_8h.html#a7edb7a7eef0400b3fb96adc814c93621">GICInterface_AHPPIR_INTID_Msk</a>)</td></tr>
1024 <tr class="separator:abf052e1e08eb339e1bb04f624d0c40d4"><td class="memSeparator" colspan="2"> </td></tr>
1025 <tr class="memitem:a31d5831811352718da5ffeae8cfbd22d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a31d5831811352718da5ffeae8cfbd22d">GICInterface_STATUSR_RRD_Pos</a>   0U</td></tr>
1026 <tr class="separator:a31d5831811352718da5ffeae8cfbd22d"><td class="memSeparator" colspan="2"> </td></tr>
1027 <tr class="memitem:a7efdc959647f530286fd2d29becf3842"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a7efdc959647f530286fd2d29becf3842">GICInterface_STATUSR_RRD_Msk</a>   (0x1U /*<< <a class="el" href="core__ca_8h.html#a31d5831811352718da5ffeae8cfbd22d">GICInterface_STATUSR_RRD_Pos</a>*/)</td></tr>
1028 <tr class="separator:a7efdc959647f530286fd2d29becf3842"><td class="memSeparator" colspan="2"> </td></tr>
1029 <tr class="memitem:aed0f5fcd7a7ce0eb0c60c1d206df2bc9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#aed0f5fcd7a7ce0eb0c60c1d206df2bc9">GICInterface_STATUSR_RRD</a>(x)   (((uint32_t)(((uint32_t)(x)) /*<< <a class="el" href="core__ca_8h.html#a31d5831811352718da5ffeae8cfbd22d">GICInterface_STATUSR_RRD_Pos</a>*/)) & <a class="el" href="core__ca_8h.html#a7efdc959647f530286fd2d29becf3842">GICInterface_STATUSR_RRD_Msk</a>)</td></tr>
1030 <tr class="separator:aed0f5fcd7a7ce0eb0c60c1d206df2bc9"><td class="memSeparator" colspan="2"> </td></tr>
1031 <tr class="memitem:af4509593e33b8149c23a9b13650bad6c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#af4509593e33b8149c23a9b13650bad6c">GICInterface_STATUSR_WRD_Pos</a>   1U</td></tr>
1032 <tr class="separator:af4509593e33b8149c23a9b13650bad6c"><td class="memSeparator" colspan="2"> </td></tr>
1033 <tr class="memitem:a166bcb139f401bf72f56d05c1415707c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a166bcb139f401bf72f56d05c1415707c">GICInterface_STATUSR_WRD_Msk</a>   (0x1U << <a class="el" href="core__ca_8h.html#af4509593e33b8149c23a9b13650bad6c">GICInterface_STATUSR_WRD_Pos</a>)</td></tr>
1034 <tr class="separator:a166bcb139f401bf72f56d05c1415707c"><td class="memSeparator" colspan="2"> </td></tr>
1035 <tr class="memitem:a621d80944d8334a2b5f66391b70502f3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a621d80944d8334a2b5f66391b70502f3">GICInterface_STATUSR_WRD</a>(x)   (((uint32_t)(((uint32_t)(x)) << <a class="el" href="core__ca_8h.html#af4509593e33b8149c23a9b13650bad6c">GICInterface_STATUSR_WRD_Pos</a>)) & <a class="el" href="core__ca_8h.html#a166bcb139f401bf72f56d05c1415707c">GICInterface_STATUSR_WRD_Msk</a>)</td></tr>
1036 <tr class="separator:a621d80944d8334a2b5f66391b70502f3"><td class="memSeparator" colspan="2"> </td></tr>
1037 <tr class="memitem:a01544142ac5dfb1a0082a91d6624179a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a01544142ac5dfb1a0082a91d6624179a">GICInterface_STATUSR_RWOD_Pos</a>   2U</td></tr>
1038 <tr class="separator:a01544142ac5dfb1a0082a91d6624179a"><td class="memSeparator" colspan="2"> </td></tr>
1039 <tr class="memitem:ab5f3156c0331d78950808841637b519f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#ab5f3156c0331d78950808841637b519f">GICInterface_STATUSR_RWOD_Msk</a>   (0x1U << <a class="el" href="core__ca_8h.html#a01544142ac5dfb1a0082a91d6624179a">GICInterface_STATUSR_RWOD_Pos</a>)</td></tr>
1040 <tr class="separator:ab5f3156c0331d78950808841637b519f"><td class="memSeparator" colspan="2"> </td></tr>
1041 <tr class="memitem:a81d59c7f5d66114e6450a679d961412b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a81d59c7f5d66114e6450a679d961412b">GICInterface_STATUSR_RWOD</a>(x)   (((uint32_t)(((uint32_t)(x)) << <a class="el" href="core__ca_8h.html#a01544142ac5dfb1a0082a91d6624179a">GICInterface_STATUSR_RWOD_Pos</a>)) & <a class="el" href="core__ca_8h.html#ab5f3156c0331d78950808841637b519f">GICInterface_STATUSR_RWOD_Msk</a>)</td></tr>
1042 <tr class="separator:a81d59c7f5d66114e6450a679d961412b"><td class="memSeparator" colspan="2"> </td></tr>
1043 <tr class="memitem:a609fdc19acdc64c72022c8f7e72f9fac"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a609fdc19acdc64c72022c8f7e72f9fac">GICInterface_STATUSR_WROD_Pos</a>   3U</td></tr>
1044 <tr class="separator:a609fdc19acdc64c72022c8f7e72f9fac"><td class="memSeparator" colspan="2"> </td></tr>
1045 <tr class="memitem:a316618e6da5aaaa3de21001615afb2ec"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a316618e6da5aaaa3de21001615afb2ec">GICInterface_STATUSR_WROD_Msk</a>   (0x1U << <a class="el" href="core__ca_8h.html#a609fdc19acdc64c72022c8f7e72f9fac">GICInterface_STATUSR_WROD_Pos</a>)</td></tr>
1046 <tr class="separator:a316618e6da5aaaa3de21001615afb2ec"><td class="memSeparator" colspan="2"> </td></tr>
1047 <tr class="memitem:a8e4b0656d26328a98afa4f81038943cf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a8e4b0656d26328a98afa4f81038943cf">GICInterface_STATUSR_WROD</a>(x)   (((uint32_t)(((uint32_t)(x)) << <a class="el" href="core__ca_8h.html#a609fdc19acdc64c72022c8f7e72f9fac">GICInterface_STATUSR_WROD_Pos</a>)) & <a class="el" href="core__ca_8h.html#a316618e6da5aaaa3de21001615afb2ec">GICInterface_STATUSR_WROD_Msk</a>)</td></tr>
1048 <tr class="separator:a8e4b0656d26328a98afa4f81038943cf"><td class="memSeparator" colspan="2"> </td></tr>
1049 <tr class="memitem:ab8fb5c170d172871cbbf690c5d4b7ea7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#ab8fb5c170d172871cbbf690c5d4b7ea7">GICInterface_STATUSR_ASV_Pos</a>   4U</td></tr>
1050 <tr class="separator:ab8fb5c170d172871cbbf690c5d4b7ea7"><td class="memSeparator" colspan="2"> </td></tr>
1051 <tr class="memitem:ae156c36ac00480f8ead8bc46f061671f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#ae156c36ac00480f8ead8bc46f061671f">GICInterface_STATUSR_ASV_Msk</a>   (0x1U << <a class="el" href="core__ca_8h.html#ab8fb5c170d172871cbbf690c5d4b7ea7">GICInterface_STATUSR_ASV_Pos</a>)</td></tr>
1052 <tr class="separator:ae156c36ac00480f8ead8bc46f061671f"><td class="memSeparator" colspan="2"> </td></tr>
1053 <tr class="memitem:aeaa7aff9ec9c1e9b4248600198295bda"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#aeaa7aff9ec9c1e9b4248600198295bda">GICInterface_STATUSR_ASV</a>(x)   (((uint32_t)(((uint32_t)(x)) << <a class="el" href="core__ca_8h.html#ab8fb5c170d172871cbbf690c5d4b7ea7">GICInterface_STATUSR_ASV_Pos</a>)) & <a class="el" href="core__ca_8h.html#ae156c36ac00480f8ead8bc46f061671f">GICInterface_STATUSR_ASV_Msk</a>)</td></tr>
1054 <tr class="separator:aeaa7aff9ec9c1e9b4248600198295bda"><td class="memSeparator" colspan="2"> </td></tr>
1055 <tr class="memitem:ad2ed35ce0fc0f10dcfce477c15f00f67"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#ad2ed35ce0fc0f10dcfce477c15f00f67">GICInterface_IIDR_Implementer_Pos</a>   0U</td></tr>
1056 <tr class="separator:ad2ed35ce0fc0f10dcfce477c15f00f67"><td class="memSeparator" colspan="2"> </td></tr>
1057 <tr class="memitem:a236375bbcaae3f7a9d45b361b246d1bb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a236375bbcaae3f7a9d45b361b246d1bb">GICInterface_IIDR_Implementer_Msk</a>   (0xFFFU /*<< <a class="el" href="core__ca_8h.html#ad2ed35ce0fc0f10dcfce477c15f00f67">GICInterface_IIDR_Implementer_Pos</a>*/)</td></tr>
1058 <tr class="separator:a236375bbcaae3f7a9d45b361b246d1bb"><td class="memSeparator" colspan="2"> </td></tr>
1059 <tr class="memitem:ad4ae4c6ad0dc3751e3876e0d5771e3b3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#ad4ae4c6ad0dc3751e3876e0d5771e3b3">GICInterface_IIDR_Implementer</a>(x)   (((uint32_t)(((uint32_t)(x)) /*<< <a class="el" href="core__ca_8h.html#ad2ed35ce0fc0f10dcfce477c15f00f67">GICInterface_IIDR_Implementer_Pos</a>*/)) & <a class="el" href="core__ca_8h.html#a236375bbcaae3f7a9d45b361b246d1bb">GICInterface_IIDR_Implementer_Msk</a>)</td></tr>
1060 <tr class="separator:ad4ae4c6ad0dc3751e3876e0d5771e3b3"><td class="memSeparator" colspan="2"> </td></tr>
1061 <tr class="memitem:a4332a64581e1c031918b50e0d32ecff2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a4332a64581e1c031918b50e0d32ecff2">GICInterface_IIDR_Revision_Pos</a>   12U</td></tr>
1062 <tr class="separator:a4332a64581e1c031918b50e0d32ecff2"><td class="memSeparator" colspan="2"> </td></tr>
1063 <tr class="memitem:ab916e22aa1b8a7589e028a9189a768ae"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#ab916e22aa1b8a7589e028a9189a768ae">GICInterface_IIDR_Revision_Msk</a>   (0xFU << <a class="el" href="core__ca_8h.html#a4332a64581e1c031918b50e0d32ecff2">GICInterface_IIDR_Revision_Pos</a>)</td></tr>
1064 <tr class="separator:ab916e22aa1b8a7589e028a9189a768ae"><td class="memSeparator" colspan="2"> </td></tr>
1065 <tr class="memitem:af03805237be902c223d23f8a19b6b2da"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#af03805237be902c223d23f8a19b6b2da">GICInterface_IIDR_Revision</a>(x)   (((uint32_t)(((uint32_t)(x)) << <a class="el" href="core__ca_8h.html#a4332a64581e1c031918b50e0d32ecff2">GICInterface_IIDR_Revision_Pos</a>)) & <a class="el" href="core__ca_8h.html#ab916e22aa1b8a7589e028a9189a768ae">GICInterface_IIDR_Revision_Msk</a>)</td></tr>
1066 <tr class="separator:af03805237be902c223d23f8a19b6b2da"><td class="memSeparator" colspan="2"> </td></tr>
1067 <tr class="memitem:a0006025e23900973bd2bc2b89ff66325"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a0006025e23900973bd2bc2b89ff66325">GICInterface_IIDR_Arch_version_Pos</a>   16U</td></tr>
1068 <tr class="separator:a0006025e23900973bd2bc2b89ff66325"><td class="memSeparator" colspan="2"> </td></tr>
1069 <tr class="memitem:a8a5a87c9eb30f036d1e65398337337c2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a8a5a87c9eb30f036d1e65398337337c2">GICInterface_IIDR_Arch_version_Msk</a>   (0xFU << <a class="el" href="core__ca_8h.html#a0006025e23900973bd2bc2b89ff66325">GICInterface_IIDR_Arch_version_Pos</a>)</td></tr>
1070 <tr class="separator:a8a5a87c9eb30f036d1e65398337337c2"><td class="memSeparator" colspan="2"> </td></tr>
1071 <tr class="memitem:a8dc9c6a1f189721daa9075a9a322ed24"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a8dc9c6a1f189721daa9075a9a322ed24">GICInterface_IIDR_Arch_version</a>(x)   (((uint32_t)(((uint32_t)(x)) << <a class="el" href="core__ca_8h.html#a0006025e23900973bd2bc2b89ff66325">GICInterface_IIDR_Arch_version_Pos</a>)) & <a class="el" href="core__ca_8h.html#a8a5a87c9eb30f036d1e65398337337c2">GICInterface_IIDR_Arch_version_Msk</a>)</td></tr>
1072 <tr class="separator:a8dc9c6a1f189721daa9075a9a322ed24"><td class="memSeparator" colspan="2"> </td></tr>
1073 <tr class="memitem:ac5da4a6801384f51c427e8ab5ff05cba"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#ac5da4a6801384f51c427e8ab5ff05cba">GICInterface_IIDR_ProductID_Pos</a>   20U</td></tr>
1074 <tr class="separator:ac5da4a6801384f51c427e8ab5ff05cba"><td class="memSeparator" colspan="2"> </td></tr>
1075 <tr class="memitem:a7253c0646d972858f8c75e650d25b3ec"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a7253c0646d972858f8c75e650d25b3ec">GICInterface_IIDR_ProductID_Msk</a>   (0xFFFU << <a class="el" href="core__ca_8h.html#ac5da4a6801384f51c427e8ab5ff05cba">GICInterface_IIDR_ProductID_Pos</a>)</td></tr>
1076 <tr class="separator:a7253c0646d972858f8c75e650d25b3ec"><td class="memSeparator" colspan="2"> </td></tr>
1077 <tr class="memitem:a839baee0cf697e8d259679352e440652"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a839baee0cf697e8d259679352e440652">GICInterface_IIDR_ProductID</a>(x)   (((uint32_t)(((uint32_t)(x)) << <a class="el" href="core__ca_8h.html#ac5da4a6801384f51c427e8ab5ff05cba">GICInterface_IIDR_ProductID_Pos</a>)) & <a class="el" href="core__ca_8h.html#a7253c0646d972858f8c75e650d25b3ec">GICInterface_IIDR_ProductID_Msk</a>)</td></tr>
1078 <tr class="separator:a839baee0cf697e8d259679352e440652"><td class="memSeparator" colspan="2"> </td></tr>
1079 <tr class="memitem:ac9c4fb306629c6c0e1821ac4cb82e46a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#ac9c4fb306629c6c0e1821ac4cb82e46a">GICInterface_DIR_INTID_Pos</a>   0U</td></tr>
1080 <tr class="separator:ac9c4fb306629c6c0e1821ac4cb82e46a"><td class="memSeparator" colspan="2"> </td></tr>
1081 <tr class="memitem:a9baee7d21c9c7b278b4e4e92a7e242b8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a9baee7d21c9c7b278b4e4e92a7e242b8">GICInterface_DIR_INTID_Msk</a>   (0xFFFFFFU /*<< <a class="el" href="core__ca_8h.html#ac9c4fb306629c6c0e1821ac4cb82e46a">GICInterface_DIR_INTID_Pos</a>*/)</td></tr>
1082 <tr class="separator:a9baee7d21c9c7b278b4e4e92a7e242b8"><td class="memSeparator" colspan="2"> </td></tr>
1083 <tr class="memitem:a6ff56d88ebfcc520e7f27a7dbfcdcf7a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a6ff56d88ebfcc520e7f27a7dbfcdcf7a">GICInterface_DIR_INTID</a>(x)   (((uint32_t)(((uint32_t)(x)) /*<< <a class="el" href="core__ca_8h.html#ac9c4fb306629c6c0e1821ac4cb82e46a">GICInterface_DIR_INTID_Pos</a>*/)) & <a class="el" href="core__ca_8h.html#a9baee7d21c9c7b278b4e4e92a7e242b8">GICInterface_DIR_INTID_Msk</a>)</td></tr>
1084 <tr class="separator:a6ff56d88ebfcc520e7f27a7dbfcdcf7a"><td class="memSeparator" colspan="2"> </td></tr>
1085 <tr class="memitem:gaaaf976e808e92970c4853195f46f86aa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__PTM__timer__functions.html#gaaaf976e808e92970c4853195f46f86aa">PTIM</a>   ((<a class="el" href="structTimer__Type.html">Timer_Type</a> *) TIMER_BASE )</td></tr>
1086 <tr class="memdesc:gaaaf976e808e92970c4853195f46f86aa"><td class="mdescLeft"> </td><td class="mdescRight">Timer register struct. <br /></td></tr>
1087 <tr class="separator:gaaaf976e808e92970c4853195f46f86aa"><td class="memSeparator" colspan="2"> </td></tr>
1088 <tr class="memitem:a6fa50338a28598914fac7b848df9dd0c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a6fa50338a28598914fac7b848df9dd0c">PTIM_CONTROL_Enable_Pos</a>   0U</td></tr>
1089 <tr class="separator:a6fa50338a28598914fac7b848df9dd0c"><td class="memSeparator" colspan="2"> </td></tr>
1090 <tr class="memitem:a6f4e1d90070433af2918698eddd65f49"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a6f4e1d90070433af2918698eddd65f49">PTIM_CONTROL_Enable_Msk</a>   (0x1U /*<< <a class="el" href="core__ca_8h.html#a6fa50338a28598914fac7b848df9dd0c">PTIM_CONTROL_Enable_Pos</a>*/)</td></tr>
1091 <tr class="separator:a6f4e1d90070433af2918698eddd65f49"><td class="memSeparator" colspan="2"> </td></tr>
1092 <tr class="memitem:ae969ab086f85072b7aaaf7fd4eabc3ff"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#ae969ab086f85072b7aaaf7fd4eabc3ff">PTIM_CONTROL_Enable</a>(x)   (((uint32_t)(((uint32_t)(x)) /*<< <a class="el" href="core__ca_8h.html#a6fa50338a28598914fac7b848df9dd0c">PTIM_CONTROL_Enable_Pos</a>*/)) & <a class="el" href="core__ca_8h.html#a6f4e1d90070433af2918698eddd65f49">PTIM_CONTROL_Enable_Msk</a>)</td></tr>
1093 <tr class="separator:ae969ab086f85072b7aaaf7fd4eabc3ff"><td class="memSeparator" colspan="2"> </td></tr>
1094 <tr class="memitem:a063285387241f2460fdade5b32c4dc46"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a063285387241f2460fdade5b32c4dc46">PTIM_CONTROL_AutoReload_Pos</a>   1U</td></tr>
1095 <tr class="separator:a063285387241f2460fdade5b32c4dc46"><td class="memSeparator" colspan="2"> </td></tr>
1096 <tr class="memitem:a22f2fb180a8e8e333469f3d185d74e95"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a22f2fb180a8e8e333469f3d185d74e95">PTIM_CONTROL_AutoReload_Msk</a>   (0x1U << <a class="el" href="core__ca_8h.html#a063285387241f2460fdade5b32c4dc46">PTIM_CONTROL_AutoReload_Pos</a>)</td></tr>
1097 <tr class="separator:a22f2fb180a8e8e333469f3d185d74e95"><td class="memSeparator" colspan="2"> </td></tr>
1098 <tr class="memitem:ae7744f04299efcff44461d22ab774673"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#ae7744f04299efcff44461d22ab774673">PTIM_CONTROL_AutoReload</a>(x)   (((uint32_t)(((uint32_t)(x)) << <a class="el" href="core__ca_8h.html#a063285387241f2460fdade5b32c4dc46">PTIM_CONTROL_AutoReload_Pos</a>)) & <a class="el" href="core__ca_8h.html#a22f2fb180a8e8e333469f3d185d74e95">PTIM_CONTROL_AutoReload_Msk</a>)</td></tr>
1099 <tr class="separator:ae7744f04299efcff44461d22ab774673"><td class="memSeparator" colspan="2"> </td></tr>
1100 <tr class="memitem:a0a4bf058b836c21a811c6619d9dcda03"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a0a4bf058b836c21a811c6619d9dcda03">PTIM_CONTROL_IRQenable_Pos</a>   2U</td></tr>
1101 <tr class="separator:a0a4bf058b836c21a811c6619d9dcda03"><td class="memSeparator" colspan="2"> </td></tr>
1102 <tr class="memitem:adc4ee5155209dad6bfdcc00e2cff8237"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#adc4ee5155209dad6bfdcc00e2cff8237">PTIM_CONTROL_IRQenable_Msk</a>   (0x1U << <a class="el" href="core__ca_8h.html#a0a4bf058b836c21a811c6619d9dcda03">PTIM_CONTROL_IRQenable_Pos</a>)</td></tr>
1103 <tr class="separator:adc4ee5155209dad6bfdcc00e2cff8237"><td class="memSeparator" colspan="2"> </td></tr>
1104 <tr class="memitem:ac2adbb60bcb8d5e8318e9604cee174ee"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#ac2adbb60bcb8d5e8318e9604cee174ee">PTIM_CONTROL_IRQenable</a>(x)   (((uint32_t)(((uint32_t)(x)) << <a class="el" href="core__ca_8h.html#a0a4bf058b836c21a811c6619d9dcda03">PTIM_CONTROL_IRQenable_Pos</a>)) & <a class="el" href="core__ca_8h.html#adc4ee5155209dad6bfdcc00e2cff8237">PTIM_CONTROL_IRQenable_Msk</a>)</td></tr>
1105 <tr class="separator:ac2adbb60bcb8d5e8318e9604cee174ee"><td class="memSeparator" colspan="2"> </td></tr>
1106 <tr class="memitem:a3c6fc3b64ce9dfd52988ca4b9252d49d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a3c6fc3b64ce9dfd52988ca4b9252d49d">PTIM_CONTROL_Prescaler_Pos</a>   8U</td></tr>
1107 <tr class="separator:a3c6fc3b64ce9dfd52988ca4b9252d49d"><td class="memSeparator" colspan="2"> </td></tr>
1108 <tr class="memitem:aa1fbcd0babcbbd47d0c0d5a914a04619"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#aa1fbcd0babcbbd47d0c0d5a914a04619">PTIM_CONTROL_Prescaler_Msk</a>   (0xFFU << <a class="el" href="core__ca_8h.html#a3c6fc3b64ce9dfd52988ca4b9252d49d">PTIM_CONTROL_Prescaler_Pos</a>)</td></tr>
1109 <tr class="separator:aa1fbcd0babcbbd47d0c0d5a914a04619"><td class="memSeparator" colspan="2"> </td></tr>
1110 <tr class="memitem:aa2ae1a6147e67806f0efc7e5d9d1b2bb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#aa2ae1a6147e67806f0efc7e5d9d1b2bb">PTIM_CONTROL_Prescaler</a>(x)   (((uint32_t)(((uint32_t)(x)) << <a class="el" href="core__ca_8h.html#a3c6fc3b64ce9dfd52988ca4b9252d49d">PTIM_CONTROL_Prescaler_Pos</a>)) & <a class="el" href="core__ca_8h.html#aa1fbcd0babcbbd47d0c0d5a914a04619">PTIM_CONTROL_Prescaler_Msk</a>)</td></tr>
1111 <tr class="separator:aa2ae1a6147e67806f0efc7e5d9d1b2bb"><td class="memSeparator" colspan="2"> </td></tr>
1112 <tr class="memitem:a766bde345c9066ff36955a46c575287b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a766bde345c9066ff36955a46c575287b">PTIM_WCONTROL_Enable_Pos</a>   0U</td></tr>
1113 <tr class="separator:a766bde345c9066ff36955a46c575287b"><td class="memSeparator" colspan="2"> </td></tr>
1114 <tr class="memitem:a3224c76fb25151decd85acaca3e07921"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a3224c76fb25151decd85acaca3e07921">PTIM_WCONTROL_Enable_Msk</a>   (0x1U /*<< <a class="el" href="core__ca_8h.html#a766bde345c9066ff36955a46c575287b">PTIM_WCONTROL_Enable_Pos</a>*/)</td></tr>
1115 <tr class="separator:a3224c76fb25151decd85acaca3e07921"><td class="memSeparator" colspan="2"> </td></tr>
1116 <tr class="memitem:a6b8afdf15f4c571bc4dc8dd68d94857b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a6b8afdf15f4c571bc4dc8dd68d94857b">PTIM_WCONTROL_Enable</a>(x)   (((uint32_t)(((uint32_t)(x)) /*<< <a class="el" href="core__ca_8h.html#a766bde345c9066ff36955a46c575287b">PTIM_WCONTROL_Enable_Pos</a>*/)) & <a class="el" href="core__ca_8h.html#a3224c76fb25151decd85acaca3e07921">PTIM_WCONTROL_Enable_Msk</a>)</td></tr>
1117 <tr class="separator:a6b8afdf15f4c571bc4dc8dd68d94857b"><td class="memSeparator" colspan="2"> </td></tr>
1118 <tr class="memitem:a92428db9bf62796b22fa4d03a0d44f8c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a92428db9bf62796b22fa4d03a0d44f8c">PTIM_WCONTROL_AutoReload_Pos</a>   1U</td></tr>
1119 <tr class="separator:a92428db9bf62796b22fa4d03a0d44f8c"><td class="memSeparator" colspan="2"> </td></tr>
1120 <tr class="memitem:acd877c3ae391c835308d6209991b3087"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#acd877c3ae391c835308d6209991b3087">PTIM_WCONTROL_AutoReload_Msk</a>   (0x1U << <a class="el" href="core__ca_8h.html#a92428db9bf62796b22fa4d03a0d44f8c">PTIM_WCONTROL_AutoReload_Pos</a>)</td></tr>
1121 <tr class="separator:acd877c3ae391c835308d6209991b3087"><td class="memSeparator" colspan="2"> </td></tr>
1122 <tr class="memitem:a354e11f2b72b0a78c1b5f97357498051"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a354e11f2b72b0a78c1b5f97357498051">PTIM_WCONTROL_AutoReload</a>(x)   (((uint32_t)(((uint32_t)(x)) << <a class="el" href="core__ca_8h.html#a92428db9bf62796b22fa4d03a0d44f8c">PTIM_WCONTROL_AutoReload_Pos</a>)) & <a class="el" href="core__ca_8h.html#acd877c3ae391c835308d6209991b3087">PTIM_WCONTROL_AutoReload_Msk</a>)</td></tr>
1123 <tr class="separator:a354e11f2b72b0a78c1b5f97357498051"><td class="memSeparator" colspan="2"> </td></tr>
1124 <tr class="memitem:a6b6e80f22db74334668eb35972d00075"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a6b6e80f22db74334668eb35972d00075">PTIM_WCONTROL_IRQenable_Pos</a>   2U</td></tr>
1125 <tr class="separator:a6b6e80f22db74334668eb35972d00075"><td class="memSeparator" colspan="2"> </td></tr>
1126 <tr class="memitem:af00fdab72c490423a4f7e5483a89ae05"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#af00fdab72c490423a4f7e5483a89ae05">PTIM_WCONTROL_IRQenable_Msk</a>   (0x1U << <a class="el" href="core__ca_8h.html#a6b6e80f22db74334668eb35972d00075">PTIM_WCONTROL_IRQenable_Pos</a>)</td></tr>
1127 <tr class="separator:af00fdab72c490423a4f7e5483a89ae05"><td class="memSeparator" colspan="2"> </td></tr>
1128 <tr class="memitem:aa8ce36df65589c55dbdbf86e9f82eff8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#aa8ce36df65589c55dbdbf86e9f82eff8">PTIM_WCONTROL_IRQenable</a>(x)   (((uint32_t)(((uint32_t)(x)) << <a class="el" href="core__ca_8h.html#a6b6e80f22db74334668eb35972d00075">PTIM_WCONTROL_IRQenable_Pos</a>)) & <a class="el" href="core__ca_8h.html#af00fdab72c490423a4f7e5483a89ae05">PTIM_WCONTROL_IRQenable_Msk</a>)</td></tr>
1129 <tr class="separator:aa8ce36df65589c55dbdbf86e9f82eff8"><td class="memSeparator" colspan="2"> </td></tr>
1130 <tr class="memitem:aa520a65ee0970978cccc6f71c4d7cf40"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#aa520a65ee0970978cccc6f71c4d7cf40">PTIM_WCONTROL_Mode_Pos</a>   3U</td></tr>
1131 <tr class="separator:aa520a65ee0970978cccc6f71c4d7cf40"><td class="memSeparator" colspan="2"> </td></tr>
1132 <tr class="memitem:a57e0ff6fa731293061548809f136db27"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a57e0ff6fa731293061548809f136db27">PTIM_WCONTROL_Mode_Msk</a>   (0x1U << <a class="el" href="core__ca_8h.html#aa520a65ee0970978cccc6f71c4d7cf40">PTIM_WCONTROL_Mode_Pos</a>)</td></tr>
1133 <tr class="separator:a57e0ff6fa731293061548809f136db27"><td class="memSeparator" colspan="2"> </td></tr>
1134 <tr class="memitem:a0002122226f327beb2448507434119dd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a0002122226f327beb2448507434119dd">PTIM_WCONTROL_Mode</a>(x)   (((uint32_t)(((uint32_t)(x)) << <a class="el" href="core__ca_8h.html#aa520a65ee0970978cccc6f71c4d7cf40">PTIM_WCONTROL_Mode_Pos</a>)) & <a class="el" href="core__ca_8h.html#a57e0ff6fa731293061548809f136db27">PTIM_WCONTROL_Mode_Msk</a>)</td></tr>
1135 <tr class="separator:a0002122226f327beb2448507434119dd"><td class="memSeparator" colspan="2"> </td></tr>
1136 <tr class="memitem:a699863868487b60d093aaa4acb476baf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a699863868487b60d093aaa4acb476baf">PTIM_WCONTROL_Presacler_Pos</a>   8U</td></tr>
1137 <tr class="separator:a699863868487b60d093aaa4acb476baf"><td class="memSeparator" colspan="2"> </td></tr>
1138 <tr class="memitem:a8517f58681a489fc2e7343740104b830"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a8517f58681a489fc2e7343740104b830">PTIM_WCONTROL_Presacler_Msk</a>   (0xFFU << <a class="el" href="core__ca_8h.html#a699863868487b60d093aaa4acb476baf">PTIM_WCONTROL_Presacler_Pos</a>)</td></tr>
1139 <tr class="separator:a8517f58681a489fc2e7343740104b830"><td class="memSeparator" colspan="2"> </td></tr>
1140 <tr class="memitem:a9de73ffcb171293679abe7e4868568cc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a9de73ffcb171293679abe7e4868568cc">PTIM_WCONTROL_Presacler</a>(x)   (((uint32_t)(((uint32_t)(x)) << <a class="el" href="core__ca_8h.html#a699863868487b60d093aaa4acb476baf">PTIM_WCONTROL_Presacler_Pos</a>)) & <a class="el" href="core__ca_8h.html#a8517f58681a489fc2e7343740104b830">PTIM_WCONTROL_Presacler_Msk</a>)</td></tr>
1141 <tr class="separator:a9de73ffcb171293679abe7e4868568cc"><td class="memSeparator" colspan="2"> </td></tr>
1142 <tr class="memitem:ab0090b3d580850c9ec8583ad2083de2a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#ab0090b3d580850c9ec8583ad2083de2a">PTIM_WISR_EventFlag_Pos</a>   0U</td></tr>
1143 <tr class="separator:ab0090b3d580850c9ec8583ad2083de2a"><td class="memSeparator" colspan="2"> </td></tr>
1144 <tr class="memitem:af7682c18d2684e3ef0b7a79a05800f62"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#af7682c18d2684e3ef0b7a79a05800f62">PTIM_WISR_EventFlag_Msk</a>   (0x1U /*<< <a class="el" href="core__ca_8h.html#ab0090b3d580850c9ec8583ad2083de2a">PTIM_WISR_EventFlag_Pos</a>*/)</td></tr>
1145 <tr class="separator:af7682c18d2684e3ef0b7a79a05800f62"><td class="memSeparator" colspan="2"> </td></tr>
1146 <tr class="memitem:a30b4ad11d0b222ba1c6138a245dd0a2d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a30b4ad11d0b222ba1c6138a245dd0a2d">PTIM_WISR_EventFlag</a>(x)   (((uint32_t)(((uint32_t)(x)) /*<< <a class="el" href="core__ca_8h.html#ab0090b3d580850c9ec8583ad2083de2a">PTIM_WISR_EventFlag_Pos</a>*/)) & <a class="el" href="core__ca_8h.html#af7682c18d2684e3ef0b7a79a05800f62">PTIM_WISR_EventFlag_Msk</a>)</td></tr>
1147 <tr class="separator:a30b4ad11d0b222ba1c6138a245dd0a2d"><td class="memSeparator" colspan="2"> </td></tr>
1148 <tr class="memitem:ab14433a719470079291e0e85afd3d4ce"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#ab14433a719470079291e0e85afd3d4ce">PTIM_WRESET_ResetFlag_Pos</a>   0U</td></tr>
1149 <tr class="separator:ab14433a719470079291e0e85afd3d4ce"><td class="memSeparator" colspan="2"> </td></tr>
1150 <tr class="memitem:a09ee8cf35de561687d0d2d5444557264"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a09ee8cf35de561687d0d2d5444557264">PTIM_WRESET_ResetFlag_Msk</a>   (0x1U /*<< <a class="el" href="core__ca_8h.html#ab14433a719470079291e0e85afd3d4ce">PTIM_WRESET_ResetFlag_Pos</a>*/)</td></tr>
1151 <tr class="separator:a09ee8cf35de561687d0d2d5444557264"><td class="memSeparator" colspan="2"> </td></tr>
1152 <tr class="memitem:a0d426f711743bb29171559c763d2b178"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a0d426f711743bb29171559c763d2b178">PTIM_WRESET_ResetFlag</a>(x)   (((uint32_t)(((uint32_t)(x)) /*<< <a class="el" href="core__ca_8h.html#ab14433a719470079291e0e85afd3d4ce">PTIM_WRESET_ResetFlag_Pos</a>*/)) & <a class="el" href="core__ca_8h.html#a09ee8cf35de561687d0d2d5444557264">PTIM_WRESET_ResetFlag_Msk</a>)</td></tr>
1153 <tr class="separator:a0d426f711743bb29171559c763d2b178"><td class="memSeparator" colspan="2"> </td></tr>
1154 <tr class="memitem:a647b0a71258678d75aed0aadd5801612"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a647b0a71258678d75aed0aadd5801612">GIC_SetSecurity</a>   <a class="el" href="core__ca_8h.html#ab875d63dc51a75149802945bb00e2695">GIC_SetGroup</a></td></tr>
1155 <tr class="separator:a647b0a71258678d75aed0aadd5801612"><td class="memSeparator" colspan="2"> </td></tr>
1156 <tr class="memitem:aea0bba954f8c3b032cf9a6540277ddef"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#aea0bba954f8c3b032cf9a6540277ddef">GIC_GetSecurity</a>   <a class="el" href="core__ca_8h.html#ae161d7a866cb61f92b808ae98fa7c812">GIC_GetGroup</a></td></tr>
1157 <tr class="separator:aea0bba954f8c3b032cf9a6540277ddef"><td class="memSeparator" colspan="2"> </td></tr>
1158 <tr class="memitem:ga4ab4ff3ff904df46da18f5532ceb1e89"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__defs__gr.html#ga4ab4ff3ff904df46da18f5532ceb1e89">SECTION_DESCRIPTOR</a>   (0x2)</td></tr>
1159 <tr class="separator:ga4ab4ff3ff904df46da18f5532ceb1e89"><td class="memSeparator" colspan="2"> </td></tr>
1160 <tr class="memitem:a16f225cca51a80c5cf1c9c002cfd2dba"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a16f225cca51a80c5cf1c9c002cfd2dba">SECTION_MASK</a>   (0xFFFFFFFC)</td></tr>
1161 <tr class="separator:a16f225cca51a80c5cf1c9c002cfd2dba"><td class="memSeparator" colspan="2"> </td></tr>
1162 <tr class="memitem:a3052ba3d97ad157189a6c6fce15b1b6a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a3052ba3d97ad157189a6c6fce15b1b6a">SECTION_TEXCB_MASK</a>   (0xFFFF8FF3)</td></tr>
1163 <tr class="separator:a3052ba3d97ad157189a6c6fce15b1b6a"><td class="memSeparator" colspan="2"> </td></tr>
1164 <tr class="memitem:gaa77545190c32bb2f4d2d86e41552daef"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__defs__gr.html#gaa77545190c32bb2f4d2d86e41552daef">SECTION_B_SHIFT</a>   (2)</td></tr>
1165 <tr class="separator:gaa77545190c32bb2f4d2d86e41552daef"><td class="memSeparator" colspan="2"> </td></tr>
1166 <tr class="memitem:gae0b3a2eccc4f9c249e928d359c43c20c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__defs__gr.html#gae0b3a2eccc4f9c249e928d359c43c20c">SECTION_C_SHIFT</a>   (3)</td></tr>
1167 <tr class="separator:gae0b3a2eccc4f9c249e928d359c43c20c"><td class="memSeparator" colspan="2"> </td></tr>
1168 <tr class="memitem:ad84432cb37ae093f7609f8f29f42c1f4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#ad84432cb37ae093f7609f8f29f42c1f4">SECTION_TEX0_SHIFT</a>   (12)</td></tr>
1169 <tr class="separator:ad84432cb37ae093f7609f8f29f42c1f4"><td class="memSeparator" colspan="2"> </td></tr>
1170 <tr class="memitem:a531cafc5eca8ade67a6fb83b35f8520e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a531cafc5eca8ade67a6fb83b35f8520e">SECTION_TEX1_SHIFT</a>   (13)</td></tr>
1171 <tr class="separator:a531cafc5eca8ade67a6fb83b35f8520e"><td class="memSeparator" colspan="2"> </td></tr>
1172 <tr class="memitem:a8a6d854746a9c0049f9a91188092a55f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a8a6d854746a9c0049f9a91188092a55f">SECTION_TEX2_SHIFT</a>   (14)</td></tr>
1173 <tr class="separator:a8a6d854746a9c0049f9a91188092a55f"><td class="memSeparator" colspan="2"> </td></tr>
1174 <tr class="memitem:a83cb551c9fa708e33082c682be614334"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a83cb551c9fa708e33082c682be614334">SECTION_XN_MASK</a>   (0xFFFFFFEF)</td></tr>
1175 <tr class="separator:a83cb551c9fa708e33082c682be614334"><td class="memSeparator" colspan="2"> </td></tr>
1176 <tr class="memitem:a6cdc2db0ca695fd1191305a13e66c0a7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a6cdc2db0ca695fd1191305a13e66c0a7">SECTION_XN_SHIFT</a>   (4)</td></tr>
1177 <tr class="separator:a6cdc2db0ca695fd1191305a13e66c0a7"><td class="memSeparator" colspan="2"> </td></tr>
1178 <tr class="memitem:a90a30c02512cbea24791212af9f2cd9f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a90a30c02512cbea24791212af9f2cd9f">SECTION_DOMAIN_MASK</a>   (0xFFFFFE1F)</td></tr>
1179 <tr class="separator:a90a30c02512cbea24791212af9f2cd9f"><td class="memSeparator" colspan="2"> </td></tr>
1180 <tr class="memitem:a70cc38b984789323feecd97033a66757"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a70cc38b984789323feecd97033a66757">SECTION_DOMAIN_SHIFT</a>   (5)</td></tr>
1181 <tr class="separator:a70cc38b984789323feecd97033a66757"><td class="memSeparator" colspan="2"> </td></tr>
1182 <tr class="memitem:ad32d146d84a9d7f964f28f1dadc98bcb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#ad32d146d84a9d7f964f28f1dadc98bcb">SECTION_P_MASK</a>   (0xFFFFFDFF)</td></tr>
1183 <tr class="separator:ad32d146d84a9d7f964f28f1dadc98bcb"><td class="memSeparator" colspan="2"> </td></tr>
1184 <tr class="memitem:a8f27fa21cb70abad114374f33a562988"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a8f27fa21cb70abad114374f33a562988">SECTION_P_SHIFT</a>   (9)</td></tr>
1185 <tr class="separator:a8f27fa21cb70abad114374f33a562988"><td class="memSeparator" colspan="2"> </td></tr>
1186 <tr class="memitem:a725efc96ea9aa940fefcf013bce6ca8c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a725efc96ea9aa940fefcf013bce6ca8c">SECTION_AP_MASK</a>   (0xFFFF73FF)</td></tr>
1187 <tr class="separator:a725efc96ea9aa940fefcf013bce6ca8c"><td class="memSeparator" colspan="2"> </td></tr>
1188 <tr class="memitem:a274fa608581b227182ce92adec4597b5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a274fa608581b227182ce92adec4597b5">SECTION_AP_SHIFT</a>   (10)</td></tr>
1189 <tr class="separator:a274fa608581b227182ce92adec4597b5"><td class="memSeparator" colspan="2"> </td></tr>
1190 <tr class="memitem:a1b8b0d00bfc7cbeed67b82db26d98195"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a1b8b0d00bfc7cbeed67b82db26d98195">SECTION_AP2_SHIFT</a>   (15)</td></tr>
1191 <tr class="separator:a1b8b0d00bfc7cbeed67b82db26d98195"><td class="memSeparator" colspan="2"> </td></tr>
1192 <tr class="memitem:a42d3645aad501af4ef447186c01685b7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a42d3645aad501af4ef447186c01685b7">SECTION_S_MASK</a>   (0xFFFEFFFF)</td></tr>
1193 <tr class="separator:a42d3645aad501af4ef447186c01685b7"><td class="memSeparator" colspan="2"> </td></tr>
1194 <tr class="memitem:a83a5fc538dad79161b122fb164d630fe"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a83a5fc538dad79161b122fb164d630fe">SECTION_S_SHIFT</a>   (16)</td></tr>
1195 <tr class="separator:a83a5fc538dad79161b122fb164d630fe"><td class="memSeparator" colspan="2"> </td></tr>
1196 <tr class="memitem:a01ceacdb3888d7cddcfeccfea9eb3658"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a01ceacdb3888d7cddcfeccfea9eb3658">SECTION_NG_MASK</a>   (0xFFFDFFFF)</td></tr>
1197 <tr class="separator:a01ceacdb3888d7cddcfeccfea9eb3658"><td class="memSeparator" colspan="2"> </td></tr>
1198 <tr class="memitem:a7af8adbf033d0a5c7b0889dd085041d1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a7af8adbf033d0a5c7b0889dd085041d1">SECTION_NG_SHIFT</a>   (17)</td></tr>
1199 <tr class="separator:a7af8adbf033d0a5c7b0889dd085041d1"><td class="memSeparator" colspan="2"> </td></tr>
1200 <tr class="memitem:a057533871fa1af6db7a27b39d976ac95"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a057533871fa1af6db7a27b39d976ac95">SECTION_NS_MASK</a>   (0xFFF7FFFF)</td></tr>
1201 <tr class="separator:a057533871fa1af6db7a27b39d976ac95"><td class="memSeparator" colspan="2"> </td></tr>
1202 <tr class="memitem:a502d55a107c909e15be282d8fbe4a8ce"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a502d55a107c909e15be282d8fbe4a8ce">SECTION_NS_SHIFT</a>   (19)</td></tr>
1203 <tr class="separator:a502d55a107c909e15be282d8fbe4a8ce"><td class="memSeparator" colspan="2"> </td></tr>
1204 <tr class="memitem:a82cb818cf0bcf9431ed9d0b52a39fe14"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a82cb818cf0bcf9431ed9d0b52a39fe14">PAGE_L1_DESCRIPTOR</a>   (0x1)</td></tr>
1205 <tr class="separator:a82cb818cf0bcf9431ed9d0b52a39fe14"><td class="memSeparator" colspan="2"> </td></tr>
1206 <tr class="memitem:a9fe764cc3a117a9ab93a301de8bceed1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a9fe764cc3a117a9ab93a301de8bceed1">PAGE_L1_MASK</a>   (0xFFFFFFFC)</td></tr>
1207 <tr class="separator:a9fe764cc3a117a9ab93a301de8bceed1"><td class="memSeparator" colspan="2"> </td></tr>
1208 <tr class="memitem:aefb20807cde04ea9fee6b197602348cf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#aefb20807cde04ea9fee6b197602348cf">PAGE_L2_4K_DESC</a>   (0x2)</td></tr>
1209 <tr class="separator:aefb20807cde04ea9fee6b197602348cf"><td class="memSeparator" colspan="2"> </td></tr>
1210 <tr class="memitem:abd292694d0155e3b0d4c12895a6c8fa6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#abd292694d0155e3b0d4c12895a6c8fa6">PAGE_L2_4K_MASK</a>   (0xFFFFFFFD)</td></tr>
1211 <tr class="separator:abd292694d0155e3b0d4c12895a6c8fa6"><td class="memSeparator" colspan="2"> </td></tr>
1212 <tr class="memitem:af38d8149733ba83690fd04ac1204bde1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#af38d8149733ba83690fd04ac1204bde1">PAGE_L2_64K_DESC</a>   (0x1)</td></tr>
1213 <tr class="separator:af38d8149733ba83690fd04ac1204bde1"><td class="memSeparator" colspan="2"> </td></tr>
1214 <tr class="memitem:ab3a82626ee70e38285852a1128b75c7a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#ab3a82626ee70e38285852a1128b75c7a">PAGE_L2_64K_MASK</a>   (0xFFFFFFFC)</td></tr>
1215 <tr class="separator:ab3a82626ee70e38285852a1128b75c7a"><td class="memSeparator" colspan="2"> </td></tr>
1216 <tr class="memitem:a234fceea67b5d6c41b0875852d86cc70"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a234fceea67b5d6c41b0875852d86cc70">PAGE_4K_TEXCB_MASK</a>   (0xFFFFFE33)</td></tr>
1217 <tr class="separator:a234fceea67b5d6c41b0875852d86cc70"><td class="memSeparator" colspan="2"> </td></tr>
1218 <tr class="memitem:a295b3b39fa6f7da3650a94551e28218b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a295b3b39fa6f7da3650a94551e28218b">PAGE_4K_B_SHIFT</a>   (2)</td></tr>
1219 <tr class="separator:a295b3b39fa6f7da3650a94551e28218b"><td class="memSeparator" colspan="2"> </td></tr>
1220 <tr class="memitem:a17ad8e75e5987a1f98adfc783640b75f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a17ad8e75e5987a1f98adfc783640b75f">PAGE_4K_C_SHIFT</a>   (3)</td></tr>
1221 <tr class="separator:a17ad8e75e5987a1f98adfc783640b75f"><td class="memSeparator" colspan="2"> </td></tr>
1222 <tr class="memitem:a8069f8882920692467749cc65f50e1f8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a8069f8882920692467749cc65f50e1f8">PAGE_4K_TEX0_SHIFT</a>   (6)</td></tr>
1223 <tr class="separator:a8069f8882920692467749cc65f50e1f8"><td class="memSeparator" colspan="2"> </td></tr>
1224 <tr class="memitem:ac0db1e472f79b641d0e51e4faa6e7e08"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#ac0db1e472f79b641d0e51e4faa6e7e08">PAGE_4K_TEX1_SHIFT</a>   (7)</td></tr>
1225 <tr class="separator:ac0db1e472f79b641d0e51e4faa6e7e08"><td class="memSeparator" colspan="2"> </td></tr>
1226 <tr class="memitem:a0e5c586a7e1928c7efa95e0d5f26e981"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a0e5c586a7e1928c7efa95e0d5f26e981">PAGE_4K_TEX2_SHIFT</a>   (8)</td></tr>
1227 <tr class="separator:a0e5c586a7e1928c7efa95e0d5f26e981"><td class="memSeparator" colspan="2"> </td></tr>
1228 <tr class="memitem:a666e7d1971403995104586f35d56590b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a666e7d1971403995104586f35d56590b">PAGE_64K_TEXCB_MASK</a>   (0xFFFF8FF3)</td></tr>
1229 <tr class="separator:a666e7d1971403995104586f35d56590b"><td class="memSeparator" colspan="2"> </td></tr>
1230 <tr class="memitem:aedc4abb2636443389128258bd74ce0bd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#aedc4abb2636443389128258bd74ce0bd">PAGE_64K_B_SHIFT</a>   (2)</td></tr>
1231 <tr class="separator:aedc4abb2636443389128258bd74ce0bd"><td class="memSeparator" colspan="2"> </td></tr>
1232 <tr class="memitem:abc1ce8b3d369d1e054fabf87514c4cd6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#abc1ce8b3d369d1e054fabf87514c4cd6">PAGE_64K_C_SHIFT</a>   (3)</td></tr>
1233 <tr class="separator:abc1ce8b3d369d1e054fabf87514c4cd6"><td class="memSeparator" colspan="2"> </td></tr>
1234 <tr class="memitem:ab4d67a1d5aa37623272abe4db32677ec"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#ab4d67a1d5aa37623272abe4db32677ec">PAGE_64K_TEX0_SHIFT</a>   (12)</td></tr>
1235 <tr class="separator:ab4d67a1d5aa37623272abe4db32677ec"><td class="memSeparator" colspan="2"> </td></tr>
1236 <tr class="memitem:a9c910152d27ce0a1552e3bb3c88782a6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a9c910152d27ce0a1552e3bb3c88782a6">PAGE_64K_TEX1_SHIFT</a>   (13)</td></tr>
1237 <tr class="separator:a9c910152d27ce0a1552e3bb3c88782a6"><td class="memSeparator" colspan="2"> </td></tr>
1238 <tr class="memitem:a8ec4dcea202b5ebc15419f7410a6c0b0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a8ec4dcea202b5ebc15419f7410a6c0b0">PAGE_64K_TEX2_SHIFT</a>   (14)</td></tr>
1239 <tr class="separator:a8ec4dcea202b5ebc15419f7410a6c0b0"><td class="memSeparator" colspan="2"> </td></tr>
1240 <tr class="memitem:aa488ef0c274f8ae125f61129745b1629"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#aa488ef0c274f8ae125f61129745b1629">PAGE_TEXCB_MASK</a>   (0xFFFF8FF3)</td></tr>
1241 <tr class="separator:aa488ef0c274f8ae125f61129745b1629"><td class="memSeparator" colspan="2"> </td></tr>
1242 <tr class="memitem:a3a660cdbc121e6510ed815fcb5bc8a44"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a3a660cdbc121e6510ed815fcb5bc8a44">PAGE_B_SHIFT</a>   (2)</td></tr>
1243 <tr class="separator:a3a660cdbc121e6510ed815fcb5bc8a44"><td class="memSeparator" colspan="2"> </td></tr>
1244 <tr class="memitem:ad9fc2f0cbe58ae4f1afea3cf9817b450"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#ad9fc2f0cbe58ae4f1afea3cf9817b450">PAGE_C_SHIFT</a>   (3)</td></tr>
1245 <tr class="separator:ad9fc2f0cbe58ae4f1afea3cf9817b450"><td class="memSeparator" colspan="2"> </td></tr>
1246 <tr class="memitem:a5833dc0a939f8d33299d8c8995a06589"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a5833dc0a939f8d33299d8c8995a06589">PAGE_TEX_SHIFT</a>   (12)</td></tr>
1247 <tr class="separator:a5833dc0a939f8d33299d8c8995a06589"><td class="memSeparator" colspan="2"> </td></tr>
1248 <tr class="memitem:a522f61b0d301d6f69c33a629e1699c7e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a522f61b0d301d6f69c33a629e1699c7e">PAGE_XN_4K_MASK</a>   (0xFFFFFFFE)</td></tr>
1249 <tr class="separator:a522f61b0d301d6f69c33a629e1699c7e"><td class="memSeparator" colspan="2"> </td></tr>
1250 <tr class="memitem:a9be26955f4a44c54008c55de61652539"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a9be26955f4a44c54008c55de61652539">PAGE_XN_4K_SHIFT</a>   (0)</td></tr>
1251 <tr class="separator:a9be26955f4a44c54008c55de61652539"><td class="memSeparator" colspan="2"> </td></tr>
1252 <tr class="memitem:ae0445cb4d6dc78359074cbb2776e3b5c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#ae0445cb4d6dc78359074cbb2776e3b5c">PAGE_XN_64K_MASK</a>   (0xFFFF7FFF)</td></tr>
1253 <tr class="separator:ae0445cb4d6dc78359074cbb2776e3b5c"><td class="memSeparator" colspan="2"> </td></tr>
1254 <tr class="memitem:ab34b65fbaaec1287daef459071c5c5c9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#ab34b65fbaaec1287daef459071c5c5c9">PAGE_XN_64K_SHIFT</a>   (15)</td></tr>
1255 <tr class="separator:ab34b65fbaaec1287daef459071c5c5c9"><td class="memSeparator" colspan="2"> </td></tr>
1256 <tr class="memitem:a0a48a4e79188149fbe886a698b6d9cb4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a0a48a4e79188149fbe886a698b6d9cb4">PAGE_DOMAIN_MASK</a>   (0xFFFFFE1F)</td></tr>
1257 <tr class="separator:a0a48a4e79188149fbe886a698b6d9cb4"><td class="memSeparator" colspan="2"> </td></tr>
1258 <tr class="memitem:ade787969e64896d0c8fe554f6aa1bc9e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#ade787969e64896d0c8fe554f6aa1bc9e">PAGE_DOMAIN_SHIFT</a>   (5)</td></tr>
1259 <tr class="separator:ade787969e64896d0c8fe554f6aa1bc9e"><td class="memSeparator" colspan="2"> </td></tr>
1260 <tr class="memitem:a604f4f13fcb78ff08d65ef4a1a3f7933"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a604f4f13fcb78ff08d65ef4a1a3f7933">PAGE_P_MASK</a>   (0xFFFFFDFF)</td></tr>
1261 <tr class="separator:a604f4f13fcb78ff08d65ef4a1a3f7933"><td class="memSeparator" colspan="2"> </td></tr>
1262 <tr class="memitem:a46a63dfcf084d48ccf27987bab48417a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a46a63dfcf084d48ccf27987bab48417a">PAGE_P_SHIFT</a>   (9)</td></tr>
1263 <tr class="separator:a46a63dfcf084d48ccf27987bab48417a"><td class="memSeparator" colspan="2"> </td></tr>
1264 <tr class="memitem:af7d3ee23adcaf9221967791f0e64d830"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#af7d3ee23adcaf9221967791f0e64d830">PAGE_AP_MASK</a>   (0xFFFFFDCF)</td></tr>
1265 <tr class="separator:af7d3ee23adcaf9221967791f0e64d830"><td class="memSeparator" colspan="2"> </td></tr>
1266 <tr class="memitem:afed0cfe8a8ab67fe26e961b876db13a3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#afed0cfe8a8ab67fe26e961b876db13a3">PAGE_AP_SHIFT</a>   (4)</td></tr>
1267 <tr class="separator:afed0cfe8a8ab67fe26e961b876db13a3"><td class="memSeparator" colspan="2"> </td></tr>
1268 <tr class="memitem:ad2d3cf0695c98dc2c4e37ebeb9235b2c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#ad2d3cf0695c98dc2c4e37ebeb9235b2c">PAGE_AP2_SHIFT</a>   (9)</td></tr>
1269 <tr class="separator:ad2d3cf0695c98dc2c4e37ebeb9235b2c"><td class="memSeparator" colspan="2"> </td></tr>
1270 <tr class="memitem:ac44cd885615a54131c372abfdc2d5c66"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#ac44cd885615a54131c372abfdc2d5c66">PAGE_S_MASK</a>   (0xFFFFFBFF)</td></tr>
1271 <tr class="separator:ac44cd885615a54131c372abfdc2d5c66"><td class="memSeparator" colspan="2"> </td></tr>
1272 <tr class="memitem:a1d9a3ed8dfa64aba257e2273d2613bce"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a1d9a3ed8dfa64aba257e2273d2613bce">PAGE_S_SHIFT</a>   (10)</td></tr>
1273 <tr class="separator:a1d9a3ed8dfa64aba257e2273d2613bce"><td class="memSeparator" colspan="2"> </td></tr>
1274 <tr class="memitem:add5d44ba746fe4d17d8b06a1086aa853"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#add5d44ba746fe4d17d8b06a1086aa853">PAGE_NG_MASK</a>   (0xFFFFF7FF)</td></tr>
1275 <tr class="separator:add5d44ba746fe4d17d8b06a1086aa853"><td class="memSeparator" colspan="2"> </td></tr>
1276 <tr class="memitem:a1d9196f2dd260244a4ad7e5b70b0e4c7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a1d9196f2dd260244a4ad7e5b70b0e4c7">PAGE_NG_SHIFT</a>   (11)</td></tr>
1277 <tr class="separator:a1d9196f2dd260244a4ad7e5b70b0e4c7"><td class="memSeparator" colspan="2"> </td></tr>
1278 <tr class="memitem:a618b1432615c3242f53360d4364c5797"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a618b1432615c3242f53360d4364c5797">PAGE_NS_MASK</a>   (0xFFFFFFF7)</td></tr>
1279 <tr class="separator:a618b1432615c3242f53360d4364c5797"><td class="memSeparator" colspan="2"> </td></tr>
1280 <tr class="memitem:a49740f5181adebe63b11c68db731bb0f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a49740f5181adebe63b11c68db731bb0f">PAGE_NS_SHIFT</a>   (3)</td></tr>
1281 <tr class="separator:a49740f5181adebe63b11c68db731bb0f"><td class="memSeparator" colspan="2"> </td></tr>
1282 <tr class="memitem:a8e51cfa91c0b6bbf1df1cff0bde44836"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a8e51cfa91c0b6bbf1df1cff0bde44836">OFFSET_1M</a>   (0x00100000)</td></tr>
1283 <tr class="separator:a8e51cfa91c0b6bbf1df1cff0bde44836"><td class="memSeparator" colspan="2"> </td></tr>
1284 <tr class="memitem:af19b9fb664a06a41562176a51c66fcff"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#af19b9fb664a06a41562176a51c66fcff">OFFSET_64K</a>   (0x00010000)</td></tr>
1285 <tr class="separator:af19b9fb664a06a41562176a51c66fcff"><td class="memSeparator" colspan="2"> </td></tr>
1286 <tr class="memitem:a121c645cdc91018720ceaf1d021fcd89"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a121c645cdc91018720ceaf1d021fcd89">OFFSET_4K</a>   (0x00001000)</td></tr>
1287 <tr class="separator:a121c645cdc91018720ceaf1d021fcd89"><td class="memSeparator" colspan="2"> </td></tr>
1288 <tr class="memitem:aba92665a24bc2ba8c49b9a0881c9df8a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#aba92665a24bc2ba8c49b9a0881c9df8a">DESCRIPTOR_FAULT</a>   (0x00000000)</td></tr>
1289 <tr class="separator:aba92665a24bc2ba8c49b9a0881c9df8a"><td class="memSeparator" colspan="2"> </td></tr>
1290 <tr class="memitem:ga220aab449cf3716723979d06666c2ebf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__defs__gr.html#ga220aab449cf3716723979d06666c2ebf">section_normal</a>(descriptor_l1, region)</td></tr>
1291 <tr class="separator:ga220aab449cf3716723979d06666c2ebf"><td class="memSeparator" colspan="2"> </td></tr>
1292 <tr class="memitem:a470b88645153aad94b09485f3108c641"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a470b88645153aad94b09485f3108c641">section_normal_nc</a>(descriptor_l1, region)</td></tr>
1293 <tr class="separator:a470b88645153aad94b09485f3108c641"><td class="memSeparator" colspan="2"> </td></tr>
1294 <tr class="memitem:gad598239f9bb9b6ae2bec8278305640b4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__defs__gr.html#gad598239f9bb9b6ae2bec8278305640b4">section_normal_cod</a>(descriptor_l1, region)</td></tr>
1295 <tr class="separator:gad598239f9bb9b6ae2bec8278305640b4"><td class="memSeparator" colspan="2"> </td></tr>
1296 <tr class="memitem:gaf95fa76d8f0f7ccfd2ebc00860af4f1d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__defs__gr.html#gaf95fa76d8f0f7ccfd2ebc00860af4f1d">section_normal_ro</a>(descriptor_l1, region)</td></tr>
1297 <tr class="separator:gaf95fa76d8f0f7ccfd2ebc00860af4f1d"><td class="memSeparator" colspan="2"> </td></tr>
1298 <tr class="memitem:ga1f2ce84e6ec5c150a2ffc05092ea6d0e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__defs__gr.html#ga1f2ce84e6ec5c150a2ffc05092ea6d0e">section_normal_rw</a>(descriptor_l1, region)</td></tr>
1299 <tr class="separator:ga1f2ce84e6ec5c150a2ffc05092ea6d0e"><td class="memSeparator" colspan="2"> </td></tr>
1300 <tr class="memitem:gaf77ecb86097e6e8cf5f6c7bb9d2740c9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__defs__gr.html#gaf77ecb86097e6e8cf5f6c7bb9d2740c9">section_so</a>(descriptor_l1, region)</td></tr>
1301 <tr class="separator:gaf77ecb86097e6e8cf5f6c7bb9d2740c9"><td class="memSeparator" colspan="2"> </td></tr>
1302 <tr class="memitem:ga1f66b52e152895af070514528763c272"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__defs__gr.html#ga1f66b52e152895af070514528763c272">section_device_ro</a>(descriptor_l1, region)</td></tr>
1303 <tr class="separator:ga1f66b52e152895af070514528763c272"><td class="memSeparator" colspan="2"> </td></tr>
1304 <tr class="memitem:ga33c6ad1fc06648fe50f8b21554c9bccb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__defs__gr.html#ga33c6ad1fc06648fe50f8b21554c9bccb">section_device_rw</a>(descriptor_l1, region)</td></tr>
1305 <tr class="separator:ga33c6ad1fc06648fe50f8b21554c9bccb"><td class="memSeparator" colspan="2"> </td></tr>
1306 <tr class="memitem:gafe66b1515bf7d251a9a3218162637a22"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__defs__gr.html#gafe66b1515bf7d251a9a3218162637a22">page4k_device_rw</a>(descriptor_l1, descriptor_l2, region)</td></tr>
1307 <tr class="separator:gafe66b1515bf7d251a9a3218162637a22"><td class="memSeparator" colspan="2"> </td></tr>
1308 <tr class="memitem:ga6c8c84bdeebf350d97eb3a99bd11845f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__defs__gr.html#ga6c8c84bdeebf350d97eb3a99bd11845f">page64k_device_rw</a>(descriptor_l1, descriptor_l2, region)</td></tr>
1309 <tr class="separator:ga6c8c84bdeebf350d97eb3a99bd11845f"><td class="memSeparator" colspan="2"> </td></tr>
1310 </table><table class="memberdecls">
1311 <tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="enum-members" name="enum-members"></a>
1312 Enumerations</h2></td></tr>
1313 <tr class="memitem:gab184b824a6d7cb728bd46c6abcd0c21a"><td class="memItemLeft" align="right" valign="top">enum  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__defs__gr.html#gab184b824a6d7cb728bd46c6abcd0c21a">mmu_region_size_Type</a> { <br />
1314   <a class="el" href="group__MMU__defs__gr.html#gab184b824a6d7cb728bd46c6abcd0c21aacb7227be6a36b93e485b62e3acddae51">SECTION</a>
1316   <a class="el" href="group__MMU__defs__gr.html#gab184b824a6d7cb728bd46c6abcd0c21aa99ce0ce05e9c418dc6bddcc47b2fa05a">PAGE_4k</a>
1318   <a class="el" href="group__MMU__defs__gr.html#gab184b824a6d7cb728bd46c6abcd0c21aafc53512bbf834739fcb97ad1c0f444fc">PAGE_64k</a>
1321 <tr class="separator:gab184b824a6d7cb728bd46c6abcd0c21a"><td class="memSeparator" colspan="2"> </td></tr>
1322 <tr class="memitem:ga83ac8de9263f89879079da521e86d5f2"><td class="memItemLeft" align="right" valign="top">enum  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__defs__gr.html#ga83ac8de9263f89879079da521e86d5f2">mmu_memory_Type</a> { <br />
1323   <a class="el" href="group__MMU__defs__gr.html#ga83ac8de9263f89879079da521e86d5f2a50d1448013c6f17125caee18aa418af7">NORMAL</a>
1325   <a class="el" href="group__MMU__defs__gr.html#ga83ac8de9263f89879079da521e86d5f2a28b8a7b4b6c2a98af7cf438255207174">DEVICE</a>
1327   <a class="el" href="group__MMU__defs__gr.html#ga83ac8de9263f89879079da521e86d5f2a9b78345535e6af3288cc69a572338808">SHARED_DEVICE</a>
1329   <a class="el" href="group__MMU__defs__gr.html#ga83ac8de9263f89879079da521e86d5f2a765e5cbb28da82e4d8f7e94fce32a7e0">NON_SHARED_DEVICE</a>
1331   <a class="el" href="group__MMU__defs__gr.html#ga83ac8de9263f89879079da521e86d5f2a0a4d347de23312717e6e57b04f0b014e">STRONGLY_ORDERED</a>
1334 <tr class="separator:ga83ac8de9263f89879079da521e86d5f2"><td class="memSeparator" colspan="2"> </td></tr>
1335 <tr class="memitem:ga11c86b7b193efb2c59b6a2179a02f584"><td class="memItemLeft" align="right" valign="top">enum  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__defs__gr.html#ga11c86b7b193efb2c59b6a2179a02f584">mmu_cacheability_Type</a> { <br />
1336   <a class="el" href="group__MMU__defs__gr.html#ga11c86b7b193efb2c59b6a2179a02f584a61a625191f7d288011e20bf2104ee151">NON_CACHEABLE</a>
1338   <a class="el" href="group__MMU__defs__gr.html#ga11c86b7b193efb2c59b6a2179a02f584a23294b86e8dbf6ff0fa98b678e8fd667">WB_WA</a>
1340   <a class="el" href="group__MMU__defs__gr.html#ga11c86b7b193efb2c59b6a2179a02f584ab044987527e64a06f65aa6f2ae0e4e7e">WT</a>
1342   <a class="el" href="group__MMU__defs__gr.html#ga11c86b7b193efb2c59b6a2179a02f584aca2e70f575679d6f3e2e340d1ede4f13">WB_NO_WA</a>
1345 <tr class="separator:ga11c86b7b193efb2c59b6a2179a02f584"><td class="memSeparator" colspan="2"> </td></tr>
1346 <tr class="memitem:ga06d94c0eaa22d713636acaff81485409"><td class="memItemLeft" align="right" valign="top">enum  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__defs__gr.html#ga06d94c0eaa22d713636acaff81485409">mmu_ecc_check_Type</a> { <br />
1347   <a class="el" href="group__MMU__defs__gr.html#ga06d94c0eaa22d713636acaff81485409a48ce2ec8ec49f0167a7d571081a9301f">ECC_DISABLED</a>
1349   <a class="el" href="group__MMU__defs__gr.html#ga06d94c0eaa22d713636acaff81485409af0e84d9540ed9d79f01caad9841d414d">ECC_ENABLED</a>
1352 <tr class="separator:ga06d94c0eaa22d713636acaff81485409"><td class="memSeparator" colspan="2"> </td></tr>
1353 <tr class="memitem:ga2fe1157deda82e66b9a1b19772309b63"><td class="memItemLeft" align="right" valign="top">enum  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__defs__gr.html#ga2fe1157deda82e66b9a1b19772309b63">mmu_execute_Type</a> { <br />
1354   <a class="el" href="group__MMU__defs__gr.html#ga2fe1157deda82e66b9a1b19772309b63a887d2cbfd9131de5cc3745731421b34b">EXECUTE</a>
1356   <a class="el" href="group__MMU__defs__gr.html#ga2fe1157deda82e66b9a1b19772309b63ad1d1eabb1b07ce896d5308a1144cf87a">NON_EXECUTE</a>
1359 <tr class="separator:ga2fe1157deda82e66b9a1b19772309b63"><td class="memSeparator" colspan="2"> </td></tr>
1360 <tr class="memitem:ga04160605fbe20914c8ef020430684a30"><td class="memItemLeft" align="right" valign="top">enum  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__defs__gr.html#ga04160605fbe20914c8ef020430684a30">mmu_global_Type</a> { <br />
1361   <a class="el" href="group__MMU__defs__gr.html#ga04160605fbe20914c8ef020430684a30afde1bb5ef04b28059e61df449501f1c0">GLOBAL</a>
1363   <a class="el" href="group__MMU__defs__gr.html#ga04160605fbe20914c8ef020430684a30a611c091f2869100296a98915a19ee018">NON_GLOBAL</a>
1366 <tr class="separator:ga04160605fbe20914c8ef020430684a30"><td class="memSeparator" colspan="2"> </td></tr>
1367 <tr class="memitem:gab884a11fa8d094573ab77fb1c0f8d8a7"><td class="memItemLeft" align="right" valign="top">enum  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__defs__gr.html#gab884a11fa8d094573ab77fb1c0f8d8a7">mmu_shared_Type</a> { <br />
1368   <a class="el" href="group__MMU__defs__gr.html#gab884a11fa8d094573ab77fb1c0f8d8a7a4a237208271e450df0a72c07169683b4">NON_SHARED</a>
1370   <a class="el" href="group__MMU__defs__gr.html#gab884a11fa8d094573ab77fb1c0f8d8a7a9c46e16a4ab019339596acadeefc8c53">SHARED</a>
1373 <tr class="separator:gab884a11fa8d094573ab77fb1c0f8d8a7"><td class="memSeparator" colspan="2"> </td></tr>
1374 <tr class="memitem:gac3d277641df9fb3bb3b555e2e79dd639"><td class="memItemLeft" align="right" valign="top">enum  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__defs__gr.html#gac3d277641df9fb3bb3b555e2e79dd639">mmu_secure_Type</a> { <br />
1375   <a class="el" href="group__MMU__defs__gr.html#gac3d277641df9fb3bb3b555e2e79dd639aa9dea2ba3f45f7d12b274eb6ab7d28d9">SECURE</a>
1377   <a class="el" href="group__MMU__defs__gr.html#gac3d277641df9fb3bb3b555e2e79dd639a9e08ca26fdda38ef731f13e4f058ef6f">NON_SECURE</a>
1380 <tr class="separator:gac3d277641df9fb3bb3b555e2e79dd639"><td class="memSeparator" colspan="2"> </td></tr>
1381 <tr class="memitem:ga2ee598252f996e4f96640b096291d280"><td class="memItemLeft" align="right" valign="top">enum  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__defs__gr.html#ga2ee598252f996e4f96640b096291d280">mmu_access_Type</a> { <br />
1382   <a class="el" href="group__MMU__defs__gr.html#ga2ee598252f996e4f96640b096291d280a4c66cd69a45985317939a53d820fb9da">NO_ACCESS</a>
1384   <a class="el" href="group__MMU__defs__gr.html#ga2ee598252f996e4f96640b096291d280aec2497e0c8af01c04bec31ec0d1d7847">RW</a>
1386   <a class="el" href="group__MMU__defs__gr.html#ga2ee598252f996e4f96640b096291d280acb9be765f361bb7efb9073730aac92c6">READ</a>
1389 <tr class="separator:ga2ee598252f996e4f96640b096291d280"><td class="memSeparator" colspan="2"> </td></tr>
1390 </table><table class="memberdecls">
1391 <tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="func-members" name="func-members"></a>
1392 Functions</h2></td></tr>
1393 <tr class="memitem:gaff8a4966eff1ada5cba80f2b689446db"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__L1__cache__functions.html#gaff8a4966eff1ada5cba80f2b689446db">L1C_EnableCaches</a> (void)</td></tr>
1394 <tr class="memdesc:gaff8a4966eff1ada5cba80f2b689446db"><td class="mdescLeft"> </td><td class="mdescRight">Enable Caches by setting I and C bits in SCTLR register. <br /></td></tr>
1395 <tr class="separator:gaff8a4966eff1ada5cba80f2b689446db"><td class="memSeparator" colspan="2"> </td></tr>
1396 <tr class="memitem:ga320ef6fd1dd65f2f82e64c096a4994a6"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__L1__cache__functions.html#ga320ef6fd1dd65f2f82e64c096a4994a6">L1C_DisableCaches</a> (void)</td></tr>
1397 <tr class="memdesc:ga320ef6fd1dd65f2f82e64c096a4994a6"><td class="mdescLeft"> </td><td class="mdescRight">Disable Caches by clearing I and C bits in SCTLR register. <br /></td></tr>
1398 <tr class="separator:ga320ef6fd1dd65f2f82e64c096a4994a6"><td class="memSeparator" colspan="2"> </td></tr>
1399 <tr class="memitem:gaa5fb36b4496e64472849f7811970c581"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__L1__cache__functions.html#gaa5fb36b4496e64472849f7811970c581">L1C_EnableBTAC</a> (void)</td></tr>
1400 <tr class="memdesc:gaa5fb36b4496e64472849f7811970c581"><td class="mdescLeft"> </td><td class="mdescRight">Enable Branch Prediction by setting Z bit in SCTLR register. <br /></td></tr>
1401 <tr class="separator:gaa5fb36b4496e64472849f7811970c581"><td class="memSeparator" colspan="2"> </td></tr>
1402 <tr class="memitem:gab8695cf1f4a7f3789b93c41dc4eeb51d"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__L1__cache__functions.html#gab8695cf1f4a7f3789b93c41dc4eeb51d">L1C_DisableBTAC</a> (void)</td></tr>
1403 <tr class="memdesc:gab8695cf1f4a7f3789b93c41dc4eeb51d"><td class="mdescLeft"> </td><td class="mdescRight">Disable Branch Prediction by clearing Z bit in SCTLR register. <br /></td></tr>
1404 <tr class="separator:gab8695cf1f4a7f3789b93c41dc4eeb51d"><td class="memSeparator" colspan="2"> </td></tr>
1405 <tr class="memitem:gad0d732293be6a928db184b59aadc1979"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__L1__cache__functions.html#gad0d732293be6a928db184b59aadc1979">L1C_InvalidateBTAC</a> (void)</td></tr>
1406 <tr class="memdesc:gad0d732293be6a928db184b59aadc1979"><td class="mdescLeft"> </td><td class="mdescRight">Invalidate entire branch predictor array. <br /></td></tr>
1407 <tr class="separator:gad0d732293be6a928db184b59aadc1979"><td class="memSeparator" colspan="2"> </td></tr>
1408 <tr class="memitem:a703d60af8047cc0d56b74d6814e375c5"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a703d60af8047cc0d56b74d6814e375c5">L1C_InvalidateICacheMVA</a> (void *va)</td></tr>
1409 <tr class="memdesc:a703d60af8047cc0d56b74d6814e375c5"><td class="mdescLeft"> </td><td class="mdescRight">Clean instruction cache line by address. <br /></td></tr>
1410 <tr class="separator:a703d60af8047cc0d56b74d6814e375c5"><td class="memSeparator" colspan="2"> </td></tr>
1411 <tr class="memitem:gac932810cfe83f087590859010972645e"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__L1__cache__functions.html#gac932810cfe83f087590859010972645e">L1C_InvalidateICacheAll</a> (void)</td></tr>
1412 <tr class="memdesc:gac932810cfe83f087590859010972645e"><td class="mdescLeft"> </td><td class="mdescRight">Invalidate the whole instruction cache. <br /></td></tr>
1413 <tr class="separator:gac932810cfe83f087590859010972645e"><td class="memSeparator" colspan="2"> </td></tr>
1414 <tr class="memitem:ga9eb6f0a7c9c04cc49efd964eb59ba26f"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__L1__cache__functions.html#ga9eb6f0a7c9c04cc49efd964eb59ba26f">L1C_CleanDCacheMVA</a> (void *va)</td></tr>
1415 <tr class="memdesc:ga9eb6f0a7c9c04cc49efd964eb59ba26f"><td class="mdescLeft"> </td><td class="mdescRight">Clean data cache line by address. <br /></td></tr>
1416 <tr class="separator:ga9eb6f0a7c9c04cc49efd964eb59ba26f"><td class="memSeparator" colspan="2"> </td></tr>
1417 <tr class="memitem:ga9209853937940991daf70edd6bc633fe"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__L1__cache__functions.html#ga9209853937940991daf70edd6bc633fe">L1C_InvalidateDCacheMVA</a> (void *va)</td></tr>
1418 <tr class="memdesc:ga9209853937940991daf70edd6bc633fe"><td class="mdescLeft"> </td><td class="mdescRight">Invalidate data cache line by address. <br /></td></tr>
1419 <tr class="separator:ga9209853937940991daf70edd6bc633fe"><td class="memSeparator" colspan="2"> </td></tr>
1420 <tr class="memitem:ga7646a5e01b529566968f393e485f46a2"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__L1__cache__functions.html#ga7646a5e01b529566968f393e485f46a2">L1C_CleanInvalidateDCacheMVA</a> (void *va)</td></tr>
1421 <tr class="memdesc:ga7646a5e01b529566968f393e485f46a2"><td class="mdescLeft"> </td><td class="mdescRight">Clean and Invalidate data cache by address. <br /></td></tr>
1422 <tr class="separator:ga7646a5e01b529566968f393e485f46a2"><td class="memSeparator" colspan="2"> </td></tr>
1423 <tr class="memitem:a35988a42567ca868bffd0b6171021ecb"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> uint8_t </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a35988a42567ca868bffd0b6171021ecb">__log2_up</a> (uint32_t n)</td></tr>
1424 <tr class="memdesc:a35988a42567ca868bffd0b6171021ecb"><td class="mdescLeft"> </td><td class="mdescRight">Calculate log2 rounded up. <br /></td></tr>
1425 <tr class="separator:a35988a42567ca868bffd0b6171021ecb"><td class="memSeparator" colspan="2"> </td></tr>
1426 <tr class="memitem:a5ace5c651cf18aaa7659e1fbe6e77988"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a5ace5c651cf18aaa7659e1fbe6e77988">__L1C_MaintainDCacheSetWay</a> (uint32_t level, uint32_t maint)</td></tr>
1427 <tr class="memdesc:a5ace5c651cf18aaa7659e1fbe6e77988"><td class="mdescLeft"> </td><td class="mdescRight">Apply cache maintenance to given cache level. <br /></td></tr>
1428 <tr class="separator:a5ace5c651cf18aaa7659e1fbe6e77988"><td class="memSeparator" colspan="2"> </td></tr>
1429 <tr class="memitem:ga30d7632156a30a3b75064f6d15b8f850"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__L1__cache__functions.html#ga30d7632156a30a3b75064f6d15b8f850">L1C_CleanInvalidateCache</a> (uint32_t op)</td></tr>
1430 <tr class="memdesc:ga30d7632156a30a3b75064f6d15b8f850"><td class="mdescLeft"> </td><td class="mdescRight">Clean and Invalidate the entire data or unified cache. <br /></td></tr>
1431 <tr class="separator:ga30d7632156a30a3b75064f6d15b8f850"><td class="memSeparator" colspan="2"> </td></tr>
1432 <tr class="memitem:gae895f75c4f3539058232f555d79e5df3"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__L1__cache__functions.html#gae895f75c4f3539058232f555d79e5df3">L1C_InvalidateDCacheAll</a> (void)</td></tr>
1433 <tr class="memdesc:gae895f75c4f3539058232f555d79e5df3"><td class="mdescLeft"> </td><td class="mdescRight">Invalidate the whole data cache. <br /></td></tr>
1434 <tr class="separator:gae895f75c4f3539058232f555d79e5df3"><td class="memSeparator" colspan="2"> </td></tr>
1435 <tr class="memitem:ga70359d824bf26f376e3d7cb9c787da27"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__L1__cache__functions.html#ga70359d824bf26f376e3d7cb9c787da27">L1C_CleanDCacheAll</a> (void)</td></tr>
1436 <tr class="memdesc:ga70359d824bf26f376e3d7cb9c787da27"><td class="mdescLeft"> </td><td class="mdescRight">Clean the whole data cache. <br /></td></tr>
1437 <tr class="separator:ga70359d824bf26f376e3d7cb9c787da27"><td class="memSeparator" colspan="2"> </td></tr>
1438 <tr class="memitem:ga92b5babf7317abe3815f61a2731735c3"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__comp__cntrl__gr.html#gab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__L1__cache__functions.html#ga92b5babf7317abe3815f61a2731735c3">L1C_CleanInvalidateDCacheAll</a> (void)</td></tr>
1439 <tr class="memdesc:ga92b5babf7317abe3815f61a2731735c3"><td class="mdescLeft"> </td><td class="mdescRight">Clean and invalidate the whole data cache. <br /></td></tr>
1440 <tr class="separator:ga92b5babf7317abe3815f61a2731735c3"><td class="memSeparator" colspan="2"> </td></tr>
1441 <tr class="memitem:ga164c59c55e2d18bf8a94dc91c0f4ce68"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__L2__cache__functions.html#ga164c59c55e2d18bf8a94dc91c0f4ce68">L2C_Sync</a> (void)</td></tr>
1442 <tr class="memdesc:ga164c59c55e2d18bf8a94dc91c0f4ce68"><td class="mdescLeft"> </td><td class="mdescRight">Cache Sync operation by writing CACHE_SYNC register. <br /></td></tr>
1443 <tr class="separator:ga164c59c55e2d18bf8a94dc91c0f4ce68"><td class="memSeparator" colspan="2"> </td></tr>
1444 <tr class="memitem:ga75af64212e1d3d0b3ade860c365e95b3"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE int </td><td class="memItemRight" valign="bottom"><a class="el" href="group__L2__cache__functions.html#ga75af64212e1d3d0b3ade860c365e95b3">L2C_GetID</a> (void)</td></tr>
1445 <tr class="memdesc:ga75af64212e1d3d0b3ade860c365e95b3"><td class="mdescLeft"> </td><td class="mdescRight">Read cache controller cache ID from CACHE_ID register. <br /></td></tr>
1446 <tr class="separator:ga75af64212e1d3d0b3ade860c365e95b3"><td class="memSeparator" colspan="2"> </td></tr>
1447 <tr class="memitem:ga0c334fa25720d77e78cfa187bdf833be"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE int </td><td class="memItemRight" valign="bottom"><a class="el" href="group__L2__cache__functions.html#ga0c334fa25720d77e78cfa187bdf833be">L2C_GetType</a> (void)</td></tr>
1448 <tr class="memdesc:ga0c334fa25720d77e78cfa187bdf833be"><td class="mdescLeft"> </td><td class="mdescRight">Read cache controller cache type from CACHE_TYPE register. <br /></td></tr>
1449 <tr class="separator:ga0c334fa25720d77e78cfa187bdf833be"><td class="memSeparator" colspan="2"> </td></tr>
1450 <tr class="memitem:ga5b0ea2db52d137b5531ce568479c9d17"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__L2__cache__functions.html#ga5b0ea2db52d137b5531ce568479c9d17">L2C_InvAllByWay</a> (void)</td></tr>
1451 <tr class="memdesc:ga5b0ea2db52d137b5531ce568479c9d17"><td class="mdescLeft"> </td><td class="mdescRight">Invalidate all cache by way. <br /></td></tr>
1452 <tr class="separator:ga5b0ea2db52d137b5531ce568479c9d17"><td class="memSeparator" colspan="2"> </td></tr>
1453 <tr class="memitem:gabd0a9b10926537fa283c0bb30d54abc7"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__L2__cache__functions.html#gabd0a9b10926537fa283c0bb30d54abc7">L2C_CleanInvAllByWay</a> (void)</td></tr>
1454 <tr class="memdesc:gabd0a9b10926537fa283c0bb30d54abc7"><td class="mdescLeft"> </td><td class="mdescRight">Clean and Invalidate all cache by way. <br /></td></tr>
1455 <tr class="separator:gabd0a9b10926537fa283c0bb30d54abc7"><td class="memSeparator" colspan="2"> </td></tr>
1456 <tr class="memitem:ga720c36b4cd1d6c070ed0d2c49cffd7e1"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__L2__cache__functions.html#ga720c36b4cd1d6c070ed0d2c49cffd7e1">L2C_Enable</a> (void)</td></tr>
1457 <tr class="memdesc:ga720c36b4cd1d6c070ed0d2c49cffd7e1"><td class="mdescLeft"> </td><td class="mdescRight">Enable Level 2 Cache. <br /></td></tr>
1458 <tr class="separator:ga720c36b4cd1d6c070ed0d2c49cffd7e1"><td class="memSeparator" colspan="2"> </td></tr>
1459 <tr class="memitem:ga66767e7f30f52d72de72231b2d6abd34"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__L2__cache__functions.html#ga66767e7f30f52d72de72231b2d6abd34">L2C_Disable</a> (void)</td></tr>
1460 <tr class="memdesc:ga66767e7f30f52d72de72231b2d6abd34"><td class="mdescLeft"> </td><td class="mdescRight">Disable Level 2 Cache. <br /></td></tr>
1461 <tr class="separator:ga66767e7f30f52d72de72231b2d6abd34"><td class="memSeparator" colspan="2"> </td></tr>
1462 <tr class="memitem:ga4cf213e72c97776def35ab8223face82"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__L2__cache__functions.html#ga4cf213e72c97776def35ab8223face82">L2C_InvPa</a> (void *pa)</td></tr>
1463 <tr class="memdesc:ga4cf213e72c97776def35ab8223face82"><td class="mdescLeft"> </td><td class="mdescRight">Invalidate cache by physical address. <br /></td></tr>
1464 <tr class="separator:ga4cf213e72c97776def35ab8223face82"><td class="memSeparator" colspan="2"> </td></tr>
1465 <tr class="memitem:ga242f6fa13f33e7d5cdd7d92935d52f5f"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__L2__cache__functions.html#ga242f6fa13f33e7d5cdd7d92935d52f5f">L2C_CleanPa</a> (void *pa)</td></tr>
1466 <tr class="memdesc:ga242f6fa13f33e7d5cdd7d92935d52f5f"><td class="mdescLeft"> </td><td class="mdescRight">Clean cache by physical address. <br /></td></tr>
1467 <tr class="separator:ga242f6fa13f33e7d5cdd7d92935d52f5f"><td class="memSeparator" colspan="2"> </td></tr>
1468 <tr class="memitem:gaaff11c6afa9eaacb4cdfcfe5c36f57eb"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__L2__cache__functions.html#gaaff11c6afa9eaacb4cdfcfe5c36f57eb">L2C_CleanInvPa</a> (void *pa)</td></tr>
1469 <tr class="memdesc:gaaff11c6afa9eaacb4cdfcfe5c36f57eb"><td class="mdescLeft"> </td><td class="mdescRight">Clean and invalidate cache by physical address. <br /></td></tr>
1470 <tr class="separator:gaaff11c6afa9eaacb4cdfcfe5c36f57eb"><td class="memSeparator" colspan="2"> </td></tr>
1471 <tr class="memitem:ga0f44df6823e90178183257e096e5cac6"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#ga0f44df6823e90178183257e096e5cac6">GIC_EnableDistributor</a> (void)</td></tr>
1472 <tr class="memdesc:ga0f44df6823e90178183257e096e5cac6"><td class="mdescLeft"> </td><td class="mdescRight">Enable the interrupt distributor using the GIC's CTLR register. <br /></td></tr>
1473 <tr class="separator:ga0f44df6823e90178183257e096e5cac6"><td class="memSeparator" colspan="2"> </td></tr>
1474 <tr class="memitem:ga363311538d4a4d750197b9936505d466"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#ga363311538d4a4d750197b9936505d466">GIC_DisableDistributor</a> (void)</td></tr>
1475 <tr class="memdesc:ga363311538d4a4d750197b9936505d466"><td class="mdescLeft"> </td><td class="mdescRight">Disable the interrupt distributor using the GIC's CTLR register. <br /></td></tr>
1476 <tr class="separator:ga363311538d4a4d750197b9936505d466"><td class="memSeparator" colspan="2"> </td></tr>
1477 <tr class="memitem:ga7d93d39736ef5e379e6511430ee6e75f"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#ga7d93d39736ef5e379e6511430ee6e75f">GIC_DistributorInfo</a> (void)</td></tr>
1478 <tr class="memdesc:ga7d93d39736ef5e379e6511430ee6e75f"><td class="mdescLeft"> </td><td class="mdescRight">Read the GIC's TYPER register. <br /></td></tr>
1479 <tr class="separator:ga7d93d39736ef5e379e6511430ee6e75f"><td class="memSeparator" colspan="2"> </td></tr>
1480 <tr class="memitem:ga1481d0cdf78f8c93fb2a710a519c4dc6"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#ga1481d0cdf78f8c93fb2a710a519c4dc6">GIC_DistributorImplementer</a> (void)</td></tr>
1481 <tr class="memdesc:ga1481d0cdf78f8c93fb2a710a519c4dc6"><td class="mdescLeft"> </td><td class="mdescRight">Reads the GIC's IIDR register. <br /></td></tr>
1482 <tr class="separator:ga1481d0cdf78f8c93fb2a710a519c4dc6"><td class="memSeparator" colspan="2"> </td></tr>
1483 <tr class="memitem:gae86bba705d0d4ef812b84d29d7b3ca2b"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#gae86bba705d0d4ef812b84d29d7b3ca2b">GIC_SetTarget</a> (<a class="el" href="group__irq__ctrl__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn, uint32_t cpu_target)</td></tr>
1484 <tr class="memdesc:gae86bba705d0d4ef812b84d29d7b3ca2b"><td class="mdescLeft"> </td><td class="mdescRight">Sets the GIC's ITARGETSR register for the given interrupt. <br /></td></tr>
1485 <tr class="separator:gae86bba705d0d4ef812b84d29d7b3ca2b"><td class="memSeparator" colspan="2"> </td></tr>
1486 <tr class="memitem:gafccf881f9517592f30489bcabcb738a8"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#gafccf881f9517592f30489bcabcb738a8">GIC_GetTarget</a> (<a class="el" href="group__irq__ctrl__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn)</td></tr>
1487 <tr class="memdesc:gafccf881f9517592f30489bcabcb738a8"><td class="mdescLeft"> </td><td class="mdescRight">Read the GIC's ITARGETSR register. <br /></td></tr>
1488 <tr class="separator:gafccf881f9517592f30489bcabcb738a8"><td class="memSeparator" colspan="2"> </td></tr>
1489 <tr class="memitem:ga758e5600d7f891e4f2f551bb45d07fce"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#ga758e5600d7f891e4f2f551bb45d07fce">GIC_EnableInterface</a> (void)</td></tr>
1490 <tr class="memdesc:ga758e5600d7f891e4f2f551bb45d07fce"><td class="mdescLeft"> </td><td class="mdescRight">Enable the CPU's interrupt interface. <br /></td></tr>
1491 <tr class="separator:ga758e5600d7f891e4f2f551bb45d07fce"><td class="memSeparator" colspan="2"> </td></tr>
1492 <tr class="memitem:ga0605877ad627c1f4320e518725fd103e"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#ga0605877ad627c1f4320e518725fd103e">GIC_DisableInterface</a> (void)</td></tr>
1493 <tr class="memdesc:ga0605877ad627c1f4320e518725fd103e"><td class="mdescLeft"> </td><td class="mdescRight">Disable the CPU's interrupt interface. <br /></td></tr>
1494 <tr class="separator:ga0605877ad627c1f4320e518725fd103e"><td class="memSeparator" colspan="2"> </td></tr>
1495 <tr class="memitem:gafc08bbc58b25fef0d24003313fd16eb8"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE <a class="el" href="group__irq__ctrl__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#gafc08bbc58b25fef0d24003313fd16eb8">GIC_AcknowledgePending</a> (void)</td></tr>
1496 <tr class="memdesc:gafc08bbc58b25fef0d24003313fd16eb8"><td class="mdescLeft"> </td><td class="mdescRight">Read the CPU's IAR register. <br /></td></tr>
1497 <tr class="separator:gafc08bbc58b25fef0d24003313fd16eb8"><td class="memSeparator" colspan="2"> </td></tr>
1498 <tr class="memitem:gac23f090f572a058b4a737f6613ded9cd"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#gac23f090f572a058b4a737f6613ded9cd">GIC_EndInterrupt</a> (<a class="el" href="group__irq__ctrl__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn)</td></tr>
1499 <tr class="memdesc:gac23f090f572a058b4a737f6613ded9cd"><td class="mdescLeft"> </td><td class="mdescRight">Writes the given interrupt number to the CPU's EOIR register. <br /></td></tr>
1500 <tr class="separator:gac23f090f572a058b4a737f6613ded9cd"><td class="memSeparator" colspan="2"> </td></tr>
1501 <tr class="memitem:gaeba215d9c4ec3599e0a168800288c3f3"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#gaeba215d9c4ec3599e0a168800288c3f3">GIC_EnableIRQ</a> (<a class="el" href="group__irq__ctrl__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn)</td></tr>
1502 <tr class="memdesc:gaeba215d9c4ec3599e0a168800288c3f3"><td class="mdescLeft"> </td><td class="mdescRight">Enables the given interrupt using GIC's ISENABLER register. <br /></td></tr>
1503 <tr class="separator:gaeba215d9c4ec3599e0a168800288c3f3"><td class="memSeparator" colspan="2"> </td></tr>
1504 <tr class="memitem:abcd7d576ea634b1a708db9fda95d09df"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#abcd7d576ea634b1a708db9fda95d09df">GIC_GetEnableIRQ</a> (<a class="el" href="group__irq__ctrl__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn)</td></tr>
1505 <tr class="memdesc:abcd7d576ea634b1a708db9fda95d09df"><td class="mdescLeft"> </td><td class="mdescRight">Get interrupt enable status using GIC's ISENABLER register. <br /></td></tr>
1506 <tr class="separator:abcd7d576ea634b1a708db9fda95d09df"><td class="memSeparator" colspan="2"> </td></tr>
1507 <tr class="memitem:ga2102399d255690c0674209a6faeec13d"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#ga2102399d255690c0674209a6faeec13d">GIC_DisableIRQ</a> (<a class="el" href="group__irq__ctrl__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn)</td></tr>
1508 <tr class="memdesc:ga2102399d255690c0674209a6faeec13d"><td class="mdescLeft"> </td><td class="mdescRight">Disables the given interrupt using GIC's ICENABLER register. <br /></td></tr>
1509 <tr class="separator:ga2102399d255690c0674209a6faeec13d"><td class="memSeparator" colspan="2"> </td></tr>
1510 <tr class="memitem:ab726a01df6ee9a480cc73910a06ddfb7"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#ab726a01df6ee9a480cc73910a06ddfb7">GIC_GetPendingIRQ</a> (<a class="el" href="group__irq__ctrl__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn)</td></tr>
1511 <tr class="memdesc:ab726a01df6ee9a480cc73910a06ddfb7"><td class="mdescLeft"> </td><td class="mdescRight">Get interrupt pending status from GIC's ISPENDR register. <br /></td></tr>
1512 <tr class="separator:ab726a01df6ee9a480cc73910a06ddfb7"><td class="memSeparator" colspan="2"> </td></tr>
1513 <tr class="memitem:ga18fbddf7f3594df141c97f61a71da47c"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#ga18fbddf7f3594df141c97f61a71da47c">GIC_SetPendingIRQ</a> (<a class="el" href="group__irq__ctrl__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn)</td></tr>
1514 <tr class="memdesc:ga18fbddf7f3594df141c97f61a71da47c"><td class="mdescLeft"> </td><td class="mdescRight">Sets the given interrupt as pending using GIC's ISPENDR register. <br /></td></tr>
1515 <tr class="separator:ga18fbddf7f3594df141c97f61a71da47c"><td class="memSeparator" colspan="2"> </td></tr>
1516 <tr class="memitem:ga5ad17ad70f23d1ff36015ffac33d383d"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#ga5ad17ad70f23d1ff36015ffac33d383d">GIC_ClearPendingIRQ</a> (<a class="el" href="group__irq__ctrl__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn)</td></tr>
1517 <tr class="memdesc:ga5ad17ad70f23d1ff36015ffac33d383d"><td class="mdescLeft"> </td><td class="mdescRight">Clears the given interrupt from being pending using GIC's ICPENDR register. <br /></td></tr>
1518 <tr class="separator:ga5ad17ad70f23d1ff36015ffac33d383d"><td class="memSeparator" colspan="2"> </td></tr>
1519 <tr class="memitem:a5dffcd04b18d2c3ee5a410e185ce5108"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE void </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a5dffcd04b18d2c3ee5a410e185ce5108">GIC_SetConfiguration</a> (<a class="el" href="group__irq__ctrl__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn, uint32_t int_config)</td></tr>
1520 <tr class="memdesc:a5dffcd04b18d2c3ee5a410e185ce5108"><td class="mdescLeft"> </td><td class="mdescRight">Sets the interrupt configuration using GIC's ICFGR register. <br /></td></tr>
1521 <tr class="separator:a5dffcd04b18d2c3ee5a410e185ce5108"><td class="memSeparator" colspan="2"> </td></tr>
1522 <tr class="memitem:a43cfac7327b49e2a89d63abc99b6b06a"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a43cfac7327b49e2a89d63abc99b6b06a">GIC_GetConfiguration</a> (<a class="el" href="group__irq__ctrl__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn)</td></tr>
1523 <tr class="memdesc:a43cfac7327b49e2a89d63abc99b6b06a"><td class="mdescLeft"> </td><td class="mdescRight">Get the interrupt configuration from the GIC's ICFGR register. <br /></td></tr>
1524 <tr class="separator:a43cfac7327b49e2a89d63abc99b6b06a"><td class="memSeparator" colspan="2"> </td></tr>
1525 <tr class="memitem:ga27b9862b58290276851ec669cabf0f71"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#ga27b9862b58290276851ec669cabf0f71">GIC_SetPriority</a> (<a class="el" href="group__irq__ctrl__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn, uint32_t priority)</td></tr>
1526 <tr class="memdesc:ga27b9862b58290276851ec669cabf0f71"><td class="mdescLeft"> </td><td class="mdescRight">Set the priority for the given interrupt in the GIC's IPRIORITYR register. <br /></td></tr>
1527 <tr class="separator:ga27b9862b58290276851ec669cabf0f71"><td class="memSeparator" colspan="2"> </td></tr>
1528 <tr class="memitem:ga397048004654f792649742f95bf8ae67"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#ga397048004654f792649742f95bf8ae67">GIC_GetPriority</a> (<a class="el" href="group__irq__ctrl__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn)</td></tr>
1529 <tr class="memdesc:ga397048004654f792649742f95bf8ae67"><td class="mdescLeft"> </td><td class="mdescRight">Read the current interrupt priority from GIC's IPRIORITYR register. <br /></td></tr>
1530 <tr class="separator:ga397048004654f792649742f95bf8ae67"><td class="memSeparator" colspan="2"> </td></tr>
1531 <tr class="memitem:gaa5eb0e76dbc89596e1ce47ddb9edc4a0"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#gaa5eb0e76dbc89596e1ce47ddb9edc4a0">GIC_SetInterfacePriorityMask</a> (uint32_t priority)</td></tr>
1532 <tr class="memdesc:gaa5eb0e76dbc89596e1ce47ddb9edc4a0"><td class="mdescLeft"> </td><td class="mdescRight">Set the interrupt priority mask using CPU's PMR register. <br /></td></tr>
1533 <tr class="separator:gaa5eb0e76dbc89596e1ce47ddb9edc4a0"><td class="memSeparator" colspan="2"> </td></tr>
1534 <tr class="memitem:ga2c5f9e5637560fc9d5c29d772580a728"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#ga2c5f9e5637560fc9d5c29d772580a728">GIC_GetInterfacePriorityMask</a> (void)</td></tr>
1535 <tr class="memdesc:ga2c5f9e5637560fc9d5c29d772580a728"><td class="mdescLeft"> </td><td class="mdescRight">Read the current interrupt priority mask from CPU's PMR register. <br /></td></tr>
1536 <tr class="separator:ga2c5f9e5637560fc9d5c29d772580a728"><td class="memSeparator" colspan="2"> </td></tr>
1537 <tr class="memitem:ga5dfedeb5403656a77e0fef4e1cc2c0c6"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#ga5dfedeb5403656a77e0fef4e1cc2c0c6">GIC_SetBinaryPoint</a> (uint32_t binary_point)</td></tr>
1538 <tr class="memdesc:ga5dfedeb5403656a77e0fef4e1cc2c0c6"><td class="mdescLeft"> </td><td class="mdescRight">Configures the group priority and subpriority split point using CPU's BPR register. <br /></td></tr>
1539 <tr class="separator:ga5dfedeb5403656a77e0fef4e1cc2c0c6"><td class="memSeparator" colspan="2"> </td></tr>
1540 <tr class="memitem:gaa7046d8206ddd4696716726e68f85906"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#gaa7046d8206ddd4696716726e68f85906">GIC_GetBinaryPoint</a> (void)</td></tr>
1541 <tr class="memdesc:gaa7046d8206ddd4696716726e68f85906"><td class="mdescLeft"> </td><td class="mdescRight">Read the current group priority and subpriority split point from CPU's BPR register. <br /></td></tr>
1542 <tr class="separator:gaa7046d8206ddd4696716726e68f85906"><td class="memSeparator" colspan="2"> </td></tr>
1543 <tr class="memitem:gabc88483ecf94a2c222b644ecfa60eb9f"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#gabc88483ecf94a2c222b644ecfa60eb9f">GIC_GetIRQStatus</a> (<a class="el" href="group__irq__ctrl__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn)</td></tr>
1544 <tr class="memdesc:gabc88483ecf94a2c222b644ecfa60eb9f"><td class="mdescLeft"> </td><td class="mdescRight">Get the status for a given interrupt. <br /></td></tr>
1545 <tr class="separator:gabc88483ecf94a2c222b644ecfa60eb9f"><td class="memSeparator" colspan="2"> </td></tr>
1546 <tr class="memitem:ga2de8850780af26e802ee4cc43e9da6e9"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#ga2de8850780af26e802ee4cc43e9da6e9">GIC_SendSGI</a> (<a class="el" href="group__irq__ctrl__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn, uint32_t target_list, uint32_t filter_list)</td></tr>
1547 <tr class="memdesc:ga2de8850780af26e802ee4cc43e9da6e9"><td class="mdescLeft"> </td><td class="mdescRight">Generate a software interrupt using GIC's SGIR register. <br /></td></tr>
1548 <tr class="separator:ga2de8850780af26e802ee4cc43e9da6e9"><td class="memSeparator" colspan="2"> </td></tr>
1549 <tr class="memitem:ga8bb27e1bab132a8df44190adb996c2a1"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#ga8bb27e1bab132a8df44190adb996c2a1">GIC_GetHighPendingIRQ</a> (void)</td></tr>
1550 <tr class="memdesc:ga8bb27e1bab132a8df44190adb996c2a1"><td class="mdescLeft"> </td><td class="mdescRight">Get the interrupt number of the highest interrupt pending from CPU's HPPIR register. <br /></td></tr>
1551 <tr class="separator:ga8bb27e1bab132a8df44190adb996c2a1"><td class="memSeparator" colspan="2"> </td></tr>
1552 <tr class="memitem:gaba1b2665cdda47fc0bc3d7b90690dc50"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#gaba1b2665cdda47fc0bc3d7b90690dc50">GIC_GetInterfaceId</a> (void)</td></tr>
1553 <tr class="memdesc:gaba1b2665cdda47fc0bc3d7b90690dc50"><td class="mdescLeft"> </td><td class="mdescRight">Provides information about the implementer and revision of the CPU interface. <br /></td></tr>
1554 <tr class="separator:gaba1b2665cdda47fc0bc3d7b90690dc50"><td class="memSeparator" colspan="2"> </td></tr>
1555 <tr class="memitem:ab875d63dc51a75149802945bb00e2695"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE void </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#ab875d63dc51a75149802945bb00e2695">GIC_SetGroup</a> (<a class="el" href="group__irq__ctrl__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn, uint32_t group)</td></tr>
1556 <tr class="memdesc:ab875d63dc51a75149802945bb00e2695"><td class="mdescLeft"> </td><td class="mdescRight">Set the interrupt group from the GIC's IGROUPR register. <br /></td></tr>
1557 <tr class="separator:ab875d63dc51a75149802945bb00e2695"><td class="memSeparator" colspan="2"> </td></tr>
1558 <tr class="memitem:ae161d7a866cb61f92b808ae98fa7c812"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#ae161d7a866cb61f92b808ae98fa7c812">GIC_GetGroup</a> (<a class="el" href="group__irq__ctrl__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn)</td></tr>
1559 <tr class="memdesc:ae161d7a866cb61f92b808ae98fa7c812"><td class="mdescLeft"> </td><td class="mdescRight">Get the interrupt group from the GIC's IGROUPR register. <br /></td></tr>
1560 <tr class="separator:ae161d7a866cb61f92b808ae98fa7c812"><td class="memSeparator" colspan="2"> </td></tr>
1561 <tr class="memitem:ga07acd03d02683bb6e33e7f57f5f371d1"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#ga07acd03d02683bb6e33e7f57f5f371d1">GIC_DistInit</a> (void)</td></tr>
1562 <tr class="memdesc:ga07acd03d02683bb6e33e7f57f5f371d1"><td class="mdescLeft"> </td><td class="mdescRight">Initialize the interrupt distributor. <br /></td></tr>
1563 <tr class="separator:ga07acd03d02683bb6e33e7f57f5f371d1"><td class="memSeparator" colspan="2"> </td></tr>
1564 <tr class="memitem:ga1c93f8af9f428cda8ec066bf4bfbade9"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#ga1c93f8af9f428cda8ec066bf4bfbade9">GIC_CPUInterfaceInit</a> (void)</td></tr>
1565 <tr class="memdesc:ga1c93f8af9f428cda8ec066bf4bfbade9"><td class="mdescLeft"> </td><td class="mdescRight">Initialize the CPU's interrupt interface. <br /></td></tr>
1566 <tr class="separator:ga1c93f8af9f428cda8ec066bf4bfbade9"><td class="memSeparator" colspan="2"> </td></tr>
1567 <tr class="memitem:ga818881f69aae3eef6eb996bee6f6c63e"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#ga818881f69aae3eef6eb996bee6f6c63e">GIC_Enable</a> (void)</td></tr>
1568 <tr class="memdesc:ga818881f69aae3eef6eb996bee6f6c63e"><td class="mdescLeft"> </td><td class="mdescRight">Initialize and enable the GIC. <br /></td></tr>
1569 <tr class="separator:ga818881f69aae3eef6eb996bee6f6c63e"><td class="memSeparator" colspan="2"> </td></tr>
1570 <tr class="memitem:gac09f09327fde6a6adffe0e6298eaa1db"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__PL1__timer__functions.html#gac09f09327fde6a6adffe0e6298eaa1db">PL1_SetCounterFrequency</a> (uint32_t value)</td></tr>
1571 <tr class="memdesc:gac09f09327fde6a6adffe0e6298eaa1db"><td class="mdescLeft"> </td><td class="mdescRight">Configures the frequency the timer shall run at. <br /></td></tr>
1572 <tr class="separator:gac09f09327fde6a6adffe0e6298eaa1db"><td class="memSeparator" colspan="2"> </td></tr>
1573 <tr class="memitem:gae4edcfbdaf901a59a81d1fbf9845d9f7"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__PL1__timer__functions.html#gae4edcfbdaf901a59a81d1fbf9845d9f7">PL1_SetLoadValue</a> (uint32_t value)</td></tr>
1574 <tr class="memdesc:gae4edcfbdaf901a59a81d1fbf9845d9f7"><td class="mdescLeft"> </td><td class="mdescRight">Sets the reset value of the timer. <br /></td></tr>
1575 <tr class="separator:gae4edcfbdaf901a59a81d1fbf9845d9f7"><td class="memSeparator" colspan="2"> </td></tr>
1576 <tr class="memitem:ga8a212e9457005edfb9f14afbf937ebf9"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__PL1__timer__functions.html#ga8a212e9457005edfb9f14afbf937ebf9">PL1_GetCurrentValue</a> (void)</td></tr>
1577 <tr class="memdesc:ga8a212e9457005edfb9f14afbf937ebf9"><td class="mdescLeft"> </td><td class="mdescRight">Get the current counter value. <br /></td></tr>
1578 <tr class="separator:ga8a212e9457005edfb9f14afbf937ebf9"><td class="memSeparator" colspan="2"> </td></tr>
1579 <tr class="memitem:gac66bd336d2353f70aa8ebfc73aa3fc43"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE uint64_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__PL1__timer__functions.html#gac66bd336d2353f70aa8ebfc73aa3fc43">PL1_GetCurrentPhysicalValue</a> (void)</td></tr>
1580 <tr class="memdesc:gac66bd336d2353f70aa8ebfc73aa3fc43"><td class="mdescLeft"> </td><td class="mdescRight">Get the current physical counter value. <br /></td></tr>
1581 <tr class="separator:gac66bd336d2353f70aa8ebfc73aa3fc43"><td class="memSeparator" colspan="2"> </td></tr>
1582 <tr class="memitem:gab34067824971064a829e17b791070643"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__PL1__timer__functions.html#gab34067824971064a829e17b791070643">PL1_SetPhysicalCompareValue</a> (uint64_t value)</td></tr>
1583 <tr class="memdesc:gab34067824971064a829e17b791070643"><td class="mdescLeft"> </td><td class="mdescRight">Set the physical compare value. <br /></td></tr>
1584 <tr class="separator:gab34067824971064a829e17b791070643"><td class="memSeparator" colspan="2"> </td></tr>
1585 <tr class="memitem:ga341ae7d1ae29f4dc5dae6310fa453164"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE uint64_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__PL1__timer__functions.html#ga341ae7d1ae29f4dc5dae6310fa453164">PL1_GetPhysicalCompareValue</a> (void)</td></tr>
1586 <tr class="memdesc:ga341ae7d1ae29f4dc5dae6310fa453164"><td class="mdescLeft"> </td><td class="mdescRight">Get the physical compare value. <br /></td></tr>
1587 <tr class="separator:ga341ae7d1ae29f4dc5dae6310fa453164"><td class="memSeparator" colspan="2"> </td></tr>
1588 <tr class="memitem:ga2e2ea7eac12a90c6243000172bf774e1"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__PL1__timer__functions.html#ga2e2ea7eac12a90c6243000172bf774e1">PL1_SetControl</a> (uint32_t value)</td></tr>
1589 <tr class="memdesc:ga2e2ea7eac12a90c6243000172bf774e1"><td class="mdescLeft"> </td><td class="mdescRight">Configure the timer by setting the control value. <br /></td></tr>
1590 <tr class="separator:ga2e2ea7eac12a90c6243000172bf774e1"><td class="memSeparator" colspan="2"> </td></tr>
1591 <tr class="memitem:gaf7fda3fe3452565fbe46cb0ea53a9f8a"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__PL1__timer__functions.html#gaf7fda3fe3452565fbe46cb0ea53a9f8a">PL1_GetControl</a> (void)</td></tr>
1592 <tr class="memdesc:gaf7fda3fe3452565fbe46cb0ea53a9f8a"><td class="mdescLeft"> </td><td class="mdescRight">Get the control value. <br /></td></tr>
1593 <tr class="separator:gaf7fda3fe3452565fbe46cb0ea53a9f8a"><td class="memSeparator" colspan="2"> </td></tr>
1594 <tr class="memitem:aead4ebf7c19a2edb6643a88a948015b9"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE void </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#aead4ebf7c19a2edb6643a88a948015b9">VL1_SetCurrentTimerValue</a> (uint32_t value)</td></tr>
1595 <tr class="memdesc:aead4ebf7c19a2edb6643a88a948015b9"><td class="mdescLeft"> </td><td class="mdescRight">Virtual Timer Control register. <br /></td></tr>
1596 <tr class="separator:aead4ebf7c19a2edb6643a88a948015b9"><td class="memSeparator" colspan="2"> </td></tr>
1597 <tr class="memitem:a6eb9e1aae071d51af457899a6ff2c7b6"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a6eb9e1aae071d51af457899a6ff2c7b6">VL1_GetCurrentTimerValue</a> (void)</td></tr>
1598 <tr class="memdesc:a6eb9e1aae071d51af457899a6ff2c7b6"><td class="mdescLeft"> </td><td class="mdescRight">Get the current virtual timer value. <br /></td></tr>
1599 <tr class="separator:a6eb9e1aae071d51af457899a6ff2c7b6"><td class="memSeparator" colspan="2"> </td></tr>
1600 <tr class="memitem:af3ebcde97e7b5d2096516b06f4ab70be"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE uint64_t </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#af3ebcde97e7b5d2096516b06f4ab70be">VL1_GetCurrentCountValue</a> (void)</td></tr>
1601 <tr class="memdesc:af3ebcde97e7b5d2096516b06f4ab70be"><td class="mdescLeft"> </td><td class="mdescRight">Get the current virtual count value. <br /></td></tr>
1602 <tr class="separator:af3ebcde97e7b5d2096516b06f4ab70be"><td class="memSeparator" colspan="2"> </td></tr>
1603 <tr class="memitem:a85248310b22171e66951267124f2ff85"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE void </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a85248310b22171e66951267124f2ff85">VL1_SetTimerCompareValue</a> (uint64_t value)</td></tr>
1604 <tr class="memdesc:a85248310b22171e66951267124f2ff85"><td class="mdescLeft"> </td><td class="mdescRight">Set the virtual timer compare value. <br /></td></tr>
1605 <tr class="separator:a85248310b22171e66951267124f2ff85"><td class="memSeparator" colspan="2"> </td></tr>
1606 <tr class="memitem:aa317cc419b7ed37b2e6e86d23152caeb"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE uint64_t </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#aa317cc419b7ed37b2e6e86d23152caeb">VL1_GetTimerCompareValue</a> (void)</td></tr>
1607 <tr class="memdesc:aa317cc419b7ed37b2e6e86d23152caeb"><td class="mdescLeft"> </td><td class="mdescRight">Get the virtual timer compare value. <br /></td></tr>
1608 <tr class="separator:aa317cc419b7ed37b2e6e86d23152caeb"><td class="memSeparator" colspan="2"> </td></tr>
1609 <tr class="memitem:ae1fa0c37d9bea7d4a2d039be754d1676"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE void </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#ae1fa0c37d9bea7d4a2d039be754d1676">VL1_SetControl</a> (uint32_t value)</td></tr>
1610 <tr class="memdesc:ae1fa0c37d9bea7d4a2d039be754d1676"><td class="mdescLeft"> </td><td class="mdescRight">Configure the virtual timer by setting the control value. <br /></td></tr>
1611 <tr class="separator:ae1fa0c37d9bea7d4a2d039be754d1676"><td class="memSeparator" colspan="2"> </td></tr>
1612 <tr class="memitem:af7e103fe79be50a7f314cdcac33612ef"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#af7e103fe79be50a7f314cdcac33612ef">VL1_GetControl</a> (void)</td></tr>
1613 <tr class="memdesc:af7e103fe79be50a7f314cdcac33612ef"><td class="mdescLeft"> </td><td class="mdescRight">Get the virtual timer control value. <br /></td></tr>
1614 <tr class="separator:af7e103fe79be50a7f314cdcac33612ef"><td class="memSeparator" colspan="2"> </td></tr>
1615 <tr class="memitem:ga30516fed24977be8eecf3efd8b6a2fea"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__PTM__timer__functions.html#ga30516fed24977be8eecf3efd8b6a2fea">PTIM_SetLoadValue</a> (uint32_t value)</td></tr>
1616 <tr class="memdesc:ga30516fed24977be8eecf3efd8b6a2fea"><td class="mdescLeft"> </td><td class="mdescRight">Set the load value to timers LOAD register. <br /></td></tr>
1617 <tr class="separator:ga30516fed24977be8eecf3efd8b6a2fea"><td class="memSeparator" colspan="2"> </td></tr>
1618 <tr class="memitem:gacca3bf92e93c69e538ff4618317f7bfa"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__PTM__timer__functions.html#gacca3bf92e93c69e538ff4618317f7bfa">PTIM_GetLoadValue</a> (void)</td></tr>
1619 <tr class="memdesc:gacca3bf92e93c69e538ff4618317f7bfa"><td class="mdescLeft"> </td><td class="mdescRight">Get the load value from timers LOAD register. <br /></td></tr>
1620 <tr class="separator:gacca3bf92e93c69e538ff4618317f7bfa"><td class="memSeparator" colspan="2"> </td></tr>
1621 <tr class="memitem:a323bf405e32846a7e57344935e51de66"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE void </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a323bf405e32846a7e57344935e51de66">PTIM_SetCurrentValue</a> (uint32_t value)</td></tr>
1622 <tr class="memdesc:a323bf405e32846a7e57344935e51de66"><td class="mdescLeft"> </td><td class="mdescRight">Set current counter value from its COUNTER register. <br /></td></tr>
1623 <tr class="separator:a323bf405e32846a7e57344935e51de66"><td class="memSeparator" colspan="2"> </td></tr>
1624 <tr class="memitem:gaaccd88ab7931c379817f71d7c0183586"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__PTM__timer__functions.html#gaaccd88ab7931c379817f71d7c0183586">PTIM_GetCurrentValue</a> (void)</td></tr>
1625 <tr class="memdesc:gaaccd88ab7931c379817f71d7c0183586"><td class="mdescLeft"> </td><td class="mdescRight">Get current counter value from timers COUNTER register. <br /></td></tr>
1626 <tr class="separator:gaaccd88ab7931c379817f71d7c0183586"><td class="memSeparator" colspan="2"> </td></tr>
1627 <tr class="memitem:gaabc1dba029389fe0e2a6297952df7972"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__PTM__timer__functions.html#gaabc1dba029389fe0e2a6297952df7972">PTIM_SetControl</a> (uint32_t value)</td></tr>
1628 <tr class="memdesc:gaabc1dba029389fe0e2a6297952df7972"><td class="mdescLeft"> </td><td class="mdescRight">Configure the timer using its CONTROL register. <br /></td></tr>
1629 <tr class="separator:gaabc1dba029389fe0e2a6297952df7972"><td class="memSeparator" colspan="2"> </td></tr>
1630 <tr class="memitem:ga34f0ceea142a4be1479cb552bf8bc4d1"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__PTM__timer__functions.html#ga34f0ceea142a4be1479cb552bf8bc4d1">PTIM_GetControl</a> (void)</td></tr>
1631 <tr class="separator:ga34f0ceea142a4be1479cb552bf8bc4d1"><td class="memSeparator" colspan="2"> </td></tr>
1632 <tr class="memitem:a2c3f9f942e8a08630562f35802dbe942"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="core__ca_8h.html#a2c3f9f942e8a08630562f35802dbe942">PTIM_GetEventFlag</a> (void)</td></tr>
1633 <tr class="separator:a2c3f9f942e8a08630562f35802dbe942"><td class="memSeparator" colspan="2"> </td></tr>
1634 <tr class="memitem:ga59dca62df390bc4bce18559fc7d28578"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__PTM__timer__functions.html#ga59dca62df390bc4bce18559fc7d28578">PTIM_ClearEventFlag</a> (void)</td></tr>
1635 <tr class="separator:ga59dca62df390bc4bce18559fc7d28578"><td class="memSeparator" colspan="2"> </td></tr>
1636 <tr class="memitem:ga9132cbfe3b2367de3db27daf4cc82ad7"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE int </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__functions.html#ga9132cbfe3b2367de3db27daf4cc82ad7">MMU_XNSection</a> (uint32_t *descriptor_l1, <a class="el" href="group__MMU__defs__gr.html#ga2fe1157deda82e66b9a1b19772309b63">mmu_execute_Type</a> xn)</td></tr>
1637 <tr class="memdesc:ga9132cbfe3b2367de3db27daf4cc82ad7"><td class="mdescLeft"> </td><td class="mdescRight">Set section execution-never attribute. <br /></td></tr>
1638 <tr class="separator:ga9132cbfe3b2367de3db27daf4cc82ad7"><td class="memSeparator" colspan="2"> </td></tr>
1639 <tr class="memitem:gabd88f4c41b74365c38209692785287d0"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE int </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__functions.html#gabd88f4c41b74365c38209692785287d0">MMU_DomainSection</a> (uint32_t *descriptor_l1, uint8_t domain)</td></tr>
1640 <tr class="memdesc:gabd88f4c41b74365c38209692785287d0"><td class="mdescLeft"> </td><td class="mdescRight">Set section domain. <br /></td></tr>
1641 <tr class="separator:gabd88f4c41b74365c38209692785287d0"><td class="memSeparator" colspan="2"> </td></tr>
1642 <tr class="memitem:ga3577aec23189228c9f95abba50c3716d"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE int </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__functions.html#ga3577aec23189228c9f95abba50c3716d">MMU_PSection</a> (uint32_t *descriptor_l1, <a class="el" href="group__MMU__defs__gr.html#ga06d94c0eaa22d713636acaff81485409">mmu_ecc_check_Type</a> p_bit)</td></tr>
1643 <tr class="memdesc:ga3577aec23189228c9f95abba50c3716d"><td class="mdescLeft"> </td><td class="mdescRight">Set section parity check. <br /></td></tr>
1644 <tr class="separator:ga3577aec23189228c9f95abba50c3716d"><td class="memSeparator" colspan="2"> </td></tr>
1645 <tr class="memitem:ga946866c84a72690c385ee07545bf8145"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE int </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__functions.html#ga946866c84a72690c385ee07545bf8145">MMU_APSection</a> (uint32_t *descriptor_l1, <a class="el" href="group__MMU__defs__gr.html#ga2ee598252f996e4f96640b096291d280">mmu_access_Type</a> user, <a class="el" href="group__MMU__defs__gr.html#ga2ee598252f996e4f96640b096291d280">mmu_access_Type</a> priv, uint32_t afe)</td></tr>
1646 <tr class="memdesc:ga946866c84a72690c385ee07545bf8145"><td class="mdescLeft"> </td><td class="mdescRight">Set section access privileges. <br /></td></tr>
1647 <tr class="separator:ga946866c84a72690c385ee07545bf8145"><td class="memSeparator" colspan="2"> </td></tr>
1648 <tr class="memitem:ga29ea426394746cdd6a4b4c14164ec6b9"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE int </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__functions.html#ga29ea426394746cdd6a4b4c14164ec6b9">MMU_SharedSection</a> (uint32_t *descriptor_l1, <a class="el" href="group__MMU__defs__gr.html#gab884a11fa8d094573ab77fb1c0f8d8a7">mmu_shared_Type</a> s_bit)</td></tr>
1649 <tr class="memdesc:ga29ea426394746cdd6a4b4c14164ec6b9"><td class="mdescLeft"> </td><td class="mdescRight">Set section shareability. <br /></td></tr>
1650 <tr class="separator:ga29ea426394746cdd6a4b4c14164ec6b9"><td class="memSeparator" colspan="2"> </td></tr>
1651 <tr class="memitem:ga3ca22117a7f2d3c4d1cd1bf832cc4d2f"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE int </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__functions.html#ga3ca22117a7f2d3c4d1cd1bf832cc4d2f">MMU_GlobalSection</a> (uint32_t *descriptor_l1, <a class="el" href="group__MMU__defs__gr.html#ga04160605fbe20914c8ef020430684a30">mmu_global_Type</a> g_bit)</td></tr>
1652 <tr class="memdesc:ga3ca22117a7f2d3c4d1cd1bf832cc4d2f"><td class="mdescLeft"> </td><td class="mdescRight">Set section Global attribute. <br /></td></tr>
1653 <tr class="separator:ga3ca22117a7f2d3c4d1cd1bf832cc4d2f"><td class="memSeparator" colspan="2"> </td></tr>
1654 <tr class="memitem:ga84a5a15ee353d70a9b904e3814bd94d8"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE int </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__functions.html#ga84a5a15ee353d70a9b904e3814bd94d8">MMU_SecureSection</a> (uint32_t *descriptor_l1, <a class="el" href="group__MMU__defs__gr.html#gac3d277641df9fb3bb3b555e2e79dd639">mmu_secure_Type</a> s_bit)</td></tr>
1655 <tr class="memdesc:ga84a5a15ee353d70a9b904e3814bd94d8"><td class="mdescLeft"> </td><td class="mdescRight">Set section Security attribute. <br /></td></tr>
1656 <tr class="separator:ga84a5a15ee353d70a9b904e3814bd94d8"><td class="memSeparator" colspan="2"> </td></tr>
1657 <tr class="memitem:gab0e0fed40d998757147beb8fcf05a890"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE int </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__functions.html#gab0e0fed40d998757147beb8fcf05a890">MMU_XNPage</a> (uint32_t *descriptor_l2, <a class="el" href="group__MMU__defs__gr.html#ga2fe1157deda82e66b9a1b19772309b63">mmu_execute_Type</a> xn, <a class="el" href="group__MMU__defs__gr.html#gab184b824a6d7cb728bd46c6abcd0c21a">mmu_region_size_Type</a> page)</td></tr>
1658 <tr class="memdesc:gab0e0fed40d998757147beb8fcf05a890"><td class="mdescLeft"> </td><td class="mdescRight">Set 4k/64k page execution-never attribute. <br /></td></tr>
1659 <tr class="separator:gab0e0fed40d998757147beb8fcf05a890"><td class="memSeparator" colspan="2"> </td></tr>
1660 <tr class="memitem:ga45f5389cb1351bb2806a38ac8c32d416"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE int </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__functions.html#ga45f5389cb1351bb2806a38ac8c32d416">MMU_DomainPage</a> (uint32_t *descriptor_l1, uint8_t domain)</td></tr>
1661 <tr class="memdesc:ga45f5389cb1351bb2806a38ac8c32d416"><td class="mdescLeft"> </td><td class="mdescRight">Set 4k/64k page domain. <br /></td></tr>
1662 <tr class="separator:ga45f5389cb1351bb2806a38ac8c32d416"><td class="memSeparator" colspan="2"> </td></tr>
1663 <tr class="memitem:gab15289c416609cd56dde816b39a4cea4"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE int </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__functions.html#gab15289c416609cd56dde816b39a4cea4">MMU_PPage</a> (uint32_t *descriptor_l1, <a class="el" href="group__MMU__defs__gr.html#ga06d94c0eaa22d713636acaff81485409">mmu_ecc_check_Type</a> p_bit)</td></tr>
1664 <tr class="memdesc:gab15289c416609cd56dde816b39a4cea4"><td class="mdescLeft"> </td><td class="mdescRight">Set 4k/64k page parity check. <br /></td></tr>
1665 <tr class="separator:gab15289c416609cd56dde816b39a4cea4"><td class="memSeparator" colspan="2"> </td></tr>
1666 <tr class="memitem:gac7c88d4d613350059b4d77814ea2c7a0"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE int </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__functions.html#gac7c88d4d613350059b4d77814ea2c7a0">MMU_APPage</a> (uint32_t *descriptor_l2, <a class="el" href="group__MMU__defs__gr.html#ga2ee598252f996e4f96640b096291d280">mmu_access_Type</a> user, <a class="el" href="group__MMU__defs__gr.html#ga2ee598252f996e4f96640b096291d280">mmu_access_Type</a> priv, uint32_t afe)</td></tr>
1667 <tr class="memdesc:gac7c88d4d613350059b4d77814ea2c7a0"><td class="mdescLeft"> </td><td class="mdescRight">Set 4k/64k page access privileges. <br /></td></tr>
1668 <tr class="separator:gac7c88d4d613350059b4d77814ea2c7a0"><td class="memSeparator" colspan="2"> </td></tr>
1669 <tr class="memitem:gaaa19560532778e4fdc667e56fd2dd378"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE int </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__functions.html#gaaa19560532778e4fdc667e56fd2dd378">MMU_SharedPage</a> (uint32_t *descriptor_l2, <a class="el" href="group__MMU__defs__gr.html#gab884a11fa8d094573ab77fb1c0f8d8a7">mmu_shared_Type</a> s_bit)</td></tr>
1670 <tr class="memdesc:gaaa19560532778e4fdc667e56fd2dd378"><td class="mdescLeft"> </td><td class="mdescRight">Set 4k/64k page shareability. <br /></td></tr>
1671 <tr class="separator:gaaa19560532778e4fdc667e56fd2dd378"><td class="memSeparator" colspan="2"> </td></tr>
1672 <tr class="memitem:ga14dfeaf8983de57521aaa66c19dd43c9"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE int </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__functions.html#ga14dfeaf8983de57521aaa66c19dd43c9">MMU_GlobalPage</a> (uint32_t *descriptor_l2, <a class="el" href="group__MMU__defs__gr.html#ga04160605fbe20914c8ef020430684a30">mmu_global_Type</a> g_bit)</td></tr>
1673 <tr class="memdesc:ga14dfeaf8983de57521aaa66c19dd43c9"><td class="mdescLeft"> </td><td class="mdescRight">Set 4k/64k page Global attribute. <br /></td></tr>
1674 <tr class="separator:ga14dfeaf8983de57521aaa66c19dd43c9"><td class="memSeparator" colspan="2"> </td></tr>
1675 <tr class="memitem:ga2c1887ed6aaff0a51e3effc3db595c94"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE int </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__functions.html#ga2c1887ed6aaff0a51e3effc3db595c94">MMU_SecurePage</a> (uint32_t *descriptor_l1, <a class="el" href="group__MMU__defs__gr.html#gac3d277641df9fb3bb3b555e2e79dd639">mmu_secure_Type</a> s_bit)</td></tr>
1676 <tr class="memdesc:ga2c1887ed6aaff0a51e3effc3db595c94"><td class="mdescLeft"> </td><td class="mdescRight">Set 4k/64k page Security attribute. <br /></td></tr>
1677 <tr class="separator:ga2c1887ed6aaff0a51e3effc3db595c94"><td class="memSeparator" colspan="2"> </td></tr>
1678 <tr class="memitem:ga353d3d794bcd1b35b3b5aeb73d6feb08"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE int </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__functions.html#ga353d3d794bcd1b35b3b5aeb73d6feb08">MMU_MemorySection</a> (uint32_t *descriptor_l1, <a class="el" href="group__MMU__defs__gr.html#ga83ac8de9263f89879079da521e86d5f2">mmu_memory_Type</a> mem, <a class="el" href="group__MMU__defs__gr.html#ga11c86b7b193efb2c59b6a2179a02f584">mmu_cacheability_Type</a> outer, <a class="el" href="group__MMU__defs__gr.html#ga11c86b7b193efb2c59b6a2179a02f584">mmu_cacheability_Type</a> inner)</td></tr>
1679 <tr class="memdesc:ga353d3d794bcd1b35b3b5aeb73d6feb08"><td class="mdescLeft"> </td><td class="mdescRight">Set Section memory attributes. <br /></td></tr>
1680 <tr class="separator:ga353d3d794bcd1b35b3b5aeb73d6feb08"><td class="memSeparator" colspan="2"> </td></tr>
1681 <tr class="memitem:ga9a2946f7c93bcb05cdd20be691a54b8c"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE int </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__functions.html#ga9a2946f7c93bcb05cdd20be691a54b8c">MMU_MemoryPage</a> (uint32_t *descriptor_l2, <a class="el" href="group__MMU__defs__gr.html#ga83ac8de9263f89879079da521e86d5f2">mmu_memory_Type</a> mem, <a class="el" href="group__MMU__defs__gr.html#ga11c86b7b193efb2c59b6a2179a02f584">mmu_cacheability_Type</a> outer, <a class="el" href="group__MMU__defs__gr.html#ga11c86b7b193efb2c59b6a2179a02f584">mmu_cacheability_Type</a> inner, <a class="el" href="group__MMU__defs__gr.html#gab184b824a6d7cb728bd46c6abcd0c21a">mmu_region_size_Type</a> page)</td></tr>
1682 <tr class="memdesc:ga9a2946f7c93bcb05cdd20be691a54b8c"><td class="mdescLeft"> </td><td class="mdescRight">Set 4k/64k page memory attributes. <br /></td></tr>
1683 <tr class="separator:ga9a2946f7c93bcb05cdd20be691a54b8c"><td class="memSeparator" colspan="2"> </td></tr>
1684 <tr class="memitem:ga4f21eee79309cf8cde694d0d7e1205bd"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE int </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__functions.html#ga4f21eee79309cf8cde694d0d7e1205bd">MMU_GetSectionDescriptor</a> (uint32_t *descriptor, <a class="el" href="structmmu__region__attributes__Type.html">mmu_region_attributes_Type</a> reg)</td></tr>
1685 <tr class="memdesc:ga4f21eee79309cf8cde694d0d7e1205bd"><td class="mdescLeft"> </td><td class="mdescRight">Create a L1 section descriptor. <br /></td></tr>
1686 <tr class="separator:ga4f21eee79309cf8cde694d0d7e1205bd"><td class="memSeparator" colspan="2"> </td></tr>
1687 <tr class="memitem:gaa2fcfb63c7019665b8a352d54f55d740"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE int </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__functions.html#gaa2fcfb63c7019665b8a352d54f55d740">MMU_GetPageDescriptor</a> (uint32_t *descriptor, uint32_t *descriptor2, <a class="el" href="structmmu__region__attributes__Type.html">mmu_region_attributes_Type</a> reg)</td></tr>
1688 <tr class="memdesc:gaa2fcfb63c7019665b8a352d54f55d740"><td class="mdescLeft"> </td><td class="mdescRight">Create a L1 and L2 4k/64k page descriptor. <br /></td></tr>
1689 <tr class="separator:gaa2fcfb63c7019665b8a352d54f55d740"><td class="memSeparator" colspan="2"> </td></tr>
1690 <tr class="memitem:gaaff28ea191391cbbd389d74327961753"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__functions.html#gaaff28ea191391cbbd389d74327961753">MMU_TTSection</a> (uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1)</td></tr>
1691 <tr class="memdesc:gaaff28ea191391cbbd389d74327961753"><td class="mdescLeft"> </td><td class="mdescRight">Create a 1MB Section. <br /></td></tr>
1692 <tr class="separator:gaaff28ea191391cbbd389d74327961753"><td class="memSeparator" colspan="2"> </td></tr>
1693 <tr class="memitem:ga823cca9649a28bab8a90f8bd9bb92d83"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__functions.html#ga823cca9649a28bab8a90f8bd9bb92d83">MMU_TTPage4k</a> (uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2)</td></tr>
1694 <tr class="memdesc:ga823cca9649a28bab8a90f8bd9bb92d83"><td class="mdescLeft"> </td><td class="mdescRight">Create a 4k page entry. <br /></td></tr>
1695 <tr class="separator:ga823cca9649a28bab8a90f8bd9bb92d83"><td class="memSeparator" colspan="2"> </td></tr>
1696 <tr class="memitem:ga48c509501f94a3f7316e79f8ccd34184"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__functions.html#ga48c509501f94a3f7316e79f8ccd34184">MMU_TTPage64k</a> (uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2)</td></tr>
1697 <tr class="memdesc:ga48c509501f94a3f7316e79f8ccd34184"><td class="mdescLeft"> </td><td class="mdescRight">Create a 64k page entry. <br /></td></tr>
1698 <tr class="separator:ga48c509501f94a3f7316e79f8ccd34184"><td class="memSeparator" colspan="2"> </td></tr>
1699 <tr class="memitem:ga63334cbd77d310d078eb226c7542b96b"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__functions.html#ga63334cbd77d310d078eb226c7542b96b">MMU_Enable</a> (void)</td></tr>
1700 <tr class="memdesc:ga63334cbd77d310d078eb226c7542b96b"><td class="mdescLeft"> </td><td class="mdescRight">Enable MMU. <br /></td></tr>
1701 <tr class="separator:ga63334cbd77d310d078eb226c7542b96b"><td class="memSeparator" colspan="2"> </td></tr>
1702 <tr class="memitem:ga2a2badd06531e04f559b97fdb2aea154"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__functions.html#ga2a2badd06531e04f559b97fdb2aea154">MMU_Disable</a> (void)</td></tr>
1703 <tr class="memdesc:ga2a2badd06531e04f559b97fdb2aea154"><td class="mdescLeft"> </td><td class="mdescRight">Disable MMU. <br /></td></tr>
1704 <tr class="separator:ga2a2badd06531e04f559b97fdb2aea154"><td class="memSeparator" colspan="2"> </td></tr>
1705 <tr class="memitem:ga9de65bea1cabf73dc4302e0e727cc8c3"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__MMU__functions.html#ga9de65bea1cabf73dc4302e0e727cc8c3">MMU_InvalidateTLB</a> (void)</td></tr>
1706 <tr class="memdesc:ga9de65bea1cabf73dc4302e0e727cc8c3"><td class="mdescLeft"> </td><td class="mdescRight">Invalidate entire unified TLB. <br /></td></tr>
1707 <tr class="separator:ga9de65bea1cabf73dc4302e0e727cc8c3"><td class="memSeparator" colspan="2"> </td></tr>
1709 <h2 class="groupheader">Macro Definition Documentation</h2>
1710 <a id="add5658d95f6b79934202e6fbf1795b12" name="add5658d95f6b79934202e6fbf1795b12"></a>
1711 <h2 class="memtitle"><span class="permalink"><a href="#add5658d95f6b79934202e6fbf1795b12">◆ </a></span>__CORE_CA_H_DEPENDANT</h2>
1713 <div class="memitem">
1714 <div class="memproto">
1715 <table class="memname">
1717 <td class="memname">#define __CORE_CA_H_DEPENDANT</td>
1720 </div><div class="memdoc">
1724 <a id="ac1ba8a48ca926bddc88be9bfd7d42641" name="ac1ba8a48ca926bddc88be9bfd7d42641"></a>
1725 <h2 class="memtitle"><span class="permalink"><a href="#ac1ba8a48ca926bddc88be9bfd7d42641">◆ </a></span>__FPU_PRESENT</h2>
1727 <div class="memitem">
1728 <div class="memproto">
1729 <table class="memname">
1731 <td class="memname">#define __FPU_PRESENT   0U</td>
1734 </div><div class="memdoc">
1738 <a id="aa167d0f532a7c2b2e3a6395db2fa0776" name="aa167d0f532a7c2b2e3a6395db2fa0776"></a>
1739 <h2 class="memtitle"><span class="permalink"><a href="#aa167d0f532a7c2b2e3a6395db2fa0776">◆ </a></span>__FPU_USED</h2>
1741 <div class="memitem">
1742 <div class="memproto">
1743 <table class="memname">
1745 <td class="memname">#define __FPU_USED   0U</td>
1748 </div><div class="memdoc">
1752 <a id="a6690a7e24ea0ec4b36a8fb077d01a820" name="a6690a7e24ea0ec4b36a8fb077d01a820"></a>
1753 <h2 class="memtitle"><span class="permalink"><a href="#a6690a7e24ea0ec4b36a8fb077d01a820">◆ </a></span>__GIC_PRESENT</h2>
1755 <div class="memitem">
1756 <div class="memproto">
1757 <table class="memname">
1759 <td class="memname">#define __GIC_PRESENT   1U</td>
1762 </div><div class="memdoc">
1766 <a id="af63697ed9952cc71e1225efe205f6cd3" name="af63697ed9952cc71e1225efe205f6cd3"></a>
1767 <h2 class="memtitle"><span class="permalink"><a href="#af63697ed9952cc71e1225efe205f6cd3">◆ </a></span>__I</h2>
1769 <div class="memitem">
1770 <div class="memproto">
1771 <table class="memname">
1773 <td class="memname">#define __I   volatile</td>
1776 </div><div class="memdoc">
1778 <p>Defines 'read only' permissions. </p>
1782 <a id="a4cc1649793116d7c2d8afce7a4ffce43" name="a4cc1649793116d7c2d8afce7a4ffce43"></a>
1783 <h2 class="memtitle"><span class="permalink"><a href="#a4cc1649793116d7c2d8afce7a4ffce43">◆ </a></span>__IM</h2>
1785 <div class="memitem">
1786 <div class="memproto">
1787 <table class="memname">
1789 <td class="memname">#define __IM   volatile const</td>
1792 </div><div class="memdoc">
1794 <p>Defines 'read only' structure member permissions. </p>
1798 <a id="aec43007d9998a0a0e01faede4133d6be" name="aec43007d9998a0a0e01faede4133d6be"></a>
1799 <h2 class="memtitle"><span class="permalink"><a href="#aec43007d9998a0a0e01faede4133d6be">◆ </a></span>__IO</h2>
1801 <div class="memitem">
1802 <div class="memproto">
1803 <table class="memname">
1805 <td class="memname">#define __IO   volatile</td>
1808 </div><div class="memdoc">
1810 <p>Defines 'read / write' permissions. </p>
1814 <a id="ab6caba5853a60a17e8e04499b52bf691" name="ab6caba5853a60a17e8e04499b52bf691"></a>
1815 <h2 class="memtitle"><span class="permalink"><a href="#ab6caba5853a60a17e8e04499b52bf691">◆ </a></span>__IOM</h2>
1817 <div class="memitem">
1818 <div class="memproto">
1819 <table class="memname">
1821 <td class="memname">#define __IOM   volatile</td>
1824 </div><div class="memdoc">
1826 <p>Defines 'read / write' structure member permissions. </p>
1830 <a id="a7e25d9380f9ef903923964322e71f2f6" name="a7e25d9380f9ef903923964322e71f2f6"></a>
1831 <h2 class="memtitle"><span class="permalink"><a href="#a7e25d9380f9ef903923964322e71f2f6">◆ </a></span>__O</h2>
1833 <div class="memitem">
1834 <div class="memproto">
1835 <table class="memname">
1837 <td class="memname">#define __O   volatile</td>
1840 </div><div class="memdoc">
1842 <p>Defines 'write only' permissions. </p>
1846 <a id="a0ea2009ed8fd9ef35b48708280fdb758" name="a0ea2009ed8fd9ef35b48708280fdb758"></a>
1847 <h2 class="memtitle"><span class="permalink"><a href="#a0ea2009ed8fd9ef35b48708280fdb758">◆ </a></span>__OM</h2>
1849 <div class="memitem">
1850 <div class="memproto">
1851 <table class="memname">
1853 <td class="memname">#define __OM   volatile</td>
1856 </div><div class="memdoc">
1858 <p>Defines 'write only' structure member permissions. </p>
1862 <a id="a0e57ca9f1bc10c2de05d383d2c76267a" name="a0e57ca9f1bc10c2de05d383d2c76267a"></a>
1863 <h2 class="memtitle"><span class="permalink"><a href="#a0e57ca9f1bc10c2de05d383d2c76267a">◆ </a></span>__TIM_PRESENT</h2>
1865 <div class="memitem">
1866 <div class="memproto">
1867 <table class="memname">
1869 <td class="memname">#define __TIM_PRESENT   1U</td>
1872 </div><div class="memdoc">
1876 <a id="a139b6e261c981f014f386927ca4a8444" name="a139b6e261c981f014f386927ca4a8444"></a>
1877 <h2 class="memtitle"><span class="permalink"><a href="#a139b6e261c981f014f386927ca4a8444">◆ </a></span>_FLD2VAL</h2>
1879 <div class="memitem">
1880 <div class="memproto">
1881 <table class="memname">
1883 <td class="memname">#define _FLD2VAL</td>
1885 <td class="paramtype"> </td>
1886 <td class="paramname">field, </td>
1889 <td class="paramkey"></td>
1891 <td class="paramtype"> </td>
1892 <td class="paramname">value </td>
1897 <td></td><td>   (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)</td>
1900 </div><div class="memdoc">
1902 <p>Mask and shift a register value to extract a bit filed value. </p>
1903 <dl class="params"><dt>Parameters</dt><dd>
1904 <table class="params">
1905 <tr><td class="paramdir">[in]</td><td class="paramname">field</td><td>Name of the register bit field. </td></tr>
1906 <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value of register. This parameter is interpreted as an uint32_t type. </td></tr>
1910 <dl class="section return"><dt>Returns</dt><dd>Masked and shifted bit field value. </dd></dl>
1914 <a id="a286e3b913dbd236c7f48ea70c8821f4e" name="a286e3b913dbd236c7f48ea70c8821f4e"></a>
1915 <h2 class="memtitle"><span class="permalink"><a href="#a286e3b913dbd236c7f48ea70c8821f4e">◆ </a></span>_VAL2FLD</h2>
1917 <div class="memitem">
1918 <div class="memproto">
1919 <table class="memname">
1921 <td class="memname">#define _VAL2FLD</td>
1923 <td class="paramtype"> </td>
1924 <td class="paramname">field, </td>
1927 <td class="paramkey"></td>
1929 <td class="paramtype"> </td>
1930 <td class="paramname">value </td>
1935 <td></td><td>   (((uint32_t)(value) << field ## _Pos) & field ## _Msk)</td>
1938 </div><div class="memdoc">
1940 <p>Mask and shift a bit field value for use in a register bit range. </p>
1941 <dl class="params"><dt>Parameters</dt><dd>
1942 <table class="params">
1943 <tr><td class="paramdir">[in]</td><td class="paramname">field</td><td>Name of the register bit field. </td></tr>
1944 <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value of the bit field. This parameter is interpreted as an uint32_t type. </td></tr>
1948 <dl class="section return"><dt>Returns</dt><dd>Masked and shifted value. </dd></dl>
1952 <a id="aba92665a24bc2ba8c49b9a0881c9df8a" name="aba92665a24bc2ba8c49b9a0881c9df8a"></a>
1953 <h2 class="memtitle"><span class="permalink"><a href="#aba92665a24bc2ba8c49b9a0881c9df8a">◆ </a></span>DESCRIPTOR_FAULT</h2>
1955 <div class="memitem">
1956 <div class="memproto">
1957 <table class="memname">
1959 <td class="memname">#define DESCRIPTOR_FAULT   (0x00000000)</td>
1962 </div><div class="memdoc">
1966 <a id="aea0bba954f8c3b032cf9a6540277ddef" name="aea0bba954f8c3b032cf9a6540277ddef"></a>
1967 <h2 class="memtitle"><span class="permalink"><a href="#aea0bba954f8c3b032cf9a6540277ddef">◆ </a></span>GIC_GetSecurity</h2>
1969 <div class="memitem">
1970 <div class="memproto">
1971 <table class="memname">
1973 <td class="memname">#define GIC_GetSecurity   <a class="el" href="core__ca_8h.html#ae161d7a866cb61f92b808ae98fa7c812">GIC_GetGroup</a></td>
1976 </div><div class="memdoc">
1980 <a id="a647b0a71258678d75aed0aadd5801612" name="a647b0a71258678d75aed0aadd5801612"></a>
1981 <h2 class="memtitle"><span class="permalink"><a href="#a647b0a71258678d75aed0aadd5801612">◆ </a></span>GIC_SetSecurity</h2>
1983 <div class="memitem">
1984 <div class="memproto">
1985 <table class="memname">
1987 <td class="memname">#define GIC_SetSecurity   <a class="el" href="core__ca_8h.html#ab875d63dc51a75149802945bb00e2695">GIC_SetGroup</a></td>
1990 </div><div class="memdoc">
1994 <a id="aeb357573357d37d881975de18f0e0b95" name="aeb357573357d37d881975de18f0e0b95"></a>
1995 <h2 class="memtitle"><span class="permalink"><a href="#aeb357573357d37d881975de18f0e0b95">◆ </a></span>GICDistributor_CLRSPI_NSR_INTID</h2>
1997 <div class="memitem">
1998 <div class="memproto">
1999 <table class="memname">
2001 <td class="memname">#define GICDistributor_CLRSPI_NSR_INTID</td>
2003 <td class="paramtype"> </td>
2004 <td class="paramname">x</td><td>)</td>
2005 <td>   (((uint32_t)(((uint32_t)(x)) /*<< <a class="el" href="core__ca_8h.html#a9a22d0d7c3a9201db3450b6e6f903990">GICDistributor_CLRSPI_NSR_INTID_Pos</a>*/)) & <a class="el" href="core__ca_8h.html#a7bb3492a25e6309a18464dca7135e58f">GICDistributor_CLRSPI_NSR_INTID_Msk</a>)</td>
2008 </div><div class="memdoc">
2012 <a id="a7bb3492a25e6309a18464dca7135e58f" name="a7bb3492a25e6309a18464dca7135e58f"></a>
2013 <h2 class="memtitle"><span class="permalink"><a href="#a7bb3492a25e6309a18464dca7135e58f">◆ </a></span>GICDistributor_CLRSPI_NSR_INTID_Msk</h2>
2015 <div class="memitem">
2016 <div class="memproto">
2017 <table class="memname">
2019 <td class="memname">#define GICDistributor_CLRSPI_NSR_INTID_Msk   (0x3FFU /*<< <a class="el" href="core__ca_8h.html#a9a22d0d7c3a9201db3450b6e6f903990">GICDistributor_CLRSPI_NSR_INTID_Pos</a>*/)</td>
2022 </div><div class="memdoc">
2023 <p>GICDistributor CLRSPI_NSR: INTID Mask </p>
2027 <a id="a9a22d0d7c3a9201db3450b6e6f903990" name="a9a22d0d7c3a9201db3450b6e6f903990"></a>
2028 <h2 class="memtitle"><span class="permalink"><a href="#a9a22d0d7c3a9201db3450b6e6f903990">◆ </a></span>GICDistributor_CLRSPI_NSR_INTID_Pos</h2>
2030 <div class="memitem">
2031 <div class="memproto">
2032 <table class="memname">
2034 <td class="memname">#define GICDistributor_CLRSPI_NSR_INTID_Pos   0U</td>
2037 </div><div class="memdoc">
2038 <p>GICDistributor CLRSPI_NSR: INTID Position </p>
2042 <a id="a75c8afc3bee11acef651f89458683d50" name="a75c8afc3bee11acef651f89458683d50"></a>
2043 <h2 class="memtitle"><span class="permalink"><a href="#a75c8afc3bee11acef651f89458683d50">◆ </a></span>GICDistributor_CLRSPI_SR_INTID</h2>
2045 <div class="memitem">
2046 <div class="memproto">
2047 <table class="memname">
2049 <td class="memname">#define GICDistributor_CLRSPI_SR_INTID</td>
2051 <td class="paramtype"> </td>
2052 <td class="paramname">x</td><td>)</td>
2053 <td>   (((uint32_t)(((uint32_t)(x)) /*<< <a class="el" href="core__ca_8h.html#a7d6ddee654f6cdbba19948b3cc160ba5">GICDistributor_CLRSPI_SR_INTID_Pos</a>*/)) & <a class="el" href="core__ca_8h.html#a8ef78b7979f3b007c9fba55faae15f78">GICDistributor_CLRSPI_SR_INTID_Msk</a>)</td>
2056 </div><div class="memdoc">
2060 <a id="a8ef78b7979f3b007c9fba55faae15f78" name="a8ef78b7979f3b007c9fba55faae15f78"></a>
2061 <h2 class="memtitle"><span class="permalink"><a href="#a8ef78b7979f3b007c9fba55faae15f78">◆ </a></span>GICDistributor_CLRSPI_SR_INTID_Msk</h2>
2063 <div class="memitem">
2064 <div class="memproto">
2065 <table class="memname">
2067 <td class="memname">#define GICDistributor_CLRSPI_SR_INTID_Msk   (0x3FFU /*<< <a class="el" href="core__ca_8h.html#a7d6ddee654f6cdbba19948b3cc160ba5">GICDistributor_CLRSPI_SR_INTID_Pos</a>*/)</td>
2070 </div><div class="memdoc">
2071 <p>GICDistributor CLRSPI_SR: INTID Mask </p>
2075 <a id="a7d6ddee654f6cdbba19948b3cc160ba5" name="a7d6ddee654f6cdbba19948b3cc160ba5"></a>
2076 <h2 class="memtitle"><span class="permalink"><a href="#a7d6ddee654f6cdbba19948b3cc160ba5">◆ </a></span>GICDistributor_CLRSPI_SR_INTID_Pos</h2>
2078 <div class="memitem">
2079 <div class="memproto">
2080 <table class="memname">
2082 <td class="memname">#define GICDistributor_CLRSPI_SR_INTID_Pos   0U</td>
2085 </div><div class="memdoc">
2086 <p>GICDistributor CLRSPI_SR: INTID Position </p>
2090 <a id="aa4fd56267dab50340aba85e9a0a40636" name="aa4fd56267dab50340aba85e9a0a40636"></a>
2091 <h2 class="memtitle"><span class="permalink"><a href="#aa4fd56267dab50340aba85e9a0a40636">◆ </a></span>GICDistributor_CTLR_ARE</h2>
2093 <div class="memitem">
2094 <div class="memproto">
2095 <table class="memname">
2097 <td class="memname">#define GICDistributor_CTLR_ARE</td>
2099 <td class="paramtype"> </td>
2100 <td class="paramname">x</td><td>)</td>
2101 <td>   (((uint32_t)(((uint32_t)(x)) << <a class="el" href="core__ca_8h.html#a81f2c37daf33d78f1a329a6def5c74ef">GICDistributor_CTLR_ARE_Pos</a>)) & <a class="el" href="core__ca_8h.html#a2cd6a6d7ab225eade558f73a5df30414">GICDistributor_CTLR_ARE_Msk</a>)</td>
2104 </div><div class="memdoc">
2108 <a id="a2cd6a6d7ab225eade558f73a5df30414" name="a2cd6a6d7ab225eade558f73a5df30414"></a>
2109 <h2 class="memtitle"><span class="permalink"><a href="#a2cd6a6d7ab225eade558f73a5df30414">◆ </a></span>GICDistributor_CTLR_ARE_Msk</h2>
2111 <div class="memitem">
2112 <div class="memproto">
2113 <table class="memname">
2115 <td class="memname">#define GICDistributor_CTLR_ARE_Msk   (0x1U << <a class="el" href="core__ca_8h.html#a81f2c37daf33d78f1a329a6def5c74ef">GICDistributor_CTLR_ARE_Pos</a>)</td>
2118 </div><div class="memdoc">
2119 <p>GICDistributor CTLR: ARE Mask </p>
2123 <a id="a81f2c37daf33d78f1a329a6def5c74ef" name="a81f2c37daf33d78f1a329a6def5c74ef"></a>
2124 <h2 class="memtitle"><span class="permalink"><a href="#a81f2c37daf33d78f1a329a6def5c74ef">◆ </a></span>GICDistributor_CTLR_ARE_Pos</h2>
2126 <div class="memitem">
2127 <div class="memproto">
2128 <table class="memname">
2130 <td class="memname">#define GICDistributor_CTLR_ARE_Pos   4U</td>
2133 </div><div class="memdoc">
2134 <p>GICDistributor CTLR: ARE Position </p>
2138 <a id="ab62c27b779ebcf1b000ffc618e26a701" name="ab62c27b779ebcf1b000ffc618e26a701"></a>
2139 <h2 class="memtitle"><span class="permalink"><a href="#ab62c27b779ebcf1b000ffc618e26a701">◆ </a></span>GICDistributor_CTLR_DC</h2>
2141 <div class="memitem">
2142 <div class="memproto">
2143 <table class="memname">
2145 <td class="memname">#define GICDistributor_CTLR_DC</td>
2147 <td class="paramtype"> </td>
2148 <td class="paramname">x</td><td>)</td>
2149 <td>   (((uint32_t)(((uint32_t)(x)) << <a class="el" href="core__ca_8h.html#a6fe71b805728da3adf3c7e8a4974aa1d">GICDistributor_CTLR_DC_Pos</a>)) & <a class="el" href="core__ca_8h.html#a9d0a78a3b6172c15ad1181ac916f9d39">GICDistributor_CTLR_DC_Msk</a>)</td>
2152 </div><div class="memdoc">
2156 <a id="a9d0a78a3b6172c15ad1181ac916f9d39" name="a9d0a78a3b6172c15ad1181ac916f9d39"></a>
2157 <h2 class="memtitle"><span class="permalink"><a href="#a9d0a78a3b6172c15ad1181ac916f9d39">◆ </a></span>GICDistributor_CTLR_DC_Msk</h2>
2159 <div class="memitem">
2160 <div class="memproto">
2161 <table class="memname">
2163 <td class="memname">#define GICDistributor_CTLR_DC_Msk   (0x1U << <a class="el" href="core__ca_8h.html#a6fe71b805728da3adf3c7e8a4974aa1d">GICDistributor_CTLR_DC_Pos</a>)</td>
2166 </div><div class="memdoc">
2167 <p>GICDistributor CTLR: DC Mask </p>
2171 <a id="a6fe71b805728da3adf3c7e8a4974aa1d" name="a6fe71b805728da3adf3c7e8a4974aa1d"></a>
2172 <h2 class="memtitle"><span class="permalink"><a href="#a6fe71b805728da3adf3c7e8a4974aa1d">◆ </a></span>GICDistributor_CTLR_DC_Pos</h2>
2174 <div class="memitem">
2175 <div class="memproto">
2176 <table class="memname">
2178 <td class="memname">#define GICDistributor_CTLR_DC_Pos   6U</td>
2181 </div><div class="memdoc">
2182 <p>GICDistributor CTLR: DC Position </p>
2186 <a id="a4bbd88a0c4f83a49680cb45fc43fcd8b" name="a4bbd88a0c4f83a49680cb45fc43fcd8b"></a>
2187 <h2 class="memtitle"><span class="permalink"><a href="#a4bbd88a0c4f83a49680cb45fc43fcd8b">◆ </a></span>GICDistributor_CTLR_EINWF</h2>
2189 <div class="memitem">
2190 <div class="memproto">
2191 <table class="memname">
2193 <td class="memname">#define GICDistributor_CTLR_EINWF</td>
2195 <td class="paramtype"> </td>
2196 <td class="paramname">x</td><td>)</td>
2197 <td>   (((uint32_t)(((uint32_t)(x)) << <a class="el" href="core__ca_8h.html#a199b879ac14e2c8066e46eb3daa51da3">GICDistributor_CTLR_EINWF_Pos</a>)) & <a class="el" href="core__ca_8h.html#a7e984cf330bd971739937957f551c71d">GICDistributor_CTLR_EINWF_Msk</a>)</td>
2200 </div><div class="memdoc">
2204 <a id="a7e984cf330bd971739937957f551c71d" name="a7e984cf330bd971739937957f551c71d"></a>
2205 <h2 class="memtitle"><span class="permalink"><a href="#a7e984cf330bd971739937957f551c71d">◆ </a></span>GICDistributor_CTLR_EINWF_Msk</h2>
2207 <div class="memitem">
2208 <div class="memproto">
2209 <table class="memname">
2211 <td class="memname">#define GICDistributor_CTLR_EINWF_Msk   (0x1U << <a class="el" href="core__ca_8h.html#a199b879ac14e2c8066e46eb3daa51da3">GICDistributor_CTLR_EINWF_Pos</a>)</td>
2214 </div><div class="memdoc">
2215 <p>GICDistributor CTLR: EINWF Mask </p>
2219 <a id="a199b879ac14e2c8066e46eb3daa51da3" name="a199b879ac14e2c8066e46eb3daa51da3"></a>
2220 <h2 class="memtitle"><span class="permalink"><a href="#a199b879ac14e2c8066e46eb3daa51da3">◆ </a></span>GICDistributor_CTLR_EINWF_Pos</h2>
2222 <div class="memitem">
2223 <div class="memproto">
2224 <table class="memname">
2226 <td class="memname">#define GICDistributor_CTLR_EINWF_Pos   7U</td>
2229 </div><div class="memdoc">
2230 <p>GICDistributor CTLR: EINWF Position </p>
2234 <a id="a60d6f24a53ad5a82a09caf3e7a0c5526" name="a60d6f24a53ad5a82a09caf3e7a0c5526"></a>
2235 <h2 class="memtitle"><span class="permalink"><a href="#a60d6f24a53ad5a82a09caf3e7a0c5526">◆ </a></span>GICDistributor_CTLR_EnableGrp0</h2>
2237 <div class="memitem">
2238 <div class="memproto">
2239 <table class="memname">
2241 <td class="memname">#define GICDistributor_CTLR_EnableGrp0</td>
2243 <td class="paramtype"> </td>
2244 <td class="paramname">x</td><td>)</td>
2245 <td>   (((uint32_t)(((uint32_t)(x)) /*<< <a class="el" href="core__ca_8h.html#ad5209e6ff9566012bb004b2f09d0b81f">GICDistributor_CTLR_EnableGrp0_Pos</a>*/)) & <a class="el" href="core__ca_8h.html#a753335218b36284c4d01f51469d3a202">GICDistributor_CTLR_EnableGrp0_Msk</a>)</td>
2248 </div><div class="memdoc">
2252 <a id="a753335218b36284c4d01f51469d3a202" name="a753335218b36284c4d01f51469d3a202"></a>
2253 <h2 class="memtitle"><span class="permalink"><a href="#a753335218b36284c4d01f51469d3a202">◆ </a></span>GICDistributor_CTLR_EnableGrp0_Msk</h2>
2255 <div class="memitem">
2256 <div class="memproto">
2257 <table class="memname">
2259 <td class="memname">#define GICDistributor_CTLR_EnableGrp0_Msk   (0x1U /*<< <a class="el" href="core__ca_8h.html#ad5209e6ff9566012bb004b2f09d0b81f">GICDistributor_CTLR_EnableGrp0_Pos</a>*/)</td>
2262 </div><div class="memdoc">
2263 <p>GICDistributor CTLR: EnableGrp0 Mask </p>
2267 <a id="ad5209e6ff9566012bb004b2f09d0b81f" name="ad5209e6ff9566012bb004b2f09d0b81f"></a>
2268 <h2 class="memtitle"><span class="permalink"><a href="#ad5209e6ff9566012bb004b2f09d0b81f">◆ </a></span>GICDistributor_CTLR_EnableGrp0_Pos</h2>
2270 <div class="memitem">
2271 <div class="memproto">
2272 <table class="memname">
2274 <td class="memname">#define GICDistributor_CTLR_EnableGrp0_Pos   0U</td>
2277 </div><div class="memdoc">
2278 <p>GICDistributor CTLR: EnableGrp0 Position </p>
2282 <a id="a37803802488aec1ffd64006fa52a7338" name="a37803802488aec1ffd64006fa52a7338"></a>
2283 <h2 class="memtitle"><span class="permalink"><a href="#a37803802488aec1ffd64006fa52a7338">◆ </a></span>GICDistributor_CTLR_EnableGrp1</h2>
2285 <div class="memitem">
2286 <div class="memproto">
2287 <table class="memname">
2289 <td class="memname">#define GICDistributor_CTLR_EnableGrp1</td>
2291 <td class="paramtype"> </td>
2292 <td class="paramname">x</td><td>)</td>
2293 <td>   (((uint32_t)(((uint32_t)(x)) << <a class="el" href="core__ca_8h.html#aff60a1c3075aa9e91504f9665ad502af">GICDistributor_CTLR_EnableGrp1_Pos</a>)) & <a class="el" href="core__ca_8h.html#a2730ca50431156282915c03a16856bb2">GICDistributor_CTLR_EnableGrp1_Msk</a>)</td>
2296 </div><div class="memdoc">
2300 <a id="a2730ca50431156282915c03a16856bb2" name="a2730ca50431156282915c03a16856bb2"></a>
2301 <h2 class="memtitle"><span class="permalink"><a href="#a2730ca50431156282915c03a16856bb2">◆ </a></span>GICDistributor_CTLR_EnableGrp1_Msk</h2>
2303 <div class="memitem">
2304 <div class="memproto">
2305 <table class="memname">
2307 <td class="memname">#define GICDistributor_CTLR_EnableGrp1_Msk   (0x1U << <a class="el" href="core__ca_8h.html#aff60a1c3075aa9e91504f9665ad502af">GICDistributor_CTLR_EnableGrp1_Pos</a>)</td>
2310 </div><div class="memdoc">
2311 <p>GICDistributor CTLR: EnableGrp1 Mask </p>
2315 <a id="aff60a1c3075aa9e91504f9665ad502af" name="aff60a1c3075aa9e91504f9665ad502af"></a>
2316 <h2 class="memtitle"><span class="permalink"><a href="#aff60a1c3075aa9e91504f9665ad502af">◆ </a></span>GICDistributor_CTLR_EnableGrp1_Pos</h2>
2318 <div class="memitem">
2319 <div class="memproto">
2320 <table class="memname">
2322 <td class="memname">#define GICDistributor_CTLR_EnableGrp1_Pos   1U</td>
2325 </div><div class="memdoc">
2326 <p>GICDistributor CTLR: EnableGrp1 Position </p>
2330 <a id="a41778c5267d09a031f23a13e98c4f9eb" name="a41778c5267d09a031f23a13e98c4f9eb"></a>
2331 <h2 class="memtitle"><span class="permalink"><a href="#a41778c5267d09a031f23a13e98c4f9eb">◆ </a></span>GICDistributor_CTLR_RWP</h2>
2333 <div class="memitem">
2334 <div class="memproto">
2335 <table class="memname">
2337 <td class="memname">#define GICDistributor_CTLR_RWP</td>
2339 <td class="paramtype"> </td>
2340 <td class="paramname">x</td><td>)</td>
2341 <td>   (((uint32_t)(((uint32_t)(x)) << <a class="el" href="core__ca_8h.html#a4432e051814aedccbc1dc83421b7f386">GICDistributor_CTLR_RWP_Pos</a>)) & <a class="el" href="core__ca_8h.html#a0b756d72f4e78786290aff157b3862de">GICDistributor_CTLR_RWP_Msk</a>)</td>
2344 </div><div class="memdoc">
2348 <a id="a0b756d72f4e78786290aff157b3862de" name="a0b756d72f4e78786290aff157b3862de"></a>
2349 <h2 class="memtitle"><span class="permalink"><a href="#a0b756d72f4e78786290aff157b3862de">◆ </a></span>GICDistributor_CTLR_RWP_Msk</h2>
2351 <div class="memitem">
2352 <div class="memproto">
2353 <table class="memname">
2355 <td class="memname">#define GICDistributor_CTLR_RWP_Msk   (0x1U << <a class="el" href="core__ca_8h.html#a4432e051814aedccbc1dc83421b7f386">GICDistributor_CTLR_RWP_Pos</a>)</td>
2358 </div><div class="memdoc">
2359 <p>GICDistributor CTLR: RWP Mask </p>
2363 <a id="a4432e051814aedccbc1dc83421b7f386" name="a4432e051814aedccbc1dc83421b7f386"></a>
2364 <h2 class="memtitle"><span class="permalink"><a href="#a4432e051814aedccbc1dc83421b7f386">◆ </a></span>GICDistributor_CTLR_RWP_Pos</h2>
2366 <div class="memitem">
2367 <div class="memproto">
2368 <table class="memname">
2370 <td class="memname">#define GICDistributor_CTLR_RWP_Pos   31U</td>
2373 </div><div class="memdoc">
2374 <p>GICDistributor CTLR: RWP Position </p>
2378 <a id="a1df00605bff4fecab35a378bcdee277f" name="a1df00605bff4fecab35a378bcdee277f"></a>
2379 <h2 class="memtitle"><span class="permalink"><a href="#a1df00605bff4fecab35a378bcdee277f">◆ </a></span>GICDistributor_IIDR_Implementer</h2>
2381 <div class="memitem">
2382 <div class="memproto">
2383 <table class="memname">
2385 <td class="memname">#define GICDistributor_IIDR_Implementer</td>
2387 <td class="paramtype"> </td>
2388 <td class="paramname">x</td><td>)</td>
2389 <td>   (((uint32_t)(((uint32_t)(x)) /*<< <a class="el" href="core__ca_8h.html#ad5cb2a02c6484a02d8599a4eec83cdeb">GICDistributor_IIDR_Implementer_Pos</a>*/)) & <a class="el" href="core__ca_8h.html#af6cf5679673b9e21f29e9d3e4cf0096f">GICDistributor_IIDR_Implementer_Msk</a>)</td>
2392 </div><div class="memdoc">
2396 <a id="af6cf5679673b9e21f29e9d3e4cf0096f" name="af6cf5679673b9e21f29e9d3e4cf0096f"></a>
2397 <h2 class="memtitle"><span class="permalink"><a href="#af6cf5679673b9e21f29e9d3e4cf0096f">◆ </a></span>GICDistributor_IIDR_Implementer_Msk</h2>
2399 <div class="memitem">
2400 <div class="memproto">
2401 <table class="memname">
2403 <td class="memname">#define GICDistributor_IIDR_Implementer_Msk   (0xFFFU /*<< <a class="el" href="core__ca_8h.html#ad5cb2a02c6484a02d8599a4eec83cdeb">GICDistributor_IIDR_Implementer_Pos</a>*/)</td>
2406 </div><div class="memdoc">
2407 <p>GICDistributor IIDR: Implementer Mask </p>
2411 <a id="ad5cb2a02c6484a02d8599a4eec83cdeb" name="ad5cb2a02c6484a02d8599a4eec83cdeb"></a>
2412 <h2 class="memtitle"><span class="permalink"><a href="#ad5cb2a02c6484a02d8599a4eec83cdeb">◆ </a></span>GICDistributor_IIDR_Implementer_Pos</h2>
2414 <div class="memitem">
2415 <div class="memproto">
2416 <table class="memname">
2418 <td class="memname">#define GICDistributor_IIDR_Implementer_Pos   0U</td>
2421 </div><div class="memdoc">
2422 <p>GICDistributor IIDR: Implementer Position </p>
2426 <a id="a3ef98229da161c0438791171919222c2" name="a3ef98229da161c0438791171919222c2"></a>
2427 <h2 class="memtitle"><span class="permalink"><a href="#a3ef98229da161c0438791171919222c2">◆ </a></span>GICDistributor_IIDR_ProductID</h2>
2429 <div class="memitem">
2430 <div class="memproto">
2431 <table class="memname">
2433 <td class="memname">#define GICDistributor_IIDR_ProductID</td>
2435 <td class="paramtype"> </td>
2436 <td class="paramname">x</td><td>)</td>
2437 <td>   (((uint32_t)(((uint32_t)(x)) << <a class="el" href="core__ca_8h.html#ab833f27680c28ec66b0fb9c00765b941">GICDistributor_IIDR_ProductID_Pos</a>)) & <a class="el" href="core__ca_8h.html#a8e6d7553302e4326de3b89cc38e7538f">GICDistributor_IIDR_ProductID_Msk</a>)</td>
2440 </div><div class="memdoc">
2444 <a id="a8e6d7553302e4326de3b89cc38e7538f" name="a8e6d7553302e4326de3b89cc38e7538f"></a>
2445 <h2 class="memtitle"><span class="permalink"><a href="#a8e6d7553302e4326de3b89cc38e7538f">◆ </a></span>GICDistributor_IIDR_ProductID_Msk</h2>
2447 <div class="memitem">
2448 <div class="memproto">
2449 <table class="memname">
2451 <td class="memname">#define GICDistributor_IIDR_ProductID_Msk   (0xFFU << <a class="el" href="core__ca_8h.html#ab833f27680c28ec66b0fb9c00765b941">GICDistributor_IIDR_ProductID_Pos</a>)</td>
2454 </div><div class="memdoc">
2455 <p>GICDistributor IIDR: ProductID Mask </p>
2459 <a id="ab833f27680c28ec66b0fb9c00765b941" name="ab833f27680c28ec66b0fb9c00765b941"></a>
2460 <h2 class="memtitle"><span class="permalink"><a href="#ab833f27680c28ec66b0fb9c00765b941">◆ </a></span>GICDistributor_IIDR_ProductID_Pos</h2>
2462 <div class="memitem">
2463 <div class="memproto">
2464 <table class="memname">
2466 <td class="memname">#define GICDistributor_IIDR_ProductID_Pos   24U</td>
2469 </div><div class="memdoc">
2470 <p>GICDistributor IIDR: ProductID Position </p>
2474 <a id="ab7bc3dde66b114b7d20c672e108d9386" name="ab7bc3dde66b114b7d20c672e108d9386"></a>
2475 <h2 class="memtitle"><span class="permalink"><a href="#ab7bc3dde66b114b7d20c672e108d9386">◆ </a></span>GICDistributor_IIDR_Revision</h2>
2477 <div class="memitem">
2478 <div class="memproto">
2479 <table class="memname">
2481 <td class="memname">#define GICDistributor_IIDR_Revision</td>
2483 <td class="paramtype"> </td>
2484 <td class="paramname">x</td><td>)</td>
2485 <td>   (((uint32_t)(((uint32_t)(x)) << <a class="el" href="core__ca_8h.html#af12891c46bd7555919f5df7771eadb09">GICDistributor_IIDR_Revision_Pos</a>)) & <a class="el" href="core__ca_8h.html#aaa5816799e45c7aaf832c847c4b333ba">GICDistributor_IIDR_Revision_Msk</a>)</td>
2488 </div><div class="memdoc">
2492 <a id="aaa5816799e45c7aaf832c847c4b333ba" name="aaa5816799e45c7aaf832c847c4b333ba"></a>
2493 <h2 class="memtitle"><span class="permalink"><a href="#aaa5816799e45c7aaf832c847c4b333ba">◆ </a></span>GICDistributor_IIDR_Revision_Msk</h2>
2495 <div class="memitem">
2496 <div class="memproto">
2497 <table class="memname">
2499 <td class="memname">#define GICDistributor_IIDR_Revision_Msk   (0xFU << <a class="el" href="core__ca_8h.html#af12891c46bd7555919f5df7771eadb09">GICDistributor_IIDR_Revision_Pos</a>)</td>
2502 </div><div class="memdoc">
2503 <p>GICDistributor IIDR: Revision Mask </p>
2507 <a id="af12891c46bd7555919f5df7771eadb09" name="af12891c46bd7555919f5df7771eadb09"></a>
2508 <h2 class="memtitle"><span class="permalink"><a href="#af12891c46bd7555919f5df7771eadb09">◆ </a></span>GICDistributor_IIDR_Revision_Pos</h2>
2510 <div class="memitem">
2511 <div class="memproto">
2512 <table class="memname">
2514 <td class="memname">#define GICDistributor_IIDR_Revision_Pos   12U</td>
2517 </div><div class="memdoc">
2518 <p>GICDistributor IIDR: Revision Position </p>
2522 <a id="a8380fa71d0da5db1773adacfade1a07b" name="a8380fa71d0da5db1773adacfade1a07b"></a>
2523 <h2 class="memtitle"><span class="permalink"><a href="#a8380fa71d0da5db1773adacfade1a07b">◆ </a></span>GICDistributor_IIDR_Variant</h2>
2525 <div class="memitem">
2526 <div class="memproto">
2527 <table class="memname">
2529 <td class="memname">#define GICDistributor_IIDR_Variant</td>
2531 <td class="paramtype"> </td>
2532 <td class="paramname">x</td><td>)</td>
2533 <td>   (((uint32_t)(((uint32_t)(x)) << <a class="el" href="core__ca_8h.html#ab7a79131c7af76dba9bbecd15d4e2117">GICDistributor_IIDR_Variant_Pos</a>)) & <a class="el" href="core__ca_8h.html#ab0d681a61eb8013e4216392306d6c70b">GICDistributor_IIDR_Variant_Msk</a>)</td>
2536 </div><div class="memdoc">
2540 <a id="ab0d681a61eb8013e4216392306d6c70b" name="ab0d681a61eb8013e4216392306d6c70b"></a>
2541 <h2 class="memtitle"><span class="permalink"><a href="#ab0d681a61eb8013e4216392306d6c70b">◆ </a></span>GICDistributor_IIDR_Variant_Msk</h2>
2543 <div class="memitem">
2544 <div class="memproto">
2545 <table class="memname">
2547 <td class="memname">#define GICDistributor_IIDR_Variant_Msk   (0xFU << <a class="el" href="core__ca_8h.html#ab7a79131c7af76dba9bbecd15d4e2117">GICDistributor_IIDR_Variant_Pos</a>)</td>
2550 </div><div class="memdoc">
2551 <p>GICDistributor IIDR: Variant Mask </p>
2555 <a id="ab7a79131c7af76dba9bbecd15d4e2117" name="ab7a79131c7af76dba9bbecd15d4e2117"></a>
2556 <h2 class="memtitle"><span class="permalink"><a href="#ab7a79131c7af76dba9bbecd15d4e2117">◆ </a></span>GICDistributor_IIDR_Variant_Pos</h2>
2558 <div class="memitem">
2559 <div class="memproto">
2560 <table class="memname">
2562 <td class="memname">#define GICDistributor_IIDR_Variant_Pos   16U</td>
2565 </div><div class="memdoc">
2566 <p>GICDistributor IIDR: Variant Position </p>
2570 <a id="a0fedb67ce7387bdf6003d4f8c9b2c3ae" name="a0fedb67ce7387bdf6003d4f8c9b2c3ae"></a>
2571 <h2 class="memtitle"><span class="permalink"><a href="#a0fedb67ce7387bdf6003d4f8c9b2c3ae">◆ </a></span>GICDistributor_IROUTER_Aff0</h2>
2573 <div class="memitem">
2574 <div class="memproto">
2575 <table class="memname">
2577 <td class="memname">#define GICDistributor_IROUTER_Aff0</td>
2579 <td class="paramtype"> </td>
2580 <td class="paramname">x</td><td>)</td>
2581 <td>   (((uint64_t)(((uint64_t)(x)) /*<< <a class="el" href="core__ca_8h.html#ac400154f3e091ce5c0c04099349be036">GICDistributor_IROUTER_Aff0_Pos</a>*/)) & <a class="el" href="core__ca_8h.html#a7154061efbf0bc6e0604788f3c8aade0">GICDistributor_IROUTER_Aff0_Msk</a>)</td>
2584 </div><div class="memdoc">
2588 <a id="a7154061efbf0bc6e0604788f3c8aade0" name="a7154061efbf0bc6e0604788f3c8aade0"></a>
2589 <h2 class="memtitle"><span class="permalink"><a href="#a7154061efbf0bc6e0604788f3c8aade0">◆ </a></span>GICDistributor_IROUTER_Aff0_Msk</h2>
2591 <div class="memitem">
2592 <div class="memproto">
2593 <table class="memname">
2595 <td class="memname">#define GICDistributor_IROUTER_Aff0_Msk   (0xFFUL /*<< <a class="el" href="core__ca_8h.html#ac400154f3e091ce5c0c04099349be036">GICDistributor_IROUTER_Aff0_Pos</a>*/)</td>
2598 </div><div class="memdoc">
2599 <p>GICDistributor IROUTER: Aff0 Mask </p>
2603 <a id="ac400154f3e091ce5c0c04099349be036" name="ac400154f3e091ce5c0c04099349be036"></a>
2604 <h2 class="memtitle"><span class="permalink"><a href="#ac400154f3e091ce5c0c04099349be036">◆ </a></span>GICDistributor_IROUTER_Aff0_Pos</h2>
2606 <div class="memitem">
2607 <div class="memproto">
2608 <table class="memname">
2610 <td class="memname">#define GICDistributor_IROUTER_Aff0_Pos   0UL</td>
2613 </div><div class="memdoc">
2614 <p>GICDistributor IROUTER: Aff0 Position </p>
2618 <a id="a6e35d64ab673e292bb88f6dc12172cec" name="a6e35d64ab673e292bb88f6dc12172cec"></a>
2619 <h2 class="memtitle"><span class="permalink"><a href="#a6e35d64ab673e292bb88f6dc12172cec">◆ </a></span>GICDistributor_IROUTER_Aff1</h2>
2621 <div class="memitem">
2622 <div class="memproto">
2623 <table class="memname">
2625 <td class="memname">#define GICDistributor_IROUTER_Aff1</td>
2627 <td class="paramtype"> </td>
2628 <td class="paramname">x</td><td>)</td>
2629 <td>   (((uint64_t)(((uint64_t)(x)) << <a class="el" href="core__ca_8h.html#a094d1737af75fe96cc48ec6f54876b73">GICDistributor_IROUTER_Aff1_Pos</a>)) & <a class="el" href="core__ca_8h.html#a1cb898980f65b989eb7010d27ca9d5a7">GICDistributor_IROUTER_Aff1_Msk</a>)</td>
2632 </div><div class="memdoc">
2636 <a id="a1cb898980f65b989eb7010d27ca9d5a7" name="a1cb898980f65b989eb7010d27ca9d5a7"></a>
2637 <h2 class="memtitle"><span class="permalink"><a href="#a1cb898980f65b989eb7010d27ca9d5a7">◆ </a></span>GICDistributor_IROUTER_Aff1_Msk</h2>
2639 <div class="memitem">
2640 <div class="memproto">
2641 <table class="memname">
2643 <td class="memname">#define GICDistributor_IROUTER_Aff1_Msk   (0xFFUL << <a class="el" href="core__ca_8h.html#a094d1737af75fe96cc48ec6f54876b73">GICDistributor_IROUTER_Aff1_Pos</a>)</td>
2646 </div><div class="memdoc">
2647 <p>GICDistributor IROUTER: Aff1 Mask </p>
2651 <a id="a094d1737af75fe96cc48ec6f54876b73" name="a094d1737af75fe96cc48ec6f54876b73"></a>
2652 <h2 class="memtitle"><span class="permalink"><a href="#a094d1737af75fe96cc48ec6f54876b73">◆ </a></span>GICDistributor_IROUTER_Aff1_Pos</h2>
2654 <div class="memitem">
2655 <div class="memproto">
2656 <table class="memname">
2658 <td class="memname">#define GICDistributor_IROUTER_Aff1_Pos   8UL</td>
2661 </div><div class="memdoc">
2662 <p>GICDistributor IROUTER: Aff1 Position </p>
2666 <a id="acc0b09a1d0d8dfbc745a0d3fe1619f8d" name="acc0b09a1d0d8dfbc745a0d3fe1619f8d"></a>
2667 <h2 class="memtitle"><span class="permalink"><a href="#acc0b09a1d0d8dfbc745a0d3fe1619f8d">◆ </a></span>GICDistributor_IROUTER_Aff2</h2>
2669 <div class="memitem">
2670 <div class="memproto">
2671 <table class="memname">
2673 <td class="memname">#define GICDistributor_IROUTER_Aff2</td>
2675 <td class="paramtype"> </td>
2676 <td class="paramname">x</td><td>)</td>
2677 <td>   (((uint64_t)(((uint64_t)(x)) << <a class="el" href="core__ca_8h.html#a3b74de8f0df7bb175a81e0d397039242">GICDistributor_IROUTER_Aff2_Pos</a>)) & <a class="el" href="core__ca_8h.html#a52f6253031637bf0259b84e0e227509b">GICDistributor_IROUTER_Aff2_Msk</a>)</td>
2680 </div><div class="memdoc">
2684 <a id="a52f6253031637bf0259b84e0e227509b" name="a52f6253031637bf0259b84e0e227509b"></a>
2685 <h2 class="memtitle"><span class="permalink"><a href="#a52f6253031637bf0259b84e0e227509b">◆ </a></span>GICDistributor_IROUTER_Aff2_Msk</h2>
2687 <div class="memitem">
2688 <div class="memproto">
2689 <table class="memname">
2691 <td class="memname">#define GICDistributor_IROUTER_Aff2_Msk   (0xFFUL << <a class="el" href="core__ca_8h.html#a3b74de8f0df7bb175a81e0d397039242">GICDistributor_IROUTER_Aff2_Pos</a>)</td>
2694 </div><div class="memdoc">
2695 <p>GICDistributor IROUTER: Aff2 Mask </p>
2699 <a id="a3b74de8f0df7bb175a81e0d397039242" name="a3b74de8f0df7bb175a81e0d397039242"></a>
2700 <h2 class="memtitle"><span class="permalink"><a href="#a3b74de8f0df7bb175a81e0d397039242">◆ </a></span>GICDistributor_IROUTER_Aff2_Pos</h2>
2702 <div class="memitem">
2703 <div class="memproto">
2704 <table class="memname">
2706 <td class="memname">#define GICDistributor_IROUTER_Aff2_Pos   16UL</td>
2709 </div><div class="memdoc">
2710 <p>GICDistributor IROUTER: Aff2 Position </p>
2714 <a id="ad1418cd587ed92264e68c2cbbc18ea2e" name="ad1418cd587ed92264e68c2cbbc18ea2e"></a>
2715 <h2 class="memtitle"><span class="permalink"><a href="#ad1418cd587ed92264e68c2cbbc18ea2e">◆ </a></span>GICDistributor_IROUTER_Aff3</h2>
2717 <div class="memitem">
2718 <div class="memproto">
2719 <table class="memname">
2721 <td class="memname">#define GICDistributor_IROUTER_Aff3</td>
2723 <td class="paramtype"> </td>
2724 <td class="paramname">x</td><td>)</td>
2725 <td>   (((uint64_t)(((uint64_t)(x)) << <a class="el" href="core__ca_8h.html#ac13830edd01d66e99f92ee103cb04d1f">GICDistributor_IROUTER_Aff3_Pos</a>)) & <a class="el" href="core__ca_8h.html#a51a1800358ad5c1f752e49c39cd9e830">GICDistributor_IROUTER_Aff3_Msk</a>)</td>
2728 </div><div class="memdoc">
2732 <a id="a51a1800358ad5c1f752e49c39cd9e830" name="a51a1800358ad5c1f752e49c39cd9e830"></a>
2733 <h2 class="memtitle"><span class="permalink"><a href="#a51a1800358ad5c1f752e49c39cd9e830">◆ </a></span>GICDistributor_IROUTER_Aff3_Msk</h2>
2735 <div class="memitem">
2736 <div class="memproto">
2737 <table class="memname">
2739 <td class="memname">#define GICDistributor_IROUTER_Aff3_Msk   (0xFFUL << <a class="el" href="core__ca_8h.html#ac13830edd01d66e99f92ee103cb04d1f">GICDistributor_IROUTER_Aff3_Pos</a>)</td>
2742 </div><div class="memdoc">
2743 <p>GICDistributor IROUTER: Aff3 Mask </p>
2747 <a id="ac13830edd01d66e99f92ee103cb04d1f" name="ac13830edd01d66e99f92ee103cb04d1f"></a>
2748 <h2 class="memtitle"><span class="permalink"><a href="#ac13830edd01d66e99f92ee103cb04d1f">◆ </a></span>GICDistributor_IROUTER_Aff3_Pos</h2>
2750 <div class="memitem">
2751 <div class="memproto">
2752 <table class="memname">
2754 <td class="memname">#define GICDistributor_IROUTER_Aff3_Pos   32UL</td>
2757 </div><div class="memdoc">
2758 <p>GICDistributor IROUTER: Aff3 Position </p>
2762 <a id="a5d3044d648a99a8611ace4afc0590979" name="a5d3044d648a99a8611ace4afc0590979"></a>
2763 <h2 class="memtitle"><span class="permalink"><a href="#a5d3044d648a99a8611ace4afc0590979">◆ </a></span>GICDistributor_IROUTER_IRM</h2>
2765 <div class="memitem">
2766 <div class="memproto">
2767 <table class="memname">
2769 <td class="memname">#define GICDistributor_IROUTER_IRM</td>
2771 <td class="paramtype"> </td>
2772 <td class="paramname">x</td><td>)</td>
2773 <td>   (((uint64_t)(((uint64_t)(x)) << <a class="el" href="core__ca_8h.html#a622e872ac3a47cd90d1a7154d123abea">GICDistributor_IROUTER_IRM_Pos</a>)) & <a class="el" href="core__ca_8h.html#a4cec345b240a7e84c6624e153b97b4d6">GICDistributor_IROUTER_IRM_Msk</a>)</td>
2776 </div><div class="memdoc">
2780 <a id="a4cec345b240a7e84c6624e153b97b4d6" name="a4cec345b240a7e84c6624e153b97b4d6"></a>
2781 <h2 class="memtitle"><span class="permalink"><a href="#a4cec345b240a7e84c6624e153b97b4d6">◆ </a></span>GICDistributor_IROUTER_IRM_Msk</h2>
2783 <div class="memitem">
2784 <div class="memproto">
2785 <table class="memname">
2787 <td class="memname">#define GICDistributor_IROUTER_IRM_Msk   (0xFFUL << <a class="el" href="core__ca_8h.html#a622e872ac3a47cd90d1a7154d123abea">GICDistributor_IROUTER_IRM_Pos</a>)</td>
2790 </div><div class="memdoc">
2791 <p>GICDistributor IROUTER: IRM Mask </p>
2795 <a id="a622e872ac3a47cd90d1a7154d123abea" name="a622e872ac3a47cd90d1a7154d123abea"></a>
2796 <h2 class="memtitle"><span class="permalink"><a href="#a622e872ac3a47cd90d1a7154d123abea">◆ </a></span>GICDistributor_IROUTER_IRM_Pos</h2>
2798 <div class="memitem">
2799 <div class="memproto">
2800 <table class="memname">
2802 <td class="memname">#define GICDistributor_IROUTER_IRM_Pos   31UL</td>
2805 </div><div class="memdoc">
2806 <p>GICDistributor IROUTER: IRM Position </p>
2810 <a id="a276be33ef8d9aeecda6e1290400b0a2e" name="a276be33ef8d9aeecda6e1290400b0a2e"></a>
2811 <h2 class="memtitle"><span class="permalink"><a href="#a276be33ef8d9aeecda6e1290400b0a2e">◆ </a></span>GICDistributor_ITARGETSR_CPU0</h2>
2813 <div class="memitem">
2814 <div class="memproto">
2815 <table class="memname">
2817 <td class="memname">#define GICDistributor_ITARGETSR_CPU0</td>
2819 <td class="paramtype"> </td>
2820 <td class="paramname">x</td><td>)</td>
2821 <td>   (((uint8_t)(((uint8_t)(x)) /*<< <a class="el" href="core__ca_8h.html#a28353192a0298bd7f35648df54839029">GICDistributor_ITARGETSR_CPU0_Pos</a>*/)) & <a class="el" href="core__ca_8h.html#a56fcab6b4afdd0998d8cbd351b060a42">GICDistributor_ITARGETSR_CPU0_Msk</a>)</td>
2824 </div><div class="memdoc">
2828 <a id="a56fcab6b4afdd0998d8cbd351b060a42" name="a56fcab6b4afdd0998d8cbd351b060a42"></a>
2829 <h2 class="memtitle"><span class="permalink"><a href="#a56fcab6b4afdd0998d8cbd351b060a42">◆ </a></span>GICDistributor_ITARGETSR_CPU0_Msk</h2>
2831 <div class="memitem">
2832 <div class="memproto">
2833 <table class="memname">
2835 <td class="memname">#define GICDistributor_ITARGETSR_CPU0_Msk   (0x1U /*<< <a class="el" href="core__ca_8h.html#a28353192a0298bd7f35648df54839029">GICDistributor_ITARGETSR_CPU0_Pos</a>*/)</td>
2838 </div><div class="memdoc">
2839 <p>GICDistributor ITARGETSR: CPU0 Mask </p>
2843 <a id="a28353192a0298bd7f35648df54839029" name="a28353192a0298bd7f35648df54839029"></a>
2844 <h2 class="memtitle"><span class="permalink"><a href="#a28353192a0298bd7f35648df54839029">◆ </a></span>GICDistributor_ITARGETSR_CPU0_Pos</h2>
2846 <div class="memitem">
2847 <div class="memproto">
2848 <table class="memname">
2850 <td class="memname">#define GICDistributor_ITARGETSR_CPU0_Pos   0U</td>
2853 </div><div class="memdoc">
2854 <p>GICDistributor ITARGETSR: CPU0 Position </p>
2858 <a id="a683207ddcab7bc574b8bb3cb2f12eed8" name="a683207ddcab7bc574b8bb3cb2f12eed8"></a>
2859 <h2 class="memtitle"><span class="permalink"><a href="#a683207ddcab7bc574b8bb3cb2f12eed8">◆ </a></span>GICDistributor_ITARGETSR_CPU1</h2>
2861 <div class="memitem">
2862 <div class="memproto">
2863 <table class="memname">
2865 <td class="memname">#define GICDistributor_ITARGETSR_CPU1</td>
2867 <td class="paramtype"> </td>
2868 <td class="paramname">x</td><td>)</td>
2869 <td>   (((uint8_t)(((uint8_t)(x)) << <a class="el" href="core__ca_8h.html#ac2d3fd8843c99b7b634e390e756e2bbd">GICDistributor_ITARGETSR_CPU1_Pos</a>)) & <a class="el" href="core__ca_8h.html#a02f1660e91258f435ad519c577b43014">GICDistributor_ITARGETSR_CPU1_Msk</a>)</td>
2872 </div><div class="memdoc">
2876 <a id="a02f1660e91258f435ad519c577b43014" name="a02f1660e91258f435ad519c577b43014"></a>
2877 <h2 class="memtitle"><span class="permalink"><a href="#a02f1660e91258f435ad519c577b43014">◆ </a></span>GICDistributor_ITARGETSR_CPU1_Msk</h2>
2879 <div class="memitem">
2880 <div class="memproto">
2881 <table class="memname">
2883 <td class="memname">#define GICDistributor_ITARGETSR_CPU1_Msk   (0x1U << <a class="el" href="core__ca_8h.html#ac2d3fd8843c99b7b634e390e756e2bbd">GICDistributor_ITARGETSR_CPU1_Pos</a>)</td>
2886 </div><div class="memdoc">
2887 <p>GICDistributor ITARGETSR: CPU1 Mask </p>
2891 <a id="ac2d3fd8843c99b7b634e390e756e2bbd" name="ac2d3fd8843c99b7b634e390e756e2bbd"></a>
2892 <h2 class="memtitle"><span class="permalink"><a href="#ac2d3fd8843c99b7b634e390e756e2bbd">◆ </a></span>GICDistributor_ITARGETSR_CPU1_Pos</h2>
2894 <div class="memitem">
2895 <div class="memproto">
2896 <table class="memname">
2898 <td class="memname">#define GICDistributor_ITARGETSR_CPU1_Pos   1U</td>
2901 </div><div class="memdoc">
2902 <p>GICDistributor ITARGETSR: CPU1 Position </p>
2906 <a id="a04bb8c24598b4b9720e1408264129400" name="a04bb8c24598b4b9720e1408264129400"></a>
2907 <h2 class="memtitle"><span class="permalink"><a href="#a04bb8c24598b4b9720e1408264129400">◆ </a></span>GICDistributor_ITARGETSR_CPU2</h2>
2909 <div class="memitem">
2910 <div class="memproto">
2911 <table class="memname">
2913 <td class="memname">#define GICDistributor_ITARGETSR_CPU2</td>
2915 <td class="paramtype"> </td>
2916 <td class="paramname">x</td><td>)</td>
2917 <td>   (((uint8_t)(((uint8_t)(x)) << <a class="el" href="core__ca_8h.html#a8a9407956d72af2b4b697a5184a0fae0">GICDistributor_ITARGETSR_CPU2_Pos</a>)) & <a class="el" href="core__ca_8h.html#ad50526ede6080c3df2af103d43ec969a">GICDistributor_ITARGETSR_CPU2_Msk</a>)</td>
2920 </div><div class="memdoc">
2924 <a id="ad50526ede6080c3df2af103d43ec969a" name="ad50526ede6080c3df2af103d43ec969a"></a>
2925 <h2 class="memtitle"><span class="permalink"><a href="#ad50526ede6080c3df2af103d43ec969a">◆ </a></span>GICDistributor_ITARGETSR_CPU2_Msk</h2>
2927 <div class="memitem">
2928 <div class="memproto">
2929 <table class="memname">
2931 <td class="memname">#define GICDistributor_ITARGETSR_CPU2_Msk   (0x1U << <a class="el" href="core__ca_8h.html#a8a9407956d72af2b4b697a5184a0fae0">GICDistributor_ITARGETSR_CPU2_Pos</a>)</td>
2934 </div><div class="memdoc">
2935 <p>GICDistributor ITARGETSR: CPU2 Mask </p>
2939 <a id="a8a9407956d72af2b4b697a5184a0fae0" name="a8a9407956d72af2b4b697a5184a0fae0"></a>
2940 <h2 class="memtitle"><span class="permalink"><a href="#a8a9407956d72af2b4b697a5184a0fae0">◆ </a></span>GICDistributor_ITARGETSR_CPU2_Pos</h2>
2942 <div class="memitem">
2943 <div class="memproto">
2944 <table class="memname">
2946 <td class="memname">#define GICDistributor_ITARGETSR_CPU2_Pos   2U</td>
2949 </div><div class="memdoc">
2950 <p>GICDistributor ITARGETSR: CPU2 Position </p>
2954 <a id="a2724b8078bf97c07e50c9a8919024cf6" name="a2724b8078bf97c07e50c9a8919024cf6"></a>
2955 <h2 class="memtitle"><span class="permalink"><a href="#a2724b8078bf97c07e50c9a8919024cf6">◆ </a></span>GICDistributor_ITARGETSR_CPU3</h2>
2957 <div class="memitem">
2958 <div class="memproto">
2959 <table class="memname">
2961 <td class="memname">#define GICDistributor_ITARGETSR_CPU3</td>
2963 <td class="paramtype"> </td>
2964 <td class="paramname">x</td><td>)</td>
2965 <td>   (((uint8_t)(((uint8_t)(x)) << <a class="el" href="core__ca_8h.html#a26635639563b054f6cd5a6862a2f2a61">GICDistributor_ITARGETSR_CPU3_Pos</a>)) & <a class="el" href="core__ca_8h.html#ac15f36682e23f172e51fded30108d2f6">GICDistributor_ITARGETSR_CPU3_Msk</a>)</td>
2968 </div><div class="memdoc">
2972 <a id="ac15f36682e23f172e51fded30108d2f6" name="ac15f36682e23f172e51fded30108d2f6"></a>
2973 <h2 class="memtitle"><span class="permalink"><a href="#ac15f36682e23f172e51fded30108d2f6">◆ </a></span>GICDistributor_ITARGETSR_CPU3_Msk</h2>
2975 <div class="memitem">
2976 <div class="memproto">
2977 <table class="memname">
2979 <td class="memname">#define GICDistributor_ITARGETSR_CPU3_Msk   (0x1U << <a class="el" href="core__ca_8h.html#a26635639563b054f6cd5a6862a2f2a61">GICDistributor_ITARGETSR_CPU3_Pos</a>)</td>
2982 </div><div class="memdoc">
2983 <p>GICDistributor ITARGETSR: CPU3 Mask </p>
2987 <a id="a26635639563b054f6cd5a6862a2f2a61" name="a26635639563b054f6cd5a6862a2f2a61"></a>
2988 <h2 class="memtitle"><span class="permalink"><a href="#a26635639563b054f6cd5a6862a2f2a61">◆ </a></span>GICDistributor_ITARGETSR_CPU3_Pos</h2>
2990 <div class="memitem">
2991 <div class="memproto">
2992 <table class="memname">
2994 <td class="memname">#define GICDistributor_ITARGETSR_CPU3_Pos   3U</td>
2997 </div><div class="memdoc">
2998 <p>GICDistributor ITARGETSR: CPU3 Position </p>
3002 <a id="aaffea378b3e1c322658d5605e1c109e6" name="aaffea378b3e1c322658d5605e1c109e6"></a>
3003 <h2 class="memtitle"><span class="permalink"><a href="#aaffea378b3e1c322658d5605e1c109e6">◆ </a></span>GICDistributor_ITARGETSR_CPU4</h2>
3005 <div class="memitem">
3006 <div class="memproto">
3007 <table class="memname">
3009 <td class="memname">#define GICDistributor_ITARGETSR_CPU4</td>
3011 <td class="paramtype"> </td>
3012 <td class="paramname">x</td><td>)</td>
3013 <td>   (((uint8_t)(((uint8_t)(x)) << <a class="el" href="core__ca_8h.html#ae25a0b0c07d793d2d8ad4685f5d9acc2">GICDistributor_ITARGETSR_CPU4_Pos</a>)) & <a class="el" href="core__ca_8h.html#a18a2390a599afb731cef504dc79d1505">GICDistributor_ITARGETSR_CPU4_Msk</a>)</td>
3016 </div><div class="memdoc">
3020 <a id="a18a2390a599afb731cef504dc79d1505" name="a18a2390a599afb731cef504dc79d1505"></a>
3021 <h2 class="memtitle"><span class="permalink"><a href="#a18a2390a599afb731cef504dc79d1505">◆ </a></span>GICDistributor_ITARGETSR_CPU4_Msk</h2>
3023 <div class="memitem">
3024 <div class="memproto">
3025 <table class="memname">
3027 <td class="memname">#define GICDistributor_ITARGETSR_CPU4_Msk   (0x1U << <a class="el" href="core__ca_8h.html#ae25a0b0c07d793d2d8ad4685f5d9acc2">GICDistributor_ITARGETSR_CPU4_Pos</a>)</td>
3030 </div><div class="memdoc">
3031 <p>GICDistributor ITARGETSR: CPU4 Mask </p>
3035 <a id="ae25a0b0c07d793d2d8ad4685f5d9acc2" name="ae25a0b0c07d793d2d8ad4685f5d9acc2"></a>
3036 <h2 class="memtitle"><span class="permalink"><a href="#ae25a0b0c07d793d2d8ad4685f5d9acc2">◆ </a></span>GICDistributor_ITARGETSR_CPU4_Pos</h2>
3038 <div class="memitem">
3039 <div class="memproto">
3040 <table class="memname">
3042 <td class="memname">#define GICDistributor_ITARGETSR_CPU4_Pos   4U</td>
3045 </div><div class="memdoc">
3046 <p>GICDistributor ITARGETSR: CPU4 Position </p>
3050 <a id="ac99060fe12c7fd70e3c3c8452daa5302" name="ac99060fe12c7fd70e3c3c8452daa5302"></a>
3051 <h2 class="memtitle"><span class="permalink"><a href="#ac99060fe12c7fd70e3c3c8452daa5302">◆ </a></span>GICDistributor_ITARGETSR_CPU5</h2>
3053 <div class="memitem">
3054 <div class="memproto">
3055 <table class="memname">
3057 <td class="memname">#define GICDistributor_ITARGETSR_CPU5</td>
3059 <td class="paramtype"> </td>
3060 <td class="paramname">x</td><td>)</td>
3061 <td>   (((uint8_t)(((uint8_t)(x)) << <a class="el" href="core__ca_8h.html#acae2c190f3999809e0d916b77d8bf95a">GICDistributor_ITARGETSR_CPU5_Pos</a>)) & <a class="el" href="core__ca_8h.html#ac814c6b67a080ea70ef020c3a21b0e20">GICDistributor_ITARGETSR_CPU5_Msk</a>)</td>
3064 </div><div class="memdoc">
3068 <a id="ac814c6b67a080ea70ef020c3a21b0e20" name="ac814c6b67a080ea70ef020c3a21b0e20"></a>
3069 <h2 class="memtitle"><span class="permalink"><a href="#ac814c6b67a080ea70ef020c3a21b0e20">◆ </a></span>GICDistributor_ITARGETSR_CPU5_Msk</h2>
3071 <div class="memitem">
3072 <div class="memproto">
3073 <table class="memname">
3075 <td class="memname">#define GICDistributor_ITARGETSR_CPU5_Msk   (0x1U << <a class="el" href="core__ca_8h.html#acae2c190f3999809e0d916b77d8bf95a">GICDistributor_ITARGETSR_CPU5_Pos</a>)</td>
3078 </div><div class="memdoc">
3079 <p>GICDistributor ITARGETSR: CPU5 Mask </p>
3083 <a id="acae2c190f3999809e0d916b77d8bf95a" name="acae2c190f3999809e0d916b77d8bf95a"></a>
3084 <h2 class="memtitle"><span class="permalink"><a href="#acae2c190f3999809e0d916b77d8bf95a">◆ </a></span>GICDistributor_ITARGETSR_CPU5_Pos</h2>
3086 <div class="memitem">
3087 <div class="memproto">
3088 <table class="memname">
3090 <td class="memname">#define GICDistributor_ITARGETSR_CPU5_Pos   5U</td>
3093 </div><div class="memdoc">
3094 <p>GICDistributor ITARGETSR: CPU5 Position </p>
3098 <a id="a48202cd0ad1df93721da27716f35ab99" name="a48202cd0ad1df93721da27716f35ab99"></a>
3099 <h2 class="memtitle"><span class="permalink"><a href="#a48202cd0ad1df93721da27716f35ab99">◆ </a></span>GICDistributor_ITARGETSR_CPU6</h2>
3101 <div class="memitem">
3102 <div class="memproto">
3103 <table class="memname">
3105 <td class="memname">#define GICDistributor_ITARGETSR_CPU6</td>
3107 <td class="paramtype"> </td>
3108 <td class="paramname">x</td><td>)</td>
3109 <td>   (((uint8_t)(((uint8_t)(x)) << <a class="el" href="core__ca_8h.html#aab6a80042fd995785ff18e4f996716c2">GICDistributor_ITARGETSR_CPU6_Pos</a>)) & <a class="el" href="core__ca_8h.html#a0d9fa1b53101815feaebc4a5943e1d4c">GICDistributor_ITARGETSR_CPU6_Msk</a>)</td>
3112 </div><div class="memdoc">
3116 <a id="a0d9fa1b53101815feaebc4a5943e1d4c" name="a0d9fa1b53101815feaebc4a5943e1d4c"></a>
3117 <h2 class="memtitle"><span class="permalink"><a href="#a0d9fa1b53101815feaebc4a5943e1d4c">◆ </a></span>GICDistributor_ITARGETSR_CPU6_Msk</h2>
3119 <div class="memitem">
3120 <div class="memproto">
3121 <table class="memname">
3123 <td class="memname">#define GICDistributor_ITARGETSR_CPU6_Msk   (0x1U << <a class="el" href="core__ca_8h.html#aab6a80042fd995785ff18e4f996716c2">GICDistributor_ITARGETSR_CPU6_Pos</a>)</td>
3126 </div><div class="memdoc">
3127 <p>GICDistributor ITARGETSR: CPU6 Mask </p>
3131 <a id="aab6a80042fd995785ff18e4f996716c2" name="aab6a80042fd995785ff18e4f996716c2"></a>
3132 <h2 class="memtitle"><span class="permalink"><a href="#aab6a80042fd995785ff18e4f996716c2">◆ </a></span>GICDistributor_ITARGETSR_CPU6_Pos</h2>
3134 <div class="memitem">
3135 <div class="memproto">
3136 <table class="memname">
3138 <td class="memname">#define GICDistributor_ITARGETSR_CPU6_Pos   6U</td>
3141 </div><div class="memdoc">
3142 <p>GICDistributor ITARGETSR: CPU6 Position </p>
3146 <a id="aa1026673480067f6c33069bf555bee9a" name="aa1026673480067f6c33069bf555bee9a"></a>
3147 <h2 class="memtitle"><span class="permalink"><a href="#aa1026673480067f6c33069bf555bee9a">◆ </a></span>GICDistributor_ITARGETSR_CPU7</h2>
3149 <div class="memitem">
3150 <div class="memproto">
3151 <table class="memname">
3153 <td class="memname">#define GICDistributor_ITARGETSR_CPU7</td>
3155 <td class="paramtype"> </td>
3156 <td class="paramname">x</td><td>)</td>
3157 <td>   (((uint8_t)(((uint8_t)(x)) << <a class="el" href="core__ca_8h.html#ab8de7f026a09862a180421168128db75">GICDistributor_ITARGETSR_CPU7_Pos</a>)) & <a class="el" href="core__ca_8h.html#aefbae4dd8686f09a13ac74db57d27a6f">GICDistributor_ITARGETSR_CPU7_Msk</a>)</td>
3160 </div><div class="memdoc">
3164 <a id="aefbae4dd8686f09a13ac74db57d27a6f" name="aefbae4dd8686f09a13ac74db57d27a6f"></a>
3165 <h2 class="memtitle"><span class="permalink"><a href="#aefbae4dd8686f09a13ac74db57d27a6f">◆ </a></span>GICDistributor_ITARGETSR_CPU7_Msk</h2>
3167 <div class="memitem">
3168 <div class="memproto">
3169 <table class="memname">
3171 <td class="memname">#define GICDistributor_ITARGETSR_CPU7_Msk   (0x1U << <a class="el" href="core__ca_8h.html#ab8de7f026a09862a180421168128db75">GICDistributor_ITARGETSR_CPU7_Pos</a>)</td>
3174 </div><div class="memdoc">
3175 <p>GICDistributor ITARGETSR: CPU7 Mask </p>
3179 <a id="ab8de7f026a09862a180421168128db75" name="ab8de7f026a09862a180421168128db75"></a>
3180 <h2 class="memtitle"><span class="permalink"><a href="#ab8de7f026a09862a180421168128db75">◆ </a></span>GICDistributor_ITARGETSR_CPU7_Pos</h2>
3182 <div class="memitem">
3183 <div class="memproto">
3184 <table class="memname">
3186 <td class="memname">#define GICDistributor_ITARGETSR_CPU7_Pos   7U</td>
3189 </div><div class="memdoc">
3190 <p>GICDistributor ITARGETSR: CPU7 Position </p>
3194 <a id="ad32219138870f7dd63a0bc211f7fcc58" name="ad32219138870f7dd63a0bc211f7fcc58"></a>
3195 <h2 class="memtitle"><span class="permalink"><a href="#ad32219138870f7dd63a0bc211f7fcc58">◆ </a></span>GICDistributor_SETSPI_NSR_INTID</h2>
3197 <div class="memitem">
3198 <div class="memproto">
3199 <table class="memname">
3201 <td class="memname">#define GICDistributor_SETSPI_NSR_INTID</td>
3203 <td class="paramtype"> </td>
3204 <td class="paramname">x</td><td>)</td>
3205 <td>   (((uint32_t)(((uint32_t)(x)) /*<< <a class="el" href="core__ca_8h.html#aa934ee036ef12831d8af1045d89d5098">GICDistributor_SETSPI_NSR_INTID_Pos</a>*/)) & <a class="el" href="core__ca_8h.html#ab953cf9ca1e33ad5711f00bac17a70e2">GICDistributor_SETSPI_NSR_INTID_Msk</a>)</td>
3208 </div><div class="memdoc">
3212 <a id="ab953cf9ca1e33ad5711f00bac17a70e2" name="ab953cf9ca1e33ad5711f00bac17a70e2"></a>
3213 <h2 class="memtitle"><span class="permalink"><a href="#ab953cf9ca1e33ad5711f00bac17a70e2">◆ </a></span>GICDistributor_SETSPI_NSR_INTID_Msk</h2>
3215 <div class="memitem">
3216 <div class="memproto">
3217 <table class="memname">
3219 <td class="memname">#define GICDistributor_SETSPI_NSR_INTID_Msk   (0x3FFU /*<< <a class="el" href="core__ca_8h.html#aa934ee036ef12831d8af1045d89d5098">GICDistributor_SETSPI_NSR_INTID_Pos</a>*/)</td>
3222 </div><div class="memdoc">
3223 <p>GICDistributor SETSPI_NSR: INTID Mask </p>
3227 <a id="aa934ee036ef12831d8af1045d89d5098" name="aa934ee036ef12831d8af1045d89d5098"></a>
3228 <h2 class="memtitle"><span class="permalink"><a href="#aa934ee036ef12831d8af1045d89d5098">◆ </a></span>GICDistributor_SETSPI_NSR_INTID_Pos</h2>
3230 <div class="memitem">
3231 <div class="memproto">
3232 <table class="memname">
3234 <td class="memname">#define GICDistributor_SETSPI_NSR_INTID_Pos   0U</td>
3237 </div><div class="memdoc">
3238 <p>GICDistributor SETSPI_NSR: INTID Position </p>
3242 <a id="aa54f4703869cef1a5cba0b0e0c45d120" name="aa54f4703869cef1a5cba0b0e0c45d120"></a>
3243 <h2 class="memtitle"><span class="permalink"><a href="#aa54f4703869cef1a5cba0b0e0c45d120">◆ </a></span>GICDistributor_SETSPI_SR_INTID</h2>
3245 <div class="memitem">
3246 <div class="memproto">
3247 <table class="memname">
3249 <td class="memname">#define GICDistributor_SETSPI_SR_INTID</td>
3251 <td class="paramtype"> </td>
3252 <td class="paramname">x</td><td>)</td>
3253 <td>   (((uint32_t)(((uint32_t)(x)) /*<< <a class="el" href="core__ca_8h.html#ae77f1bf2954b62ee958857a8da665c08">GICDistributor_SETSPI_SR_INTID_Pos</a>*/)) & <a class="el" href="core__ca_8h.html#aa6d470044e50683356814e998a886c50">GICDistributor_SETSPI_SR_INTID_Msk</a>)</td>
3256 </div><div class="memdoc">
3260 <a id="aa6d470044e50683356814e998a886c50" name="aa6d470044e50683356814e998a886c50"></a>
3261 <h2 class="memtitle"><span class="permalink"><a href="#aa6d470044e50683356814e998a886c50">◆ </a></span>GICDistributor_SETSPI_SR_INTID_Msk</h2>
3263 <div class="memitem">
3264 <div class="memproto">
3265 <table class="memname">
3267 <td class="memname">#define GICDistributor_SETSPI_SR_INTID_Msk   (0x3FFU /*<< <a class="el" href="core__ca_8h.html#ae77f1bf2954b62ee958857a8da665c08">GICDistributor_SETSPI_SR_INTID_Pos</a>*/)</td>
3270 </div><div class="memdoc">
3271 <p>GICDistributor SETSPI_SR: INTID Mask </p>
3275 <a id="ae77f1bf2954b62ee958857a8da665c08" name="ae77f1bf2954b62ee958857a8da665c08"></a>
3276 <h2 class="memtitle"><span class="permalink"><a href="#ae77f1bf2954b62ee958857a8da665c08">◆ </a></span>GICDistributor_SETSPI_SR_INTID_Pos</h2>
3278 <div class="memitem">
3279 <div class="memproto">
3280 <table class="memname">
3282 <td class="memname">#define GICDistributor_SETSPI_SR_INTID_Pos   0U</td>
3285 </div><div class="memdoc">
3286 <p>GICDistributor SETSPI_SR: INTID Position </p>
3290 <a id="a96fab5404da27e765c6e7c917674f5ae" name="a96fab5404da27e765c6e7c917674f5ae"></a>
3291 <h2 class="memtitle"><span class="permalink"><a href="#a96fab5404da27e765c6e7c917674f5ae">◆ </a></span>GICDistributor_SGIR_CPUTargetList</h2>
3293 <div class="memitem">
3294 <div class="memproto">
3295 <table class="memname">
3297 <td class="memname">#define GICDistributor_SGIR_CPUTargetList</td>
3299 <td class="paramtype"> </td>
3300 <td class="paramname">x</td><td>)</td>
3301 <td>   (((uint32_t)(((uint32_t)(x)) << <a class="el" href="core__ca_8h.html#a981be1c459eaa484ad6f46de18e959c8">GICDistributor_SGIR_CPUTargetList_Pos</a>)) & <a class="el" href="core__ca_8h.html#a4b5c793fb6ace02cabc6afe09dce6af7">GICDistributor_SGIR_CPUTargetList_Msk</a>)</td>
3304 </div><div class="memdoc">
3308 <a id="a4b5c793fb6ace02cabc6afe09dce6af7" name="a4b5c793fb6ace02cabc6afe09dce6af7"></a>
3309 <h2 class="memtitle"><span class="permalink"><a href="#a4b5c793fb6ace02cabc6afe09dce6af7">◆ </a></span>GICDistributor_SGIR_CPUTargetList_Msk</h2>
3311 <div class="memitem">
3312 <div class="memproto">
3313 <table class="memname">
3315 <td class="memname">#define GICDistributor_SGIR_CPUTargetList_Msk   (0xFFU << <a class="el" href="core__ca_8h.html#a981be1c459eaa484ad6f46de18e959c8">GICDistributor_SGIR_CPUTargetList_Pos</a>)</td>
3318 </div><div class="memdoc">
3319 <p>GICDistributor SGIR: CPUTargetList Mask </p>
3323 <a id="a981be1c459eaa484ad6f46de18e959c8" name="a981be1c459eaa484ad6f46de18e959c8"></a>
3324 <h2 class="memtitle"><span class="permalink"><a href="#a981be1c459eaa484ad6f46de18e959c8">◆ </a></span>GICDistributor_SGIR_CPUTargetList_Pos</h2>
3326 <div class="memitem">
3327 <div class="memproto">
3328 <table class="memname">
3330 <td class="memname">#define GICDistributor_SGIR_CPUTargetList_Pos   16U</td>
3333 </div><div class="memdoc">
3334 <p>GICDistributor SGIR: CPUTargetList Position </p>
3338 <a id="aa45326a8811c425d0ea6bedd1936444c" name="aa45326a8811c425d0ea6bedd1936444c"></a>
3339 <h2 class="memtitle"><span class="permalink"><a href="#aa45326a8811c425d0ea6bedd1936444c">◆ </a></span>GICDistributor_SGIR_INTID</h2>
3341 <div class="memitem">
3342 <div class="memproto">
3343 <table class="memname">
3345 <td class="memname">#define GICDistributor_SGIR_INTID</td>
3347 <td class="paramtype"> </td>
3348 <td class="paramname">x</td><td>)</td>
3349 <td>   (((uint32_t)(((uint32_t)(x)) /*<< <a class="el" href="core__ca_8h.html#ae1dd9d68a6bf8a6c9025ae7279fedae6">GICDistributor_SGIR_INTID_Pos</a>*/)) & <a class="el" href="core__ca_8h.html#aeb93cabf664375c4213402cbc85d2c44">GICDistributor_SGIR_INTID_Msk</a>)</td>
3352 </div><div class="memdoc">
3356 <a id="aeb93cabf664375c4213402cbc85d2c44" name="aeb93cabf664375c4213402cbc85d2c44"></a>
3357 <h2 class="memtitle"><span class="permalink"><a href="#aeb93cabf664375c4213402cbc85d2c44">◆ </a></span>GICDistributor_SGIR_INTID_Msk</h2>
3359 <div class="memitem">
3360 <div class="memproto">
3361 <table class="memname">
3363 <td class="memname">#define GICDistributor_SGIR_INTID_Msk   (0x7U /*<< <a class="el" href="core__ca_8h.html#ae1dd9d68a6bf8a6c9025ae7279fedae6">GICDistributor_SGIR_INTID_Pos</a>*/)</td>
3366 </div><div class="memdoc">
3367 <p>GICDistributor SGIR: INTID Mask </p>
3371 <a id="ae1dd9d68a6bf8a6c9025ae7279fedae6" name="ae1dd9d68a6bf8a6c9025ae7279fedae6"></a>
3372 <h2 class="memtitle"><span class="permalink"><a href="#ae1dd9d68a6bf8a6c9025ae7279fedae6">◆ </a></span>GICDistributor_SGIR_INTID_Pos</h2>
3374 <div class="memitem">
3375 <div class="memproto">
3376 <table class="memname">
3378 <td class="memname">#define GICDistributor_SGIR_INTID_Pos   0U</td>
3381 </div><div class="memdoc">
3382 <p>GICDistributor SGIR: INTID Position </p>
3386 <a id="ac2aff3b2b284d922e23a14dde8c91689" name="ac2aff3b2b284d922e23a14dde8c91689"></a>
3387 <h2 class="memtitle"><span class="permalink"><a href="#ac2aff3b2b284d922e23a14dde8c91689">◆ </a></span>GICDistributor_SGIR_NSATT</h2>
3389 <div class="memitem">
3390 <div class="memproto">
3391 <table class="memname">
3393 <td class="memname">#define GICDistributor_SGIR_NSATT</td>
3395 <td class="paramtype"> </td>
3396 <td class="paramname">x</td><td>)</td>
3397 <td>   (((uint32_t)(((uint32_t)(x)) << <a class="el" href="core__ca_8h.html#a24cd5de9c2639ea81ef62500a3cbe8ad">GICDistributor_SGIR_NSATT_Pos</a>)) & <a class="el" href="core__ca_8h.html#a99afa06bfe662185b91c004719979f4f">GICDistributor_SGIR_NSATT_Msk</a>)</td>
3400 </div><div class="memdoc">
3404 <a id="a99afa06bfe662185b91c004719979f4f" name="a99afa06bfe662185b91c004719979f4f"></a>
3405 <h2 class="memtitle"><span class="permalink"><a href="#a99afa06bfe662185b91c004719979f4f">◆ </a></span>GICDistributor_SGIR_NSATT_Msk</h2>
3407 <div class="memitem">
3408 <div class="memproto">
3409 <table class="memname">
3411 <td class="memname">#define GICDistributor_SGIR_NSATT_Msk   (0x1U << <a class="el" href="core__ca_8h.html#a24cd5de9c2639ea81ef62500a3cbe8ad">GICDistributor_SGIR_NSATT_Pos</a>)</td>
3414 </div><div class="memdoc">
3415 <p>GICDistributor SGIR: NSATT Mask </p>
3419 <a id="a24cd5de9c2639ea81ef62500a3cbe8ad" name="a24cd5de9c2639ea81ef62500a3cbe8ad"></a>
3420 <h2 class="memtitle"><span class="permalink"><a href="#a24cd5de9c2639ea81ef62500a3cbe8ad">◆ </a></span>GICDistributor_SGIR_NSATT_Pos</h2>
3422 <div class="memitem">
3423 <div class="memproto">
3424 <table class="memname">
3426 <td class="memname">#define GICDistributor_SGIR_NSATT_Pos   15U</td>
3429 </div><div class="memdoc">
3430 <p>GICDistributor SGIR: NSATT Position </p>
3434 <a id="a503b7a0ad26672fdb87577162624c920" name="a503b7a0ad26672fdb87577162624c920"></a>
3435 <h2 class="memtitle"><span class="permalink"><a href="#a503b7a0ad26672fdb87577162624c920">◆ </a></span>GICDistributor_SGIR_TargetFilterList</h2>
3437 <div class="memitem">
3438 <div class="memproto">
3439 <table class="memname">
3441 <td class="memname">#define GICDistributor_SGIR_TargetFilterList</td>
3443 <td class="paramtype"> </td>
3444 <td class="paramname">x</td><td>)</td>
3445 <td>   (((uint32_t)(((uint32_t)(x)) << <a class="el" href="core__ca_8h.html#ac6d41353e1f46a74d007f75049c3571c">GICDistributor_SGIR_TargetFilterList_Pos</a>)) & <a class="el" href="core__ca_8h.html#afef4f1a483835c535630dcd02c1640b4">GICDistributor_SGIR_TargetFilterList_Msk</a>)</td>
3448 </div><div class="memdoc">
3452 <a id="afef4f1a483835c535630dcd02c1640b4" name="afef4f1a483835c535630dcd02c1640b4"></a>
3453 <h2 class="memtitle"><span class="permalink"><a href="#afef4f1a483835c535630dcd02c1640b4">◆ </a></span>GICDistributor_SGIR_TargetFilterList_Msk</h2>
3455 <div class="memitem">
3456 <div class="memproto">
3457 <table class="memname">
3459 <td class="memname">#define GICDistributor_SGIR_TargetFilterList_Msk   (0x3U << <a class="el" href="core__ca_8h.html#ac6d41353e1f46a74d007f75049c3571c">GICDistributor_SGIR_TargetFilterList_Pos</a>)</td>
3462 </div><div class="memdoc">
3463 <p>GICDistributor SGIR: TargetFilterList Mask </p>
3467 <a id="ac6d41353e1f46a74d007f75049c3571c" name="ac6d41353e1f46a74d007f75049c3571c"></a>
3468 <h2 class="memtitle"><span class="permalink"><a href="#ac6d41353e1f46a74d007f75049c3571c">◆ </a></span>GICDistributor_SGIR_TargetFilterList_Pos</h2>
3470 <div class="memitem">
3471 <div class="memproto">
3472 <table class="memname">
3474 <td class="memname">#define GICDistributor_SGIR_TargetFilterList_Pos   24U</td>
3477 </div><div class="memdoc">
3478 <p>GICDistributor SGIR: TargetFilterList Position </p>
3482 <a id="a44b7dd5f0ba7bc48c66c2b09ec38f3b9" name="a44b7dd5f0ba7bc48c66c2b09ec38f3b9"></a>
3483 <h2 class="memtitle"><span class="permalink"><a href="#a44b7dd5f0ba7bc48c66c2b09ec38f3b9">◆ </a></span>GICDistributor_STATUSR_RRD</h2>
3485 <div class="memitem">
3486 <div class="memproto">
3487 <table class="memname">
3489 <td class="memname">#define GICDistributor_STATUSR_RRD</td>
3491 <td class="paramtype"> </td>
3492 <td class="paramname">x</td><td>)</td>
3493 <td>   (((uint32_t)(((uint32_t)(x)) /*<< <a class="el" href="core__ca_8h.html#a6b3d0d43717045928b96ce9c8e76493d">GICDistributor_STATUSR_RRD_Pos</a>*/)) & <a class="el" href="core__ca_8h.html#aa8bef863ded4eccc540df63bb9409b66">GICDistributor_STATUSR_RRD_Msk</a>)</td>
3496 </div><div class="memdoc">
3500 <a id="aa8bef863ded4eccc540df63bb9409b66" name="aa8bef863ded4eccc540df63bb9409b66"></a>
3501 <h2 class="memtitle"><span class="permalink"><a href="#aa8bef863ded4eccc540df63bb9409b66">◆ </a></span>GICDistributor_STATUSR_RRD_Msk</h2>
3503 <div class="memitem">
3504 <div class="memproto">
3505 <table class="memname">
3507 <td class="memname">#define GICDistributor_STATUSR_RRD_Msk   (0x1U /*<< <a class="el" href="core__ca_8h.html#a6b3d0d43717045928b96ce9c8e76493d">GICDistributor_STATUSR_RRD_Pos</a>*/)</td>
3510 </div><div class="memdoc">
3511 <p>GICDistributor STATUSR: RRD Mask </p>
3515 <a id="a6b3d0d43717045928b96ce9c8e76493d" name="a6b3d0d43717045928b96ce9c8e76493d"></a>
3516 <h2 class="memtitle"><span class="permalink"><a href="#a6b3d0d43717045928b96ce9c8e76493d">◆ </a></span>GICDistributor_STATUSR_RRD_Pos</h2>
3518 <div class="memitem">
3519 <div class="memproto">
3520 <table class="memname">
3522 <td class="memname">#define GICDistributor_STATUSR_RRD_Pos   0U</td>
3525 </div><div class="memdoc">
3526 <p>GICDistributor STATUSR: RRD Position </p>
3530 <a id="ad5e6e2461927af5b913ae150531cba55" name="ad5e6e2461927af5b913ae150531cba55"></a>
3531 <h2 class="memtitle"><span class="permalink"><a href="#ad5e6e2461927af5b913ae150531cba55">◆ </a></span>GICDistributor_STATUSR_RWOD</h2>
3533 <div class="memitem">
3534 <div class="memproto">
3535 <table class="memname">
3537 <td class="memname">#define GICDistributor_STATUSR_RWOD</td>
3539 <td class="paramtype"> </td>
3540 <td class="paramname">x</td><td>)</td>
3541 <td>   (((uint32_t)(((uint32_t)(x)) << <a class="el" href="core__ca_8h.html#a770b3e754d28bfe33264925f982601d3">GICDistributor_STATUSR_RWOD_Pos</a>)) & <a class="el" href="core__ca_8h.html#aa118bf40ce6c4afcfe0d7f5d1962e3d9">GICDistributor_STATUSR_RWOD_Msk</a>)</td>
3544 </div><div class="memdoc">
3548 <a id="aa118bf40ce6c4afcfe0d7f5d1962e3d9" name="aa118bf40ce6c4afcfe0d7f5d1962e3d9"></a>
3549 <h2 class="memtitle"><span class="permalink"><a href="#aa118bf40ce6c4afcfe0d7f5d1962e3d9">◆ </a></span>GICDistributor_STATUSR_RWOD_Msk</h2>
3551 <div class="memitem">
3552 <div class="memproto">
3553 <table class="memname">
3555 <td class="memname">#define GICDistributor_STATUSR_RWOD_Msk   (0x1U << <a class="el" href="core__ca_8h.html#a770b3e754d28bfe33264925f982601d3">GICDistributor_STATUSR_RWOD_Pos</a>)</td>
3558 </div><div class="memdoc">
3559 <p>GICDistributor STATUSR: RWOD Mask </p>
3563 <a id="a770b3e754d28bfe33264925f982601d3" name="a770b3e754d28bfe33264925f982601d3"></a>
3564 <h2 class="memtitle"><span class="permalink"><a href="#a770b3e754d28bfe33264925f982601d3">◆ </a></span>GICDistributor_STATUSR_RWOD_Pos</h2>
3566 <div class="memitem">
3567 <div class="memproto">
3568 <table class="memname">
3570 <td class="memname">#define GICDistributor_STATUSR_RWOD_Pos   2U</td>
3573 </div><div class="memdoc">
3574 <p>GICDistributor STATUSR: RWOD Position </p>
3578 <a id="a97af8de41d50552933bde33d37b45501" name="a97af8de41d50552933bde33d37b45501"></a>
3579 <h2 class="memtitle"><span class="permalink"><a href="#a97af8de41d50552933bde33d37b45501">◆ </a></span>GICDistributor_STATUSR_WRD</h2>
3581 <div class="memitem">
3582 <div class="memproto">
3583 <table class="memname">
3585 <td class="memname">#define GICDistributor_STATUSR_WRD</td>
3587 <td class="paramtype"> </td>
3588 <td class="paramname">x</td><td>)</td>
3589 <td>   (((uint32_t)(((uint32_t)(x)) << <a class="el" href="core__ca_8h.html#a445ce8828d51d1e51fd2ee7220d80ef7">GICDistributor_STATUSR_WRD_Pos</a>)) & <a class="el" href="core__ca_8h.html#a4918f67f256f60199aab4aea51641ff4">GICDistributor_STATUSR_WRD_Msk</a>)</td>
3592 </div><div class="memdoc">
3596 <a id="a4918f67f256f60199aab4aea51641ff4" name="a4918f67f256f60199aab4aea51641ff4"></a>
3597 <h2 class="memtitle"><span class="permalink"><a href="#a4918f67f256f60199aab4aea51641ff4">◆ </a></span>GICDistributor_STATUSR_WRD_Msk</h2>
3599 <div class="memitem">
3600 <div class="memproto">
3601 <table class="memname">
3603 <td class="memname">#define GICDistributor_STATUSR_WRD_Msk   (0x1U << <a class="el" href="core__ca_8h.html#a445ce8828d51d1e51fd2ee7220d80ef7">GICDistributor_STATUSR_WRD_Pos</a>)</td>
3606 </div><div class="memdoc">
3607 <p>GICDistributor STATUSR: WRD Mask </p>
3611 <a id="a445ce8828d51d1e51fd2ee7220d80ef7" name="a445ce8828d51d1e51fd2ee7220d80ef7"></a>
3612 <h2 class="memtitle"><span class="permalink"><a href="#a445ce8828d51d1e51fd2ee7220d80ef7">◆ </a></span>GICDistributor_STATUSR_WRD_Pos</h2>
3614 <div class="memitem">
3615 <div class="memproto">
3616 <table class="memname">
3618 <td class="memname">#define GICDistributor_STATUSR_WRD_Pos   1U</td>
3621 </div><div class="memdoc">
3622 <p>GICDistributor STATUSR: WRD Position </p>
3626 <a id="a83dfa2f07a25812301dceeac8632257e" name="a83dfa2f07a25812301dceeac8632257e"></a>
3627 <h2 class="memtitle"><span class="permalink"><a href="#a83dfa2f07a25812301dceeac8632257e">◆ </a></span>GICDistributor_STATUSR_WROD</h2>
3629 <div class="memitem">
3630 <div class="memproto">
3631 <table class="memname">
3633 <td class="memname">#define GICDistributor_STATUSR_WROD</td>
3635 <td class="paramtype"> </td>
3636 <td class="paramname">x</td><td>)</td>
3637 <td>   (((uint32_t)(((uint32_t)(x)) << <a class="el" href="core__ca_8h.html#aa10fb1346557f4a47cba190a8e1e5276">GICDistributor_STATUSR_WROD_Pos</a>)) & <a class="el" href="core__ca_8h.html#a3ebeda889d892922823097d05234498b">GICDistributor_STATUSR_WROD_Msk</a>)</td>
3640 </div><div class="memdoc">
3644 <a id="a3ebeda889d892922823097d05234498b" name="a3ebeda889d892922823097d05234498b"></a>
3645 <h2 class="memtitle"><span class="permalink"><a href="#a3ebeda889d892922823097d05234498b">◆ </a></span>GICDistributor_STATUSR_WROD_Msk</h2>
3647 <div class="memitem">
3648 <div class="memproto">
3649 <table class="memname">
3651 <td class="memname">#define GICDistributor_STATUSR_WROD_Msk   (0x1U << <a class="el" href="core__ca_8h.html#aa10fb1346557f4a47cba190a8e1e5276">GICDistributor_STATUSR_WROD_Pos</a>)</td>
3654 </div><div class="memdoc">
3655 <p>GICDistributor STATUSR: WROD Mask </p>
3659 <a id="aa10fb1346557f4a47cba190a8e1e5276" name="aa10fb1346557f4a47cba190a8e1e5276"></a>
3660 <h2 class="memtitle"><span class="permalink"><a href="#aa10fb1346557f4a47cba190a8e1e5276">◆ </a></span>GICDistributor_STATUSR_WROD_Pos</h2>
3662 <div class="memitem">
3663 <div class="memproto">
3664 <table class="memname">
3666 <td class="memname">#define GICDistributor_STATUSR_WROD_Pos   3U</td>
3669 </div><div class="memdoc">
3670 <p>GICDistributor STATUSR: WROD Position </p>
3674 <a id="a9f26592b70ad969b7ced5cc787d07cdb" name="a9f26592b70ad969b7ced5cc787d07cdb"></a>
3675 <h2 class="memtitle"><span class="permalink"><a href="#a9f26592b70ad969b7ced5cc787d07cdb">◆ </a></span>GICDistributor_TYPER_CPUNumber</h2>
3677 <div class="memitem">
3678 <div class="memproto">
3679 <table class="memname">
3681 <td class="memname">#define GICDistributor_TYPER_CPUNumber</td>
3683 <td class="paramtype"> </td>
3684 <td class="paramname">x</td><td>)</td>
3685 <td>   (((uint32_t)(((uint32_t)(x)) << <a class="el" href="core__ca_8h.html#a75ed96a2761b78a89e74d324d5584142">GICDistributor_TYPER_CPUNumber_Pos</a>)) & <a class="el" href="core__ca_8h.html#a7a299859f30b505dcfe18390acca30ba">GICDistributor_TYPER_CPUNumber_Msk</a>)</td>
3688 </div><div class="memdoc">
3692 <a id="a7a299859f30b505dcfe18390acca30ba" name="a7a299859f30b505dcfe18390acca30ba"></a>
3693 <h2 class="memtitle"><span class="permalink"><a href="#a7a299859f30b505dcfe18390acca30ba">◆ </a></span>GICDistributor_TYPER_CPUNumber_Msk</h2>
3695 <div class="memitem">
3696 <div class="memproto">
3697 <table class="memname">
3699 <td class="memname">#define GICDistributor_TYPER_CPUNumber_Msk   (0x7U << <a class="el" href="core__ca_8h.html#a75ed96a2761b78a89e74d324d5584142">GICDistributor_TYPER_CPUNumber_Pos</a>)</td>
3702 </div><div class="memdoc">
3703 <p>GICDistributor TYPER: CPUNumber Mask </p>
3707 <a id="a75ed96a2761b78a89e74d324d5584142" name="a75ed96a2761b78a89e74d324d5584142"></a>
3708 <h2 class="memtitle"><span class="permalink"><a href="#a75ed96a2761b78a89e74d324d5584142">◆ </a></span>GICDistributor_TYPER_CPUNumber_Pos</h2>
3710 <div class="memitem">
3711 <div class="memproto">
3712 <table class="memname">
3714 <td class="memname">#define GICDistributor_TYPER_CPUNumber_Pos   5U</td>
3717 </div><div class="memdoc">
3718 <p>GICDistributor TYPER: CPUNumber Position </p>
3722 <a id="a54970661ead25e94edb829e2e369a665" name="a54970661ead25e94edb829e2e369a665"></a>
3723 <h2 class="memtitle"><span class="permalink"><a href="#a54970661ead25e94edb829e2e369a665">◆ </a></span>GICDistributor_TYPER_ITLinesNumber</h2>
3725 <div class="memitem">
3726 <div class="memproto">
3727 <table class="memname">
3729 <td class="memname">#define GICDistributor_TYPER_ITLinesNumber</td>
3731 <td class="paramtype"> </td>
3732 <td class="paramname">x</td><td>)</td>
3733 <td>   (((uint32_t)(((uint32_t)(x)) /*<< <a class="el" href="core__ca_8h.html#afca2b1421a2f881e45cc8925dc22a9bf">GICDistributor_TYPER_ITLinesNumber_Pos</a>*/)) & GICDistributor_CTLR_ITLinesNumber_Msk)</td>
3736 </div><div class="memdoc">
3740 <a id="ad1298a5af707fdc4a9aa5ae7a311f326" name="ad1298a5af707fdc4a9aa5ae7a311f326"></a>
3741 <h2 class="memtitle"><span class="permalink"><a href="#ad1298a5af707fdc4a9aa5ae7a311f326">◆ </a></span>GICDistributor_TYPER_ITLinesNumber_Msk</h2>
3743 <div class="memitem">
3744 <div class="memproto">
3745 <table class="memname">
3747 <td class="memname">#define GICDistributor_TYPER_ITLinesNumber_Msk   (0x1FU /*<< <a class="el" href="core__ca_8h.html#afca2b1421a2f881e45cc8925dc22a9bf">GICDistributor_TYPER_ITLinesNumber_Pos</a>*/)</td>
3750 </div><div class="memdoc">
3751 <p>GICDistributor TYPER: ITLinesNumber Mask </p>
3755 <a id="afca2b1421a2f881e45cc8925dc22a9bf" name="afca2b1421a2f881e45cc8925dc22a9bf"></a>
3756 <h2 class="memtitle"><span class="permalink"><a href="#afca2b1421a2f881e45cc8925dc22a9bf">◆ </a></span>GICDistributor_TYPER_ITLinesNumber_Pos</h2>
3758 <div class="memitem">
3759 <div class="memproto">
3760 <table class="memname">
3762 <td class="memname">#define GICDistributor_TYPER_ITLinesNumber_Pos   0U</td>
3765 </div><div class="memdoc">
3766 <p>GICDistributor TYPER: ITLinesNumber Position </p>
3770 <a id="a0a58d0f567826aa548949f17474686c0" name="a0a58d0f567826aa548949f17474686c0"></a>
3771 <h2 class="memtitle"><span class="permalink"><a href="#a0a58d0f567826aa548949f17474686c0">◆ </a></span>GICDistributor_TYPER_LSPI</h2>
3773 <div class="memitem">
3774 <div class="memproto">
3775 <table class="memname">
3777 <td class="memname">#define GICDistributor_TYPER_LSPI</td>
3779 <td class="paramtype"> </td>
3780 <td class="paramname">x</td><td>)</td>
3781 <td>   (((uint32_t)(((uint32_t)(x)) << <a class="el" href="core__ca_8h.html#a6aa6a3afd05d1e914eca81a0f633c282">GICDistributor_TYPER_LSPI_Pos</a>)) & <a class="el" href="core__ca_8h.html#a4a869c9815cef6b3d9d96517d00b0f6d">GICDistributor_TYPER_LSPI_Msk</a>)</td>
3784 </div><div class="memdoc">
3788 <a id="a4a869c9815cef6b3d9d96517d00b0f6d" name="a4a869c9815cef6b3d9d96517d00b0f6d"></a>
3789 <h2 class="memtitle"><span class="permalink"><a href="#a4a869c9815cef6b3d9d96517d00b0f6d">◆ </a></span>GICDistributor_TYPER_LSPI_Msk</h2>
3791 <div class="memitem">
3792 <div class="memproto">
3793 <table class="memname">
3795 <td class="memname">#define GICDistributor_TYPER_LSPI_Msk   (0x1FU << <a class="el" href="core__ca_8h.html#a6aa6a3afd05d1e914eca81a0f633c282">GICDistributor_TYPER_LSPI_Pos</a>)</td>
3798 </div><div class="memdoc">
3799 <p>GICDistributor TYPER: LSPI Mask </p>
3803 <a id="a6aa6a3afd05d1e914eca81a0f633c282" name="a6aa6a3afd05d1e914eca81a0f633c282"></a>
3804 <h2 class="memtitle"><span class="permalink"><a href="#a6aa6a3afd05d1e914eca81a0f633c282">◆ </a></span>GICDistributor_TYPER_LSPI_Pos</h2>
3806 <div class="memitem">
3807 <div class="memproto">
3808 <table class="memname">
3810 <td class="memname">#define GICDistributor_TYPER_LSPI_Pos   11U</td>
3813 </div><div class="memdoc">
3814 <p>GICDistributor TYPER: LSPI Position </p>
3818 <a id="a0be7c527f9d5caa531c0f14363bf0c95" name="a0be7c527f9d5caa531c0f14363bf0c95"></a>
3819 <h2 class="memtitle"><span class="permalink"><a href="#a0be7c527f9d5caa531c0f14363bf0c95">◆ </a></span>GICDistributor_TYPER_SecurityExtn</h2>
3821 <div class="memitem">
3822 <div class="memproto">
3823 <table class="memname">
3825 <td class="memname">#define GICDistributor_TYPER_SecurityExtn</td>
3827 <td class="paramtype"> </td>
3828 <td class="paramname">x</td><td>)</td>
3829 <td>   (((uint32_t)(((uint32_t)(x)) << <a class="el" href="core__ca_8h.html#a23ead3c0a646bec5a3ef37a746bc636b">GICDistributor_TYPER_SecurityExtn_Pos</a>)) & <a class="el" href="core__ca_8h.html#ae79bcab413026c129df5b1d256439137">GICDistributor_TYPER_SecurityExtn_Msk</a>)</td>
3832 </div><div class="memdoc">
3836 <a id="ae79bcab413026c129df5b1d256439137" name="ae79bcab413026c129df5b1d256439137"></a>
3837 <h2 class="memtitle"><span class="permalink"><a href="#ae79bcab413026c129df5b1d256439137">◆ </a></span>GICDistributor_TYPER_SecurityExtn_Msk</h2>
3839 <div class="memitem">
3840 <div class="memproto">
3841 <table class="memname">
3843 <td class="memname">#define GICDistributor_TYPER_SecurityExtn_Msk   (0x1U << <a class="el" href="core__ca_8h.html#a23ead3c0a646bec5a3ef37a746bc636b">GICDistributor_TYPER_SecurityExtn_Pos</a>)</td>
3846 </div><div class="memdoc">
3847 <p>GICDistributor TYPER: SecurityExtn Mask </p>
3851 <a id="a23ead3c0a646bec5a3ef37a746bc636b" name="a23ead3c0a646bec5a3ef37a746bc636b"></a>
3852 <h2 class="memtitle"><span class="permalink"><a href="#a23ead3c0a646bec5a3ef37a746bc636b">◆ </a></span>GICDistributor_TYPER_SecurityExtn_Pos</h2>
3854 <div class="memitem">
3855 <div class="memproto">
3856 <table class="memname">
3858 <td class="memname">#define GICDistributor_TYPER_SecurityExtn_Pos   10U</td>
3861 </div><div class="memdoc">
3862 <p>GICDistributor TYPER: SecurityExtn Position </p>
3866 <a id="a1134babb25c7f194a2381206afc550e6" name="a1134babb25c7f194a2381206afc550e6"></a>
3867 <h2 class="memtitle"><span class="permalink"><a href="#a1134babb25c7f194a2381206afc550e6">◆ </a></span>GICInterface_ABPR_Binary_Point</h2>
3869 <div class="memitem">
3870 <div class="memproto">
3871 <table class="memname">
3873 <td class="memname">#define GICInterface_ABPR_Binary_Point</td>
3875 <td class="paramtype"> </td>
3876 <td class="paramname">x</td><td>)</td>
3877 <td>   (((uint32_t)(((uint32_t)(x)) /*<< <a class="el" href="core__ca_8h.html#a807965f59441878b51ff6d29b6354b68">GICInterface_ABPR_Binary_Point_Pos</a>*/)) & <a class="el" href="core__ca_8h.html#a5af342deca8701354f1bf9eccd08f28f">GICInterface_ABPR_Binary_Point_Msk</a>)</td>
3880 </div><div class="memdoc">
3884 <a id="a5af342deca8701354f1bf9eccd08f28f" name="a5af342deca8701354f1bf9eccd08f28f"></a>
3885 <h2 class="memtitle"><span class="permalink"><a href="#a5af342deca8701354f1bf9eccd08f28f">◆ </a></span>GICInterface_ABPR_Binary_Point_Msk</h2>
3887 <div class="memitem">
3888 <div class="memproto">
3889 <table class="memname">
3891 <td class="memname">#define GICInterface_ABPR_Binary_Point_Msk   (0x7U /*<< <a class="el" href="core__ca_8h.html#a807965f59441878b51ff6d29b6354b68">GICInterface_ABPR_Binary_Point_Pos</a>*/)</td>
3894 </div><div class="memdoc">
3895 <p>PTIM ABPR: Binary_Point Mask </p>
3899 <a id="a807965f59441878b51ff6d29b6354b68" name="a807965f59441878b51ff6d29b6354b68"></a>
3900 <h2 class="memtitle"><span class="permalink"><a href="#a807965f59441878b51ff6d29b6354b68">◆ </a></span>GICInterface_ABPR_Binary_Point_Pos</h2>
3902 <div class="memitem">
3903 <div class="memproto">
3904 <table class="memname">
3906 <td class="memname">#define GICInterface_ABPR_Binary_Point_Pos   0U</td>
3909 </div><div class="memdoc">
3910 <p>PTIM ABPR: Binary_Point Position </p>
3914 <a id="a04f1bd42fd08721ec7a327936298d80c" name="a04f1bd42fd08721ec7a327936298d80c"></a>
3915 <h2 class="memtitle"><span class="permalink"><a href="#a04f1bd42fd08721ec7a327936298d80c">◆ </a></span>GICInterface_AEOIR_INTID</h2>
3917 <div class="memitem">
3918 <div class="memproto">
3919 <table class="memname">
3921 <td class="memname">#define GICInterface_AEOIR_INTID</td>
3923 <td class="paramtype"> </td>
3924 <td class="paramname">x</td><td>)</td>
3925 <td>   (((uint32_t)(((uint32_t)(x)) /*<< <a class="el" href="core__ca_8h.html#acb9124edf6d65fbf428b913c9e4fd892">GICInterface_AEOIR_INTID_Pos</a>*/)) & <a class="el" href="core__ca_8h.html#a41906ea8e42bcc5b7925863a0c01379b">GICInterface_AEOIR_INTID_Msk</a>)</td>
3928 </div><div class="memdoc">
3932 <a id="a41906ea8e42bcc5b7925863a0c01379b" name="a41906ea8e42bcc5b7925863a0c01379b"></a>
3933 <h2 class="memtitle"><span class="permalink"><a href="#a41906ea8e42bcc5b7925863a0c01379b">◆ </a></span>GICInterface_AEOIR_INTID_Msk</h2>
3935 <div class="memitem">
3936 <div class="memproto">
3937 <table class="memname">
3939 <td class="memname">#define GICInterface_AEOIR_INTID_Msk   (0xFFFFFFU /*<< <a class="el" href="core__ca_8h.html#acb9124edf6d65fbf428b913c9e4fd892">GICInterface_AEOIR_INTID_Pos</a>*/)</td>
3942 </div><div class="memdoc">
3943 <p>PTIM AEOIR: INTID Mask </p>
3947 <a id="acb9124edf6d65fbf428b913c9e4fd892" name="acb9124edf6d65fbf428b913c9e4fd892"></a>
3948 <h2 class="memtitle"><span class="permalink"><a href="#acb9124edf6d65fbf428b913c9e4fd892">◆ </a></span>GICInterface_AEOIR_INTID_Pos</h2>
3950 <div class="memitem">
3951 <div class="memproto">
3952 <table class="memname">
3954 <td class="memname">#define GICInterface_AEOIR_INTID_Pos   0U</td>
3957 </div><div class="memdoc">
3958 <p>PTIM AEOIR: INTID Position </p>
3962 <a id="abf052e1e08eb339e1bb04f624d0c40d4" name="abf052e1e08eb339e1bb04f624d0c40d4"></a>
3963 <h2 class="memtitle"><span class="permalink"><a href="#abf052e1e08eb339e1bb04f624d0c40d4">◆ </a></span>GICInterface_AHPPIR_INTID</h2>
3965 <div class="memitem">
3966 <div class="memproto">
3967 <table class="memname">
3969 <td class="memname">#define GICInterface_AHPPIR_INTID</td>
3971 <td class="paramtype"> </td>
3972 <td class="paramname">x</td><td>)</td>
3973 <td>   (((uint32_t)(((uint32_t)(x)) /*<< <a class="el" href="core__ca_8h.html#a09b44c6effd3209e5d87251d8bcb4e71">GICInterface_AHPPIR_INTID_Pos</a>*/)) & <a class="el" href="core__ca_8h.html#a7edb7a7eef0400b3fb96adc814c93621">GICInterface_AHPPIR_INTID_Msk</a>)</td>
3976 </div><div class="memdoc">
3980 <a id="a7edb7a7eef0400b3fb96adc814c93621" name="a7edb7a7eef0400b3fb96adc814c93621"></a>
3981 <h2 class="memtitle"><span class="permalink"><a href="#a7edb7a7eef0400b3fb96adc814c93621">◆ </a></span>GICInterface_AHPPIR_INTID_Msk</h2>
3983 <div class="memitem">
3984 <div class="memproto">
3985 <table class="memname">
3987 <td class="memname">#define GICInterface_AHPPIR_INTID_Msk   (0xFFFFFFU /*<< <a class="el" href="core__ca_8h.html#a09b44c6effd3209e5d87251d8bcb4e71">GICInterface_AHPPIR_INTID_Pos</a>*/)</td>
3990 </div><div class="memdoc">
3991 <p>PTIM AHPPIR: INTID Mask </p>
3995 <a id="a09b44c6effd3209e5d87251d8bcb4e71" name="a09b44c6effd3209e5d87251d8bcb4e71"></a>
3996 <h2 class="memtitle"><span class="permalink"><a href="#a09b44c6effd3209e5d87251d8bcb4e71">◆ </a></span>GICInterface_AHPPIR_INTID_Pos</h2>
3998 <div class="memitem">
3999 <div class="memproto">
4000 <table class="memname">
4002 <td class="memname">#define GICInterface_AHPPIR_INTID_Pos   0U</td>
4005 </div><div class="memdoc">
4006 <p>PTIM AHPPIR: INTID Position </p>
4010 <a id="aa808951562f71c5094c5283ae88a8f9b" name="aa808951562f71c5094c5283ae88a8f9b"></a>
4011 <h2 class="memtitle"><span class="permalink"><a href="#aa808951562f71c5094c5283ae88a8f9b">◆ </a></span>GICInterface_AIAR_INTID</h2>
4013 <div class="memitem">
4014 <div class="memproto">
4015 <table class="memname">
4017 <td class="memname">#define GICInterface_AIAR_INTID</td>
4019 <td class="paramtype"> </td>
4020 <td class="paramname">x</td><td>)</td>
4021 <td>   (((uint32_t)(((uint32_t)(x)) /*<< <a class="el" href="core__ca_8h.html#aefdcb304363aa42cc311e7a8fc4d0c29">GICInterface_AIAR_INTID_Pos</a>*/)) & <a class="el" href="core__ca_8h.html#a4eca545aea443243d25859b358d15260">GICInterface_AIAR_INTID_Msk</a>)</td>
4024 </div><div class="memdoc">
4028 <a id="a4eca545aea443243d25859b358d15260" name="a4eca545aea443243d25859b358d15260"></a>
4029 <h2 class="memtitle"><span class="permalink"><a href="#a4eca545aea443243d25859b358d15260">◆ </a></span>GICInterface_AIAR_INTID_Msk</h2>
4031 <div class="memitem">
4032 <div class="memproto">
4033 <table class="memname">
4035 <td class="memname">#define GICInterface_AIAR_INTID_Msk   (0xFFFFFFU /*<< <a class="el" href="core__ca_8h.html#aefdcb304363aa42cc311e7a8fc4d0c29">GICInterface_AIAR_INTID_Pos</a>*/)</td>
4038 </div><div class="memdoc">
4039 <p>PTIM AIAR: INTID Mask </p>
4043 <a id="aefdcb304363aa42cc311e7a8fc4d0c29" name="aefdcb304363aa42cc311e7a8fc4d0c29"></a>
4044 <h2 class="memtitle"><span class="permalink"><a href="#aefdcb304363aa42cc311e7a8fc4d0c29">◆ </a></span>GICInterface_AIAR_INTID_Pos</h2>
4046 <div class="memitem">
4047 <div class="memproto">
4048 <table class="memname">
4050 <td class="memname">#define GICInterface_AIAR_INTID_Pos   0U</td>
4053 </div><div class="memdoc">
4054 <p>PTIM AIAR: INTID Position </p>
4058 <a id="a4ebcb87bed742c0b28d08f5c668f9033" name="a4ebcb87bed742c0b28d08f5c668f9033"></a>
4059 <h2 class="memtitle"><span class="permalink"><a href="#a4ebcb87bed742c0b28d08f5c668f9033">◆ </a></span>GICInterface_BPR_Binary_Point</h2>
4061 <div class="memitem">
4062 <div class="memproto">
4063 <table class="memname">
4065 <td class="memname">#define GICInterface_BPR_Binary_Point</td>
4067 <td class="paramtype"> </td>
4068 <td class="paramname">x</td><td>)</td>
4069 <td>   (((uint32_t)(((uint32_t)(x)) /*<< <a class="el" href="core__ca_8h.html#ab1be8491d3c5f996d484e4664a24ed53">GICInterface_BPR_Binary_Point_Pos</a>*/)) & <a class="el" href="core__ca_8h.html#a77e90d30a84d26f405b3fc6e7000370c">GICInterface_BPR_Binary_Point_Msk</a>)</td>
4072 </div><div class="memdoc">
4076 <a id="a77e90d30a84d26f405b3fc6e7000370c" name="a77e90d30a84d26f405b3fc6e7000370c"></a>
4077 <h2 class="memtitle"><span class="permalink"><a href="#a77e90d30a84d26f405b3fc6e7000370c">◆ </a></span>GICInterface_BPR_Binary_Point_Msk</h2>
4079 <div class="memitem">
4080 <div class="memproto">
4081 <table class="memname">
4083 <td class="memname">#define GICInterface_BPR_Binary_Point_Msk   (0x7U /*<< <a class="el" href="core__ca_8h.html#ab1be8491d3c5f996d484e4664a24ed53">GICInterface_BPR_Binary_Point_Pos</a>*/)</td>
4086 </div><div class="memdoc">
4087 <p>PTIM BPR: Binary_Point Mask </p>
4091 <a id="ab1be8491d3c5f996d484e4664a24ed53" name="ab1be8491d3c5f996d484e4664a24ed53"></a>
4092 <h2 class="memtitle"><span class="permalink"><a href="#ab1be8491d3c5f996d484e4664a24ed53">◆ </a></span>GICInterface_BPR_Binary_Point_Pos</h2>
4094 <div class="memitem">
4095 <div class="memproto">
4096 <table class="memname">
4098 <td class="memname">#define GICInterface_BPR_Binary_Point_Pos   0U</td>
4101 </div><div class="memdoc">
4102 <p>PTIM BPR: Binary_Point Position </p>
4106 <a id="aaa6e31976be4c7fd0712873df95ff76e" name="aaa6e31976be4c7fd0712873df95ff76e"></a>
4107 <h2 class="memtitle"><span class="permalink"><a href="#aaa6e31976be4c7fd0712873df95ff76e">◆ </a></span>GICInterface_CTLR_Enable</h2>
4109 <div class="memitem">
4110 <div class="memproto">
4111 <table class="memname">
4113 <td class="memname">#define GICInterface_CTLR_Enable</td>
4115 <td class="paramtype"> </td>
4116 <td class="paramname">x</td><td>)</td>
4117 <td>   (((uint32_t)(((uint32_t)(x)) /*<< <a class="el" href="core__ca_8h.html#a23a54215a53eac983daab61b98a42dac">GICInterface_CTLR_Enable_Pos</a>*/)) & <a class="el" href="core__ca_8h.html#a5b7bfcdc714a0f56aabe7aada107c0b0">GICInterface_CTLR_Enable_Msk</a>)</td>
4120 </div><div class="memdoc">
4124 <a id="a5b7bfcdc714a0f56aabe7aada107c0b0" name="a5b7bfcdc714a0f56aabe7aada107c0b0"></a>
4125 <h2 class="memtitle"><span class="permalink"><a href="#a5b7bfcdc714a0f56aabe7aada107c0b0">◆ </a></span>GICInterface_CTLR_Enable_Msk</h2>
4127 <div class="memitem">
4128 <div class="memproto">
4129 <table class="memname">
4131 <td class="memname">#define GICInterface_CTLR_Enable_Msk   (0x1U /*<< <a class="el" href="core__ca_8h.html#a23a54215a53eac983daab61b98a42dac">GICInterface_CTLR_Enable_Pos</a>*/)</td>
4134 </div><div class="memdoc">
4135 <p>PTIM CTLR: Enable Mask </p>
4139 <a id="a23a54215a53eac983daab61b98a42dac" name="a23a54215a53eac983daab61b98a42dac"></a>
4140 <h2 class="memtitle"><span class="permalink"><a href="#a23a54215a53eac983daab61b98a42dac">◆ </a></span>GICInterface_CTLR_Enable_Pos</h2>
4142 <div class="memitem">
4143 <div class="memproto">
4144 <table class="memname">
4146 <td class="memname">#define GICInterface_CTLR_Enable_Pos   0U</td>
4149 </div><div class="memdoc">
4150 <p>PTIM CTLR: Enable Position </p>
4154 <a id="a6ff56d88ebfcc520e7f27a7dbfcdcf7a" name="a6ff56d88ebfcc520e7f27a7dbfcdcf7a"></a>
4155 <h2 class="memtitle"><span class="permalink"><a href="#a6ff56d88ebfcc520e7f27a7dbfcdcf7a">◆ </a></span>GICInterface_DIR_INTID</h2>
4157 <div class="memitem">
4158 <div class="memproto">
4159 <table class="memname">
4161 <td class="memname">#define GICInterface_DIR_INTID</td>
4163 <td class="paramtype"> </td>
4164 <td class="paramname">x</td><td>)</td>
4165 <td>   (((uint32_t)(((uint32_t)(x)) /*<< <a class="el" href="core__ca_8h.html#ac9c4fb306629c6c0e1821ac4cb82e46a">GICInterface_DIR_INTID_Pos</a>*/)) & <a class="el" href="core__ca_8h.html#a9baee7d21c9c7b278b4e4e92a7e242b8">GICInterface_DIR_INTID_Msk</a>)</td>
4168 </div><div class="memdoc">
4172 <a id="a9baee7d21c9c7b278b4e4e92a7e242b8" name="a9baee7d21c9c7b278b4e4e92a7e242b8"></a>
4173 <h2 class="memtitle"><span class="permalink"><a href="#a9baee7d21c9c7b278b4e4e92a7e242b8">◆ </a></span>GICInterface_DIR_INTID_Msk</h2>
4175 <div class="memitem">
4176 <div class="memproto">
4177 <table class="memname">
4179 <td class="memname">#define GICInterface_DIR_INTID_Msk   (0xFFFFFFU /*<< <a class="el" href="core__ca_8h.html#ac9c4fb306629c6c0e1821ac4cb82e46a">GICInterface_DIR_INTID_Pos</a>*/)</td>
4182 </div><div class="memdoc">
4183 <p>PTIM DIR: INTID Mask </p>
4187 <a id="ac9c4fb306629c6c0e1821ac4cb82e46a" name="ac9c4fb306629c6c0e1821ac4cb82e46a"></a>
4188 <h2 class="memtitle"><span class="permalink"><a href="#ac9c4fb306629c6c0e1821ac4cb82e46a">◆ </a></span>GICInterface_DIR_INTID_Pos</h2>
4190 <div class="memitem">
4191 <div class="memproto">
4192 <table class="memname">
4194 <td class="memname">#define GICInterface_DIR_INTID_Pos   0U</td>
4197 </div><div class="memdoc">
4198 <p>PTIM DIR: INTID Position </p>
4202 <a id="af92688869c3fe1172bd2be443cd42f74" name="af92688869c3fe1172bd2be443cd42f74"></a>
4203 <h2 class="memtitle"><span class="permalink"><a href="#af92688869c3fe1172bd2be443cd42f74">◆ </a></span>GICInterface_EOIR_INTID</h2>
4205 <div class="memitem">
4206 <div class="memproto">
4207 <table class="memname">
4209 <td class="memname">#define GICInterface_EOIR_INTID</td>
4211 <td class="paramtype"> </td>
4212 <td class="paramname">x</td><td>)</td>
4213 <td>   (((uint32_t)(((uint32_t)(x)) /*<< <a class="el" href="core__ca_8h.html#a101da35ef97f5bdf0593fbf1f8a7335c">GICInterface_EOIR_INTID_Pos</a>*/)) & <a class="el" href="core__ca_8h.html#a31d46bd478e4cff2c41ddd86f1c2151a">GICInterface_EOIR_INTID_Msk</a>)</td>
4216 </div><div class="memdoc">
4220 <a id="a31d46bd478e4cff2c41ddd86f1c2151a" name="a31d46bd478e4cff2c41ddd86f1c2151a"></a>
4221 <h2 class="memtitle"><span class="permalink"><a href="#a31d46bd478e4cff2c41ddd86f1c2151a">◆ </a></span>GICInterface_EOIR_INTID_Msk</h2>
4223 <div class="memitem">
4224 <div class="memproto">
4225 <table class="memname">
4227 <td class="memname">#define GICInterface_EOIR_INTID_Msk   (0xFFFFFFU /*<< <a class="el" href="core__ca_8h.html#a101da35ef97f5bdf0593fbf1f8a7335c">GICInterface_EOIR_INTID_Pos</a>*/)</td>
4230 </div><div class="memdoc">
4231 <p>PTIM EOIR: INTID Mask </p>
4235 <a id="a101da35ef97f5bdf0593fbf1f8a7335c" name="a101da35ef97f5bdf0593fbf1f8a7335c"></a>
4236 <h2 class="memtitle"><span class="permalink"><a href="#a101da35ef97f5bdf0593fbf1f8a7335c">◆ </a></span>GICInterface_EOIR_INTID_Pos</h2>
4238 <div class="memitem">
4239 <div class="memproto">
4240 <table class="memname">
4242 <td class="memname">#define GICInterface_EOIR_INTID_Pos   0U</td>
4245 </div><div class="memdoc">
4246 <p>PTIM EOIR: INTID Position </p>
4250 <a id="a38b60af419b00e92185a98a09d82d562" name="a38b60af419b00e92185a98a09d82d562"></a>
4251 <h2 class="memtitle"><span class="permalink"><a href="#a38b60af419b00e92185a98a09d82d562">◆ </a></span>GICInterface_HPPIR_INTID</h2>
4253 <div class="memitem">
4254 <div class="memproto">
4255 <table class="memname">
4257 <td class="memname">#define GICInterface_HPPIR_INTID</td>
4259 <td class="paramtype"> </td>
4260 <td class="paramname">x</td><td>)</td>
4261 <td>   (((uint32_t)(((uint32_t)(x)) /*<< <a class="el" href="core__ca_8h.html#a0951b34200d0d4b1cd18dd8cc9af1224">GICInterface_HPPIR_INTID_Pos</a>*/)) & <a class="el" href="core__ca_8h.html#a26f9cea29872fdd172ce51c210e72235">GICInterface_HPPIR_INTID_Msk</a>)</td>
4264 </div><div class="memdoc">
4268 <a id="a26f9cea29872fdd172ce51c210e72235" name="a26f9cea29872fdd172ce51c210e72235"></a>
4269 <h2 class="memtitle"><span class="permalink"><a href="#a26f9cea29872fdd172ce51c210e72235">◆ </a></span>GICInterface_HPPIR_INTID_Msk</h2>
4271 <div class="memitem">
4272 <div class="memproto">
4273 <table class="memname">
4275 <td class="memname">#define GICInterface_HPPIR_INTID_Msk   (0xFFFFFFU /*<< <a class="el" href="core__ca_8h.html#a0951b34200d0d4b1cd18dd8cc9af1224">GICInterface_HPPIR_INTID_Pos</a>*/)</td>
4278 </div><div class="memdoc">
4279 <p>PTIM HPPIR: INTID Mask </p>
4283 <a id="a0951b34200d0d4b1cd18dd8cc9af1224" name="a0951b34200d0d4b1cd18dd8cc9af1224"></a>
4284 <h2 class="memtitle"><span class="permalink"><a href="#a0951b34200d0d4b1cd18dd8cc9af1224">◆ </a></span>GICInterface_HPPIR_INTID_Pos</h2>
4286 <div class="memitem">
4287 <div class="memproto">
4288 <table class="memname">
4290 <td class="memname">#define GICInterface_HPPIR_INTID_Pos   0U</td>
4293 </div><div class="memdoc">
4294 <p>PTIM HPPIR: INTID Position </p>
4298 <a id="a83cfd1ed557e7d19c3ff09b13d1bc63c" name="a83cfd1ed557e7d19c3ff09b13d1bc63c"></a>
4299 <h2 class="memtitle"><span class="permalink"><a href="#a83cfd1ed557e7d19c3ff09b13d1bc63c">◆ </a></span>GICInterface_IAR_INTID</h2>
4301 <div class="memitem">
4302 <div class="memproto">
4303 <table class="memname">
4305 <td class="memname">#define GICInterface_IAR_INTID</td>
4307 <td class="paramtype"> </td>
4308 <td class="paramname">x</td><td>)</td>
4309 <td>   (((uint32_t)(((uint32_t)(x)) /*<< <a class="el" href="core__ca_8h.html#a25b2030f094c7c5e61fb60f7ab537a29">GICInterface_IAR_INTID_Pos</a>*/)) & <a class="el" href="core__ca_8h.html#a65c7a27d6678c414fbad22c0a0bee56e">GICInterface_IAR_INTID_Msk</a>)</td>
4312 </div><div class="memdoc">
4316 <a id="a65c7a27d6678c414fbad22c0a0bee56e" name="a65c7a27d6678c414fbad22c0a0bee56e"></a>
4317 <h2 class="memtitle"><span class="permalink"><a href="#a65c7a27d6678c414fbad22c0a0bee56e">◆ </a></span>GICInterface_IAR_INTID_Msk</h2>
4319 <div class="memitem">
4320 <div class="memproto">
4321 <table class="memname">
4323 <td class="memname">#define GICInterface_IAR_INTID_Msk   (0xFFFFFFU /*<< <a class="el" href="core__ca_8h.html#a25b2030f094c7c5e61fb60f7ab537a29">GICInterface_IAR_INTID_Pos</a>*/)</td>
4326 </div><div class="memdoc">
4327 <p>PTIM IAR: INTID Mask </p>
4331 <a id="a25b2030f094c7c5e61fb60f7ab537a29" name="a25b2030f094c7c5e61fb60f7ab537a29"></a>
4332 <h2 class="memtitle"><span class="permalink"><a href="#a25b2030f094c7c5e61fb60f7ab537a29">◆ </a></span>GICInterface_IAR_INTID_Pos</h2>
4334 <div class="memitem">
4335 <div class="memproto">
4336 <table class="memname">
4338 <td class="memname">#define GICInterface_IAR_INTID_Pos   0U</td>
4341 </div><div class="memdoc">
4342 <p>PTIM IAR: INTID Position </p>
4346 <a id="a8dc9c6a1f189721daa9075a9a322ed24" name="a8dc9c6a1f189721daa9075a9a322ed24"></a>
4347 <h2 class="memtitle"><span class="permalink"><a href="#a8dc9c6a1f189721daa9075a9a322ed24">◆ </a></span>GICInterface_IIDR_Arch_version</h2>
4349 <div class="memitem">
4350 <div class="memproto">
4351 <table class="memname">
4353 <td class="memname">#define GICInterface_IIDR_Arch_version</td>
4355 <td class="paramtype"> </td>
4356 <td class="paramname">x</td><td>)</td>
4357 <td>   (((uint32_t)(((uint32_t)(x)) << <a class="el" href="core__ca_8h.html#a0006025e23900973bd2bc2b89ff66325">GICInterface_IIDR_Arch_version_Pos</a>)) & <a class="el" href="core__ca_8h.html#a8a5a87c9eb30f036d1e65398337337c2">GICInterface_IIDR_Arch_version_Msk</a>)</td>
4360 </div><div class="memdoc">
4364 <a id="a8a5a87c9eb30f036d1e65398337337c2" name="a8a5a87c9eb30f036d1e65398337337c2"></a>
4365 <h2 class="memtitle"><span class="permalink"><a href="#a8a5a87c9eb30f036d1e65398337337c2">◆ </a></span>GICInterface_IIDR_Arch_version_Msk</h2>
4367 <div class="memitem">
4368 <div class="memproto">
4369 <table class="memname">
4371 <td class="memname">#define GICInterface_IIDR_Arch_version_Msk   (0xFU << <a class="el" href="core__ca_8h.html#a0006025e23900973bd2bc2b89ff66325">GICInterface_IIDR_Arch_version_Pos</a>)</td>
4374 </div><div class="memdoc">
4375 <p>GICInterface IIDR: Arch_version Mask </p>
4379 <a id="a0006025e23900973bd2bc2b89ff66325" name="a0006025e23900973bd2bc2b89ff66325"></a>
4380 <h2 class="memtitle"><span class="permalink"><a href="#a0006025e23900973bd2bc2b89ff66325">◆ </a></span>GICInterface_IIDR_Arch_version_Pos</h2>
4382 <div class="memitem">
4383 <div class="memproto">
4384 <table class="memname">
4386 <td class="memname">#define GICInterface_IIDR_Arch_version_Pos   16U</td>
4389 </div><div class="memdoc">
4390 <p>GICInterface IIDR: Arch_version Position </p>
4394 <a id="ad4ae4c6ad0dc3751e3876e0d5771e3b3" name="ad4ae4c6ad0dc3751e3876e0d5771e3b3"></a>
4395 <h2 class="memtitle"><span class="permalink"><a href="#ad4ae4c6ad0dc3751e3876e0d5771e3b3">◆ </a></span>GICInterface_IIDR_Implementer</h2>
4397 <div class="memitem">
4398 <div class="memproto">
4399 <table class="memname">
4401 <td class="memname">#define GICInterface_IIDR_Implementer</td>
4403 <td class="paramtype"> </td>
4404 <td class="paramname">x</td><td>)</td>
4405 <td>   (((uint32_t)(((uint32_t)(x)) /*<< <a class="el" href="core__ca_8h.html#ad2ed35ce0fc0f10dcfce477c15f00f67">GICInterface_IIDR_Implementer_Pos</a>*/)) & <a class="el" href="core__ca_8h.html#a236375bbcaae3f7a9d45b361b246d1bb">GICInterface_IIDR_Implementer_Msk</a>)</td>
4408 </div><div class="memdoc">
4412 <a id="a236375bbcaae3f7a9d45b361b246d1bb" name="a236375bbcaae3f7a9d45b361b246d1bb"></a>
4413 <h2 class="memtitle"><span class="permalink"><a href="#a236375bbcaae3f7a9d45b361b246d1bb">◆ </a></span>GICInterface_IIDR_Implementer_Msk</h2>
4415 <div class="memitem">
4416 <div class="memproto">
4417 <table class="memname">
4419 <td class="memname">#define GICInterface_IIDR_Implementer_Msk   (0xFFFU /*<< <a class="el" href="core__ca_8h.html#ad2ed35ce0fc0f10dcfce477c15f00f67">GICInterface_IIDR_Implementer_Pos</a>*/)</td>
4422 </div><div class="memdoc">
4423 <p>GICInterface IIDR: Implementer Mask </p>
4427 <a id="ad2ed35ce0fc0f10dcfce477c15f00f67" name="ad2ed35ce0fc0f10dcfce477c15f00f67"></a>
4428 <h2 class="memtitle"><span class="permalink"><a href="#ad2ed35ce0fc0f10dcfce477c15f00f67">◆ </a></span>GICInterface_IIDR_Implementer_Pos</h2>
4430 <div class="memitem">
4431 <div class="memproto">
4432 <table class="memname">
4434 <td class="memname">#define GICInterface_IIDR_Implementer_Pos   0U</td>
4437 </div><div class="memdoc">
4438 <p>GICInterface IIDR: Implementer Position </p>
4442 <a id="a839baee0cf697e8d259679352e440652" name="a839baee0cf697e8d259679352e440652"></a>
4443 <h2 class="memtitle"><span class="permalink"><a href="#a839baee0cf697e8d259679352e440652">◆ </a></span>GICInterface_IIDR_ProductID</h2>
4445 <div class="memitem">
4446 <div class="memproto">
4447 <table class="memname">
4449 <td class="memname">#define GICInterface_IIDR_ProductID</td>
4451 <td class="paramtype"> </td>
4452 <td class="paramname">x</td><td>)</td>
4453 <td>   (((uint32_t)(((uint32_t)(x)) << <a class="el" href="core__ca_8h.html#ac5da4a6801384f51c427e8ab5ff05cba">GICInterface_IIDR_ProductID_Pos</a>)) & <a class="el" href="core__ca_8h.html#a7253c0646d972858f8c75e650d25b3ec">GICInterface_IIDR_ProductID_Msk</a>)</td>
4456 </div><div class="memdoc">
4460 <a id="a7253c0646d972858f8c75e650d25b3ec" name="a7253c0646d972858f8c75e650d25b3ec"></a>
4461 <h2 class="memtitle"><span class="permalink"><a href="#a7253c0646d972858f8c75e650d25b3ec">◆ </a></span>GICInterface_IIDR_ProductID_Msk</h2>
4463 <div class="memitem">
4464 <div class="memproto">
4465 <table class="memname">
4467 <td class="memname">#define GICInterface_IIDR_ProductID_Msk   (0xFFFU << <a class="el" href="core__ca_8h.html#ac5da4a6801384f51c427e8ab5ff05cba">GICInterface_IIDR_ProductID_Pos</a>)</td>
4470 </div><div class="memdoc">
4471 <p>GICInterface IIDR: ProductID Mask </p>
4475 <a id="ac5da4a6801384f51c427e8ab5ff05cba" name="ac5da4a6801384f51c427e8ab5ff05cba"></a>
4476 <h2 class="memtitle"><span class="permalink"><a href="#ac5da4a6801384f51c427e8ab5ff05cba">◆ </a></span>GICInterface_IIDR_ProductID_Pos</h2>
4478 <div class="memitem">
4479 <div class="memproto">
4480 <table class="memname">
4482 <td class="memname">#define GICInterface_IIDR_ProductID_Pos   20U</td>
4485 </div><div class="memdoc">
4486 <p>GICInterface IIDR: ProductID Position </p>
4490 <a id="af03805237be902c223d23f8a19b6b2da" name="af03805237be902c223d23f8a19b6b2da"></a>
4491 <h2 class="memtitle"><span class="permalink"><a href="#af03805237be902c223d23f8a19b6b2da">◆ </a></span>GICInterface_IIDR_Revision</h2>
4493 <div class="memitem">
4494 <div class="memproto">
4495 <table class="memname">
4497 <td class="memname">#define GICInterface_IIDR_Revision</td>
4499 <td class="paramtype"> </td>
4500 <td class="paramname">x</td><td>)</td>
4501 <td>   (((uint32_t)(((uint32_t)(x)) << <a class="el" href="core__ca_8h.html#a4332a64581e1c031918b50e0d32ecff2">GICInterface_IIDR_Revision_Pos</a>)) & <a class="el" href="core__ca_8h.html#ab916e22aa1b8a7589e028a9189a768ae">GICInterface_IIDR_Revision_Msk</a>)</td>
4504 </div><div class="memdoc">
4508 <a id="ab916e22aa1b8a7589e028a9189a768ae" name="ab916e22aa1b8a7589e028a9189a768ae"></a>
4509 <h2 class="memtitle"><span class="permalink"><a href="#ab916e22aa1b8a7589e028a9189a768ae">◆ </a></span>GICInterface_IIDR_Revision_Msk</h2>
4511 <div class="memitem">
4512 <div class="memproto">
4513 <table class="memname">
4515 <td class="memname">#define GICInterface_IIDR_Revision_Msk   (0xFU << <a class="el" href="core__ca_8h.html#a4332a64581e1c031918b50e0d32ecff2">GICInterface_IIDR_Revision_Pos</a>)</td>
4518 </div><div class="memdoc">
4519 <p>GICInterface IIDR: Revision Mask </p>
4523 <a id="a4332a64581e1c031918b50e0d32ecff2" name="a4332a64581e1c031918b50e0d32ecff2"></a>
4524 <h2 class="memtitle"><span class="permalink"><a href="#a4332a64581e1c031918b50e0d32ecff2">◆ </a></span>GICInterface_IIDR_Revision_Pos</h2>
4526 <div class="memitem">
4527 <div class="memproto">
4528 <table class="memname">
4530 <td class="memname">#define GICInterface_IIDR_Revision_Pos   12U</td>
4533 </div><div class="memdoc">
4534 <p>GICInterface IIDR: Revision Position </p>
4538 <a id="a149d248020f9bb305a8f98dbe22d683f" name="a149d248020f9bb305a8f98dbe22d683f"></a>
4539 <h2 class="memtitle"><span class="permalink"><a href="#a149d248020f9bb305a8f98dbe22d683f">◆ </a></span>GICInterface_PMR_Priority</h2>
4541 <div class="memitem">
4542 <div class="memproto">
4543 <table class="memname">
4545 <td class="memname">#define GICInterface_PMR_Priority</td>
4547 <td class="paramtype"> </td>
4548 <td class="paramname">x</td><td>)</td>
4549 <td>   (((uint32_t)(((uint32_t)(x)) /*<< <a class="el" href="core__ca_8h.html#a71c3b07764634704decda87508d302aa">GICInterface_PMR_Priority_Pos</a>*/)) & <a class="el" href="core__ca_8h.html#af4e6f38664b7a24008df71779e53b628">GICInterface_PMR_Priority_Msk</a>)</td>
4552 </div><div class="memdoc">
4556 <a id="af4e6f38664b7a24008df71779e53b628" name="af4e6f38664b7a24008df71779e53b628"></a>
4557 <h2 class="memtitle"><span class="permalink"><a href="#af4e6f38664b7a24008df71779e53b628">◆ </a></span>GICInterface_PMR_Priority_Msk</h2>
4559 <div class="memitem">
4560 <div class="memproto">
4561 <table class="memname">
4563 <td class="memname">#define GICInterface_PMR_Priority_Msk   (0xFFU /*<< <a class="el" href="core__ca_8h.html#a71c3b07764634704decda87508d302aa">GICInterface_PMR_Priority_Pos</a>*/)</td>
4566 </div><div class="memdoc">
4567 <p>PTIM PMR: Priority Mask </p>
4571 <a id="a71c3b07764634704decda87508d302aa" name="a71c3b07764634704decda87508d302aa"></a>
4572 <h2 class="memtitle"><span class="permalink"><a href="#a71c3b07764634704decda87508d302aa">◆ </a></span>GICInterface_PMR_Priority_Pos</h2>
4574 <div class="memitem">
4575 <div class="memproto">
4576 <table class="memname">
4578 <td class="memname">#define GICInterface_PMR_Priority_Pos   0U</td>
4581 </div><div class="memdoc">
4582 <p>PTIM PMR: Priority Position </p>
4586 <a id="a3b85565c9bdf010acc15523073aa1789" name="a3b85565c9bdf010acc15523073aa1789"></a>
4587 <h2 class="memtitle"><span class="permalink"><a href="#a3b85565c9bdf010acc15523073aa1789">◆ </a></span>GICInterface_RPR_INTID</h2>
4589 <div class="memitem">
4590 <div class="memproto">
4591 <table class="memname">
4593 <td class="memname">#define GICInterface_RPR_INTID</td>
4595 <td class="paramtype"> </td>
4596 <td class="paramname">x</td><td>)</td>
4597 <td>   (((uint32_t)(((uint32_t)(x)) /*<< <a class="el" href="core__ca_8h.html#ad3081f7f2410d2895c727e6d11d53253">GICInterface_RPR_INTID_Pos</a>*/)) & <a class="el" href="core__ca_8h.html#aee1baadc46e37df107730db62340824f">GICInterface_RPR_INTID_Msk</a>)</td>
4600 </div><div class="memdoc">
4604 <a id="aee1baadc46e37df107730db62340824f" name="aee1baadc46e37df107730db62340824f"></a>
4605 <h2 class="memtitle"><span class="permalink"><a href="#aee1baadc46e37df107730db62340824f">◆ </a></span>GICInterface_RPR_INTID_Msk</h2>
4607 <div class="memitem">
4608 <div class="memproto">
4609 <table class="memname">
4611 <td class="memname">#define GICInterface_RPR_INTID_Msk   (0xFFU /*<< <a class="el" href="core__ca_8h.html#ad3081f7f2410d2895c727e6d11d53253">GICInterface_RPR_INTID_Pos</a>*/)</td>
4614 </div><div class="memdoc">
4615 <p>PTIM RPR: INTID Mask </p>
4619 <a id="ad3081f7f2410d2895c727e6d11d53253" name="ad3081f7f2410d2895c727e6d11d53253"></a>
4620 <h2 class="memtitle"><span class="permalink"><a href="#ad3081f7f2410d2895c727e6d11d53253">◆ </a></span>GICInterface_RPR_INTID_Pos</h2>
4622 <div class="memitem">
4623 <div class="memproto">
4624 <table class="memname">
4626 <td class="memname">#define GICInterface_RPR_INTID_Pos   0U</td>
4629 </div><div class="memdoc">
4630 <p>PTIM RPR: INTID Position </p>
4634 <a id="aeaa7aff9ec9c1e9b4248600198295bda" name="aeaa7aff9ec9c1e9b4248600198295bda"></a>
4635 <h2 class="memtitle"><span class="permalink"><a href="#aeaa7aff9ec9c1e9b4248600198295bda">◆ </a></span>GICInterface_STATUSR_ASV</h2>
4637 <div class="memitem">
4638 <div class="memproto">
4639 <table class="memname">
4641 <td class="memname">#define GICInterface_STATUSR_ASV</td>
4643 <td class="paramtype"> </td>
4644 <td class="paramname">x</td><td>)</td>
4645 <td>   (((uint32_t)(((uint32_t)(x)) << <a class="el" href="core__ca_8h.html#ab8fb5c170d172871cbbf690c5d4b7ea7">GICInterface_STATUSR_ASV_Pos</a>)) & <a class="el" href="core__ca_8h.html#ae156c36ac00480f8ead8bc46f061671f">GICInterface_STATUSR_ASV_Msk</a>)</td>
4648 </div><div class="memdoc">
4652 <a id="ae156c36ac00480f8ead8bc46f061671f" name="ae156c36ac00480f8ead8bc46f061671f"></a>
4653 <h2 class="memtitle"><span class="permalink"><a href="#ae156c36ac00480f8ead8bc46f061671f">◆ </a></span>GICInterface_STATUSR_ASV_Msk</h2>
4655 <div class="memitem">
4656 <div class="memproto">
4657 <table class="memname">
4659 <td class="memname">#define GICInterface_STATUSR_ASV_Msk   (0x1U << <a class="el" href="core__ca_8h.html#ab8fb5c170d172871cbbf690c5d4b7ea7">GICInterface_STATUSR_ASV_Pos</a>)</td>
4662 </div><div class="memdoc">
4663 <p>GICInterface STATUSR: ASV Mask </p>
4667 <a id="ab8fb5c170d172871cbbf690c5d4b7ea7" name="ab8fb5c170d172871cbbf690c5d4b7ea7"></a>
4668 <h2 class="memtitle"><span class="permalink"><a href="#ab8fb5c170d172871cbbf690c5d4b7ea7">◆ </a></span>GICInterface_STATUSR_ASV_Pos</h2>
4670 <div class="memitem">
4671 <div class="memproto">
4672 <table class="memname">
4674 <td class="memname">#define GICInterface_STATUSR_ASV_Pos   4U</td>
4677 </div><div class="memdoc">
4678 <p>GICInterface STATUSR: ASV Position </p>
4682 <a id="aed0f5fcd7a7ce0eb0c60c1d206df2bc9" name="aed0f5fcd7a7ce0eb0c60c1d206df2bc9"></a>
4683 <h2 class="memtitle"><span class="permalink"><a href="#aed0f5fcd7a7ce0eb0c60c1d206df2bc9">◆ </a></span>GICInterface_STATUSR_RRD</h2>
4685 <div class="memitem">
4686 <div class="memproto">
4687 <table class="memname">
4689 <td class="memname">#define GICInterface_STATUSR_RRD</td>
4691 <td class="paramtype"> </td>
4692 <td class="paramname">x</td><td>)</td>
4693 <td>   (((uint32_t)(((uint32_t)(x)) /*<< <a class="el" href="core__ca_8h.html#a31d5831811352718da5ffeae8cfbd22d">GICInterface_STATUSR_RRD_Pos</a>*/)) & <a class="el" href="core__ca_8h.html#a7efdc959647f530286fd2d29becf3842">GICInterface_STATUSR_RRD_Msk</a>)</td>
4696 </div><div class="memdoc">
4700 <a id="a7efdc959647f530286fd2d29becf3842" name="a7efdc959647f530286fd2d29becf3842"></a>
4701 <h2 class="memtitle"><span class="permalink"><a href="#a7efdc959647f530286fd2d29becf3842">◆ </a></span>GICInterface_STATUSR_RRD_Msk</h2>
4703 <div class="memitem">
4704 <div class="memproto">
4705 <table class="memname">
4707 <td class="memname">#define GICInterface_STATUSR_RRD_Msk   (0x1U /*<< <a class="el" href="core__ca_8h.html#a31d5831811352718da5ffeae8cfbd22d">GICInterface_STATUSR_RRD_Pos</a>*/)</td>
4710 </div><div class="memdoc">
4711 <p>GICInterface STATUSR: RRD Mask </p>
4715 <a id="a31d5831811352718da5ffeae8cfbd22d" name="a31d5831811352718da5ffeae8cfbd22d"></a>
4716 <h2 class="memtitle"><span class="permalink"><a href="#a31d5831811352718da5ffeae8cfbd22d">◆ </a></span>GICInterface_STATUSR_RRD_Pos</h2>
4718 <div class="memitem">
4719 <div class="memproto">
4720 <table class="memname">
4722 <td class="memname">#define GICInterface_STATUSR_RRD_Pos   0U</td>
4725 </div><div class="memdoc">
4726 <p>GICInterface STATUSR: RRD Position </p>
4730 <a id="a81d59c7f5d66114e6450a679d961412b" name="a81d59c7f5d66114e6450a679d961412b"></a>
4731 <h2 class="memtitle"><span class="permalink"><a href="#a81d59c7f5d66114e6450a679d961412b">◆ </a></span>GICInterface_STATUSR_RWOD</h2>
4733 <div class="memitem">
4734 <div class="memproto">
4735 <table class="memname">
4737 <td class="memname">#define GICInterface_STATUSR_RWOD</td>
4739 <td class="paramtype"> </td>
4740 <td class="paramname">x</td><td>)</td>
4741 <td>   (((uint32_t)(((uint32_t)(x)) << <a class="el" href="core__ca_8h.html#a01544142ac5dfb1a0082a91d6624179a">GICInterface_STATUSR_RWOD_Pos</a>)) & <a class="el" href="core__ca_8h.html#ab5f3156c0331d78950808841637b519f">GICInterface_STATUSR_RWOD_Msk</a>)</td>
4744 </div><div class="memdoc">
4748 <a id="ab5f3156c0331d78950808841637b519f" name="ab5f3156c0331d78950808841637b519f"></a>
4749 <h2 class="memtitle"><span class="permalink"><a href="#ab5f3156c0331d78950808841637b519f">◆ </a></span>GICInterface_STATUSR_RWOD_Msk</h2>
4751 <div class="memitem">
4752 <div class="memproto">
4753 <table class="memname">
4755 <td class="memname">#define GICInterface_STATUSR_RWOD_Msk   (0x1U << <a class="el" href="core__ca_8h.html#a01544142ac5dfb1a0082a91d6624179a">GICInterface_STATUSR_RWOD_Pos</a>)</td>
4758 </div><div class="memdoc">
4759 <p>GICInterface STATUSR: RWOD Mask </p>
4763 <a id="a01544142ac5dfb1a0082a91d6624179a" name="a01544142ac5dfb1a0082a91d6624179a"></a>
4764 <h2 class="memtitle"><span class="permalink"><a href="#a01544142ac5dfb1a0082a91d6624179a">◆ </a></span>GICInterface_STATUSR_RWOD_Pos</h2>
4766 <div class="memitem">
4767 <div class="memproto">
4768 <table class="memname">
4770 <td class="memname">#define GICInterface_STATUSR_RWOD_Pos   2U</td>
4773 </div><div class="memdoc">
4774 <p>GICInterface STATUSR: RWOD Position </p>
4778 <a id="a621d80944d8334a2b5f66391b70502f3" name="a621d80944d8334a2b5f66391b70502f3"></a>
4779 <h2 class="memtitle"><span class="permalink"><a href="#a621d80944d8334a2b5f66391b70502f3">◆ </a></span>GICInterface_STATUSR_WRD</h2>
4781 <div class="memitem">
4782 <div class="memproto">
4783 <table class="memname">
4785 <td class="memname">#define GICInterface_STATUSR_WRD</td>
4787 <td class="paramtype"> </td>
4788 <td class="paramname">x</td><td>)</td>
4789 <td>   (((uint32_t)(((uint32_t)(x)) << <a class="el" href="core__ca_8h.html#af4509593e33b8149c23a9b13650bad6c">GICInterface_STATUSR_WRD_Pos</a>)) & <a class="el" href="core__ca_8h.html#a166bcb139f401bf72f56d05c1415707c">GICInterface_STATUSR_WRD_Msk</a>)</td>
4792 </div><div class="memdoc">
4796 <a id="a166bcb139f401bf72f56d05c1415707c" name="a166bcb139f401bf72f56d05c1415707c"></a>
4797 <h2 class="memtitle"><span class="permalink"><a href="#a166bcb139f401bf72f56d05c1415707c">◆ </a></span>GICInterface_STATUSR_WRD_Msk</h2>
4799 <div class="memitem">
4800 <div class="memproto">
4801 <table class="memname">
4803 <td class="memname">#define GICInterface_STATUSR_WRD_Msk   (0x1U << <a class="el" href="core__ca_8h.html#af4509593e33b8149c23a9b13650bad6c">GICInterface_STATUSR_WRD_Pos</a>)</td>
4806 </div><div class="memdoc">
4807 <p>GICInterface STATUSR: WRD Mask </p>
4811 <a id="af4509593e33b8149c23a9b13650bad6c" name="af4509593e33b8149c23a9b13650bad6c"></a>
4812 <h2 class="memtitle"><span class="permalink"><a href="#af4509593e33b8149c23a9b13650bad6c">◆ </a></span>GICInterface_STATUSR_WRD_Pos</h2>
4814 <div class="memitem">
4815 <div class="memproto">
4816 <table class="memname">
4818 <td class="memname">#define GICInterface_STATUSR_WRD_Pos   1U</td>
4821 </div><div class="memdoc">
4822 <p>GICInterface STATUSR: WRD Position </p>
4826 <a id="a8e4b0656d26328a98afa4f81038943cf" name="a8e4b0656d26328a98afa4f81038943cf"></a>
4827 <h2 class="memtitle"><span class="permalink"><a href="#a8e4b0656d26328a98afa4f81038943cf">◆ </a></span>GICInterface_STATUSR_WROD</h2>
4829 <div class="memitem">
4830 <div class="memproto">
4831 <table class="memname">
4833 <td class="memname">#define GICInterface_STATUSR_WROD</td>
4835 <td class="paramtype"> </td>
4836 <td class="paramname">x</td><td>)</td>
4837 <td>   (((uint32_t)(((uint32_t)(x)) << <a class="el" href="core__ca_8h.html#a609fdc19acdc64c72022c8f7e72f9fac">GICInterface_STATUSR_WROD_Pos</a>)) & <a class="el" href="core__ca_8h.html#a316618e6da5aaaa3de21001615afb2ec">GICInterface_STATUSR_WROD_Msk</a>)</td>
4840 </div><div class="memdoc">
4844 <a id="a316618e6da5aaaa3de21001615afb2ec" name="a316618e6da5aaaa3de21001615afb2ec"></a>
4845 <h2 class="memtitle"><span class="permalink"><a href="#a316618e6da5aaaa3de21001615afb2ec">◆ </a></span>GICInterface_STATUSR_WROD_Msk</h2>
4847 <div class="memitem">
4848 <div class="memproto">
4849 <table class="memname">
4851 <td class="memname">#define GICInterface_STATUSR_WROD_Msk   (0x1U << <a class="el" href="core__ca_8h.html#a609fdc19acdc64c72022c8f7e72f9fac">GICInterface_STATUSR_WROD_Pos</a>)</td>
4854 </div><div class="memdoc">
4855 <p>GICInterface STATUSR: WROD Mask </p>
4859 <a id="a609fdc19acdc64c72022c8f7e72f9fac" name="a609fdc19acdc64c72022c8f7e72f9fac"></a>
4860 <h2 class="memtitle"><span class="permalink"><a href="#a609fdc19acdc64c72022c8f7e72f9fac">◆ </a></span>GICInterface_STATUSR_WROD_Pos</h2>
4862 <div class="memitem">
4863 <div class="memproto">
4864 <table class="memname">
4866 <td class="memname">#define GICInterface_STATUSR_WROD_Pos   3U</td>
4869 </div><div class="memdoc">
4870 <p>GICInterface STATUSR: WROD Position </p>
4874 <a id="a8e51cfa91c0b6bbf1df1cff0bde44836" name="a8e51cfa91c0b6bbf1df1cff0bde44836"></a>
4875 <h2 class="memtitle"><span class="permalink"><a href="#a8e51cfa91c0b6bbf1df1cff0bde44836">◆ </a></span>OFFSET_1M</h2>
4877 <div class="memitem">
4878 <div class="memproto">
4879 <table class="memname">
4881 <td class="memname">#define OFFSET_1M   (0x00100000)</td>
4884 </div><div class="memdoc">
4888 <a id="a121c645cdc91018720ceaf1d021fcd89" name="a121c645cdc91018720ceaf1d021fcd89"></a>
4889 <h2 class="memtitle"><span class="permalink"><a href="#a121c645cdc91018720ceaf1d021fcd89">◆ </a></span>OFFSET_4K</h2>
4891 <div class="memitem">
4892 <div class="memproto">
4893 <table class="memname">
4895 <td class="memname">#define OFFSET_4K   (0x00001000)</td>
4898 </div><div class="memdoc">
4902 <a id="af19b9fb664a06a41562176a51c66fcff" name="af19b9fb664a06a41562176a51c66fcff"></a>
4903 <h2 class="memtitle"><span class="permalink"><a href="#af19b9fb664a06a41562176a51c66fcff">◆ </a></span>OFFSET_64K</h2>
4905 <div class="memitem">
4906 <div class="memproto">
4907 <table class="memname">
4909 <td class="memname">#define OFFSET_64K   (0x00010000)</td>
4912 </div><div class="memdoc">
4916 <a id="a295b3b39fa6f7da3650a94551e28218b" name="a295b3b39fa6f7da3650a94551e28218b"></a>
4917 <h2 class="memtitle"><span class="permalink"><a href="#a295b3b39fa6f7da3650a94551e28218b">◆ </a></span>PAGE_4K_B_SHIFT</h2>
4919 <div class="memitem">
4920 <div class="memproto">
4921 <table class="memname">
4923 <td class="memname">#define PAGE_4K_B_SHIFT   (2)</td>
4926 </div><div class="memdoc">
4930 <a id="a17ad8e75e5987a1f98adfc783640b75f" name="a17ad8e75e5987a1f98adfc783640b75f"></a>
4931 <h2 class="memtitle"><span class="permalink"><a href="#a17ad8e75e5987a1f98adfc783640b75f">◆ </a></span>PAGE_4K_C_SHIFT</h2>
4933 <div class="memitem">
4934 <div class="memproto">
4935 <table class="memname">
4937 <td class="memname">#define PAGE_4K_C_SHIFT   (3)</td>
4940 </div><div class="memdoc">
4944 <a id="a8069f8882920692467749cc65f50e1f8" name="a8069f8882920692467749cc65f50e1f8"></a>
4945 <h2 class="memtitle"><span class="permalink"><a href="#a8069f8882920692467749cc65f50e1f8">◆ </a></span>PAGE_4K_TEX0_SHIFT</h2>
4947 <div class="memitem">
4948 <div class="memproto">
4949 <table class="memname">
4951 <td class="memname">#define PAGE_4K_TEX0_SHIFT   (6)</td>
4954 </div><div class="memdoc">
4958 <a id="ac0db1e472f79b641d0e51e4faa6e7e08" name="ac0db1e472f79b641d0e51e4faa6e7e08"></a>
4959 <h2 class="memtitle"><span class="permalink"><a href="#ac0db1e472f79b641d0e51e4faa6e7e08">◆ </a></span>PAGE_4K_TEX1_SHIFT</h2>
4961 <div class="memitem">
4962 <div class="memproto">
4963 <table class="memname">
4965 <td class="memname">#define PAGE_4K_TEX1_SHIFT   (7)</td>
4968 </div><div class="memdoc">
4972 <a id="a0e5c586a7e1928c7efa95e0d5f26e981" name="a0e5c586a7e1928c7efa95e0d5f26e981"></a>
4973 <h2 class="memtitle"><span class="permalink"><a href="#a0e5c586a7e1928c7efa95e0d5f26e981">◆ </a></span>PAGE_4K_TEX2_SHIFT</h2>
4975 <div class="memitem">
4976 <div class="memproto">
4977 <table class="memname">
4979 <td class="memname">#define PAGE_4K_TEX2_SHIFT   (8)</td>
4982 </div><div class="memdoc">
4986 <a id="a234fceea67b5d6c41b0875852d86cc70" name="a234fceea67b5d6c41b0875852d86cc70"></a>
4987 <h2 class="memtitle"><span class="permalink"><a href="#a234fceea67b5d6c41b0875852d86cc70">◆ </a></span>PAGE_4K_TEXCB_MASK</h2>
4989 <div class="memitem">
4990 <div class="memproto">
4991 <table class="memname">
4993 <td class="memname">#define PAGE_4K_TEXCB_MASK   (0xFFFFFE33)</td>
4996 </div><div class="memdoc">
5000 <a id="aedc4abb2636443389128258bd74ce0bd" name="aedc4abb2636443389128258bd74ce0bd"></a>
5001 <h2 class="memtitle"><span class="permalink"><a href="#aedc4abb2636443389128258bd74ce0bd">◆ </a></span>PAGE_64K_B_SHIFT</h2>
5003 <div class="memitem">
5004 <div class="memproto">
5005 <table class="memname">
5007 <td class="memname">#define PAGE_64K_B_SHIFT   (2)</td>
5010 </div><div class="memdoc">
5014 <a id="abc1ce8b3d369d1e054fabf87514c4cd6" name="abc1ce8b3d369d1e054fabf87514c4cd6"></a>
5015 <h2 class="memtitle"><span class="permalink"><a href="#abc1ce8b3d369d1e054fabf87514c4cd6">◆ </a></span>PAGE_64K_C_SHIFT</h2>
5017 <div class="memitem">
5018 <div class="memproto">
5019 <table class="memname">
5021 <td class="memname">#define PAGE_64K_C_SHIFT   (3)</td>
5024 </div><div class="memdoc">
5028 <a id="ab4d67a1d5aa37623272abe4db32677ec" name="ab4d67a1d5aa37623272abe4db32677ec"></a>
5029 <h2 class="memtitle"><span class="permalink"><a href="#ab4d67a1d5aa37623272abe4db32677ec">◆ </a></span>PAGE_64K_TEX0_SHIFT</h2>
5031 <div class="memitem">
5032 <div class="memproto">
5033 <table class="memname">
5035 <td class="memname">#define PAGE_64K_TEX0_SHIFT   (12)</td>
5038 </div><div class="memdoc">
5042 <a id="a9c910152d27ce0a1552e3bb3c88782a6" name="a9c910152d27ce0a1552e3bb3c88782a6"></a>
5043 <h2 class="memtitle"><span class="permalink"><a href="#a9c910152d27ce0a1552e3bb3c88782a6">◆ </a></span>PAGE_64K_TEX1_SHIFT</h2>
5045 <div class="memitem">
5046 <div class="memproto">
5047 <table class="memname">
5049 <td class="memname">#define PAGE_64K_TEX1_SHIFT   (13)</td>
5052 </div><div class="memdoc">
5056 <a id="a8ec4dcea202b5ebc15419f7410a6c0b0" name="a8ec4dcea202b5ebc15419f7410a6c0b0"></a>
5057 <h2 class="memtitle"><span class="permalink"><a href="#a8ec4dcea202b5ebc15419f7410a6c0b0">◆ </a></span>PAGE_64K_TEX2_SHIFT</h2>
5059 <div class="memitem">
5060 <div class="memproto">
5061 <table class="memname">
5063 <td class="memname">#define PAGE_64K_TEX2_SHIFT   (14)</td>
5066 </div><div class="memdoc">
5070 <a id="a666e7d1971403995104586f35d56590b" name="a666e7d1971403995104586f35d56590b"></a>
5071 <h2 class="memtitle"><span class="permalink"><a href="#a666e7d1971403995104586f35d56590b">◆ </a></span>PAGE_64K_TEXCB_MASK</h2>
5073 <div class="memitem">
5074 <div class="memproto">
5075 <table class="memname">
5077 <td class="memname">#define PAGE_64K_TEXCB_MASK   (0xFFFF8FF3)</td>
5080 </div><div class="memdoc">
5084 <a id="ad2d3cf0695c98dc2c4e37ebeb9235b2c" name="ad2d3cf0695c98dc2c4e37ebeb9235b2c"></a>
5085 <h2 class="memtitle"><span class="permalink"><a href="#ad2d3cf0695c98dc2c4e37ebeb9235b2c">◆ </a></span>PAGE_AP2_SHIFT</h2>
5087 <div class="memitem">
5088 <div class="memproto">
5089 <table class="memname">
5091 <td class="memname">#define PAGE_AP2_SHIFT   (9)</td>
5094 </div><div class="memdoc">
5098 <a id="af7d3ee23adcaf9221967791f0e64d830" name="af7d3ee23adcaf9221967791f0e64d830"></a>
5099 <h2 class="memtitle"><span class="permalink"><a href="#af7d3ee23adcaf9221967791f0e64d830">◆ </a></span>PAGE_AP_MASK</h2>
5101 <div class="memitem">
5102 <div class="memproto">
5103 <table class="memname">
5105 <td class="memname">#define PAGE_AP_MASK   (0xFFFFFDCF)</td>
5108 </div><div class="memdoc">
5112 <a id="afed0cfe8a8ab67fe26e961b876db13a3" name="afed0cfe8a8ab67fe26e961b876db13a3"></a>
5113 <h2 class="memtitle"><span class="permalink"><a href="#afed0cfe8a8ab67fe26e961b876db13a3">◆ </a></span>PAGE_AP_SHIFT</h2>
5115 <div class="memitem">
5116 <div class="memproto">
5117 <table class="memname">
5119 <td class="memname">#define PAGE_AP_SHIFT   (4)</td>
5122 </div><div class="memdoc">
5126 <a id="a3a660cdbc121e6510ed815fcb5bc8a44" name="a3a660cdbc121e6510ed815fcb5bc8a44"></a>
5127 <h2 class="memtitle"><span class="permalink"><a href="#a3a660cdbc121e6510ed815fcb5bc8a44">◆ </a></span>PAGE_B_SHIFT</h2>
5129 <div class="memitem">
5130 <div class="memproto">
5131 <table class="memname">
5133 <td class="memname">#define PAGE_B_SHIFT   (2)</td>
5136 </div><div class="memdoc">
5140 <a id="ad9fc2f0cbe58ae4f1afea3cf9817b450" name="ad9fc2f0cbe58ae4f1afea3cf9817b450"></a>
5141 <h2 class="memtitle"><span class="permalink"><a href="#ad9fc2f0cbe58ae4f1afea3cf9817b450">◆ </a></span>PAGE_C_SHIFT</h2>
5143 <div class="memitem">
5144 <div class="memproto">
5145 <table class="memname">
5147 <td class="memname">#define PAGE_C_SHIFT   (3)</td>
5150 </div><div class="memdoc">
5154 <a id="a0a48a4e79188149fbe886a698b6d9cb4" name="a0a48a4e79188149fbe886a698b6d9cb4"></a>
5155 <h2 class="memtitle"><span class="permalink"><a href="#a0a48a4e79188149fbe886a698b6d9cb4">◆ </a></span>PAGE_DOMAIN_MASK</h2>
5157 <div class="memitem">
5158 <div class="memproto">
5159 <table class="memname">
5161 <td class="memname">#define PAGE_DOMAIN_MASK   (0xFFFFFE1F)</td>
5164 </div><div class="memdoc">
5168 <a id="ade787969e64896d0c8fe554f6aa1bc9e" name="ade787969e64896d0c8fe554f6aa1bc9e"></a>
5169 <h2 class="memtitle"><span class="permalink"><a href="#ade787969e64896d0c8fe554f6aa1bc9e">◆ </a></span>PAGE_DOMAIN_SHIFT</h2>
5171 <div class="memitem">
5172 <div class="memproto">
5173 <table class="memname">
5175 <td class="memname">#define PAGE_DOMAIN_SHIFT   (5)</td>
5178 </div><div class="memdoc">
5182 <a id="a82cb818cf0bcf9431ed9d0b52a39fe14" name="a82cb818cf0bcf9431ed9d0b52a39fe14"></a>
5183 <h2 class="memtitle"><span class="permalink"><a href="#a82cb818cf0bcf9431ed9d0b52a39fe14">◆ </a></span>PAGE_L1_DESCRIPTOR</h2>
5185 <div class="memitem">
5186 <div class="memproto">
5187 <table class="memname">
5189 <td class="memname">#define PAGE_L1_DESCRIPTOR   (0x1)</td>
5192 </div><div class="memdoc">
5196 <a id="a9fe764cc3a117a9ab93a301de8bceed1" name="a9fe764cc3a117a9ab93a301de8bceed1"></a>
5197 <h2 class="memtitle"><span class="permalink"><a href="#a9fe764cc3a117a9ab93a301de8bceed1">◆ </a></span>PAGE_L1_MASK</h2>
5199 <div class="memitem">
5200 <div class="memproto">
5201 <table class="memname">
5203 <td class="memname">#define PAGE_L1_MASK   (0xFFFFFFFC)</td>
5206 </div><div class="memdoc">
5210 <a id="aefb20807cde04ea9fee6b197602348cf" name="aefb20807cde04ea9fee6b197602348cf"></a>
5211 <h2 class="memtitle"><span class="permalink"><a href="#aefb20807cde04ea9fee6b197602348cf">◆ </a></span>PAGE_L2_4K_DESC</h2>
5213 <div class="memitem">
5214 <div class="memproto">
5215 <table class="memname">
5217 <td class="memname">#define PAGE_L2_4K_DESC   (0x2)</td>
5220 </div><div class="memdoc">
5224 <a id="abd292694d0155e3b0d4c12895a6c8fa6" name="abd292694d0155e3b0d4c12895a6c8fa6"></a>
5225 <h2 class="memtitle"><span class="permalink"><a href="#abd292694d0155e3b0d4c12895a6c8fa6">◆ </a></span>PAGE_L2_4K_MASK</h2>
5227 <div class="memitem">
5228 <div class="memproto">
5229 <table class="memname">
5231 <td class="memname">#define PAGE_L2_4K_MASK   (0xFFFFFFFD)</td>
5234 </div><div class="memdoc">
5238 <a id="af38d8149733ba83690fd04ac1204bde1" name="af38d8149733ba83690fd04ac1204bde1"></a>
5239 <h2 class="memtitle"><span class="permalink"><a href="#af38d8149733ba83690fd04ac1204bde1">◆ </a></span>PAGE_L2_64K_DESC</h2>
5241 <div class="memitem">
5242 <div class="memproto">
5243 <table class="memname">
5245 <td class="memname">#define PAGE_L2_64K_DESC   (0x1)</td>
5248 </div><div class="memdoc">
5252 <a id="ab3a82626ee70e38285852a1128b75c7a" name="ab3a82626ee70e38285852a1128b75c7a"></a>
5253 <h2 class="memtitle"><span class="permalink"><a href="#ab3a82626ee70e38285852a1128b75c7a">◆ </a></span>PAGE_L2_64K_MASK</h2>
5255 <div class="memitem">
5256 <div class="memproto">
5257 <table class="memname">
5259 <td class="memname">#define PAGE_L2_64K_MASK   (0xFFFFFFFC)</td>
5262 </div><div class="memdoc">
5266 <a id="add5d44ba746fe4d17d8b06a1086aa853" name="add5d44ba746fe4d17d8b06a1086aa853"></a>
5267 <h2 class="memtitle"><span class="permalink"><a href="#add5d44ba746fe4d17d8b06a1086aa853">◆ </a></span>PAGE_NG_MASK</h2>
5269 <div class="memitem">
5270 <div class="memproto">
5271 <table class="memname">
5273 <td class="memname">#define PAGE_NG_MASK   (0xFFFFF7FF)</td>
5276 </div><div class="memdoc">
5280 <a id="a1d9196f2dd260244a4ad7e5b70b0e4c7" name="a1d9196f2dd260244a4ad7e5b70b0e4c7"></a>
5281 <h2 class="memtitle"><span class="permalink"><a href="#a1d9196f2dd260244a4ad7e5b70b0e4c7">◆ </a></span>PAGE_NG_SHIFT</h2>
5283 <div class="memitem">
5284 <div class="memproto">
5285 <table class="memname">
5287 <td class="memname">#define PAGE_NG_SHIFT   (11)</td>
5290 </div><div class="memdoc">
5294 <a id="a618b1432615c3242f53360d4364c5797" name="a618b1432615c3242f53360d4364c5797"></a>
5295 <h2 class="memtitle"><span class="permalink"><a href="#a618b1432615c3242f53360d4364c5797">◆ </a></span>PAGE_NS_MASK</h2>
5297 <div class="memitem">
5298 <div class="memproto">
5299 <table class="memname">
5301 <td class="memname">#define PAGE_NS_MASK   (0xFFFFFFF7)</td>
5304 </div><div class="memdoc">
5308 <a id="a49740f5181adebe63b11c68db731bb0f" name="a49740f5181adebe63b11c68db731bb0f"></a>
5309 <h2 class="memtitle"><span class="permalink"><a href="#a49740f5181adebe63b11c68db731bb0f">◆ </a></span>PAGE_NS_SHIFT</h2>
5311 <div class="memitem">
5312 <div class="memproto">
5313 <table class="memname">
5315 <td class="memname">#define PAGE_NS_SHIFT   (3)</td>
5318 </div><div class="memdoc">
5322 <a id="a604f4f13fcb78ff08d65ef4a1a3f7933" name="a604f4f13fcb78ff08d65ef4a1a3f7933"></a>
5323 <h2 class="memtitle"><span class="permalink"><a href="#a604f4f13fcb78ff08d65ef4a1a3f7933">◆ </a></span>PAGE_P_MASK</h2>
5325 <div class="memitem">
5326 <div class="memproto">
5327 <table class="memname">
5329 <td class="memname">#define PAGE_P_MASK   (0xFFFFFDFF)</td>
5332 </div><div class="memdoc">
5336 <a id="a46a63dfcf084d48ccf27987bab48417a" name="a46a63dfcf084d48ccf27987bab48417a"></a>
5337 <h2 class="memtitle"><span class="permalink"><a href="#a46a63dfcf084d48ccf27987bab48417a">◆ </a></span>PAGE_P_SHIFT</h2>
5339 <div class="memitem">
5340 <div class="memproto">
5341 <table class="memname">
5343 <td class="memname">#define PAGE_P_SHIFT   (9)</td>
5346 </div><div class="memdoc">
5350 <a id="ac44cd885615a54131c372abfdc2d5c66" name="ac44cd885615a54131c372abfdc2d5c66"></a>
5351 <h2 class="memtitle"><span class="permalink"><a href="#ac44cd885615a54131c372abfdc2d5c66">◆ </a></span>PAGE_S_MASK</h2>
5353 <div class="memitem">
5354 <div class="memproto">
5355 <table class="memname">
5357 <td class="memname">#define PAGE_S_MASK   (0xFFFFFBFF)</td>
5360 </div><div class="memdoc">
5364 <a id="a1d9a3ed8dfa64aba257e2273d2613bce" name="a1d9a3ed8dfa64aba257e2273d2613bce"></a>
5365 <h2 class="memtitle"><span class="permalink"><a href="#a1d9a3ed8dfa64aba257e2273d2613bce">◆ </a></span>PAGE_S_SHIFT</h2>
5367 <div class="memitem">
5368 <div class="memproto">
5369 <table class="memname">
5371 <td class="memname">#define PAGE_S_SHIFT   (10)</td>
5374 </div><div class="memdoc">
5378 <a id="a5833dc0a939f8d33299d8c8995a06589" name="a5833dc0a939f8d33299d8c8995a06589"></a>
5379 <h2 class="memtitle"><span class="permalink"><a href="#a5833dc0a939f8d33299d8c8995a06589">◆ </a></span>PAGE_TEX_SHIFT</h2>
5381 <div class="memitem">
5382 <div class="memproto">
5383 <table class="memname">
5385 <td class="memname">#define PAGE_TEX_SHIFT   (12)</td>
5388 </div><div class="memdoc">
5392 <a id="aa488ef0c274f8ae125f61129745b1629" name="aa488ef0c274f8ae125f61129745b1629"></a>
5393 <h2 class="memtitle"><span class="permalink"><a href="#aa488ef0c274f8ae125f61129745b1629">◆ </a></span>PAGE_TEXCB_MASK</h2>
5395 <div class="memitem">
5396 <div class="memproto">
5397 <table class="memname">
5399 <td class="memname">#define PAGE_TEXCB_MASK   (0xFFFF8FF3)</td>
5402 </div><div class="memdoc">
5406 <a id="a522f61b0d301d6f69c33a629e1699c7e" name="a522f61b0d301d6f69c33a629e1699c7e"></a>
5407 <h2 class="memtitle"><span class="permalink"><a href="#a522f61b0d301d6f69c33a629e1699c7e">◆ </a></span>PAGE_XN_4K_MASK</h2>
5409 <div class="memitem">
5410 <div class="memproto">
5411 <table class="memname">
5413 <td class="memname">#define PAGE_XN_4K_MASK   (0xFFFFFFFE)</td>
5416 </div><div class="memdoc">
5420 <a id="a9be26955f4a44c54008c55de61652539" name="a9be26955f4a44c54008c55de61652539"></a>
5421 <h2 class="memtitle"><span class="permalink"><a href="#a9be26955f4a44c54008c55de61652539">◆ </a></span>PAGE_XN_4K_SHIFT</h2>
5423 <div class="memitem">
5424 <div class="memproto">
5425 <table class="memname">
5427 <td class="memname">#define PAGE_XN_4K_SHIFT   (0)</td>
5430 </div><div class="memdoc">
5434 <a id="ae0445cb4d6dc78359074cbb2776e3b5c" name="ae0445cb4d6dc78359074cbb2776e3b5c"></a>
5435 <h2 class="memtitle"><span class="permalink"><a href="#ae0445cb4d6dc78359074cbb2776e3b5c">◆ </a></span>PAGE_XN_64K_MASK</h2>
5437 <div class="memitem">
5438 <div class="memproto">
5439 <table class="memname">
5441 <td class="memname">#define PAGE_XN_64K_MASK   (0xFFFF7FFF)</td>
5444 </div><div class="memdoc">
5448 <a id="ab34b65fbaaec1287daef459071c5c5c9" name="ab34b65fbaaec1287daef459071c5c5c9"></a>
5449 <h2 class="memtitle"><span class="permalink"><a href="#ab34b65fbaaec1287daef459071c5c5c9">◆ </a></span>PAGE_XN_64K_SHIFT</h2>
5451 <div class="memitem">
5452 <div class="memproto">
5453 <table class="memname">
5455 <td class="memname">#define PAGE_XN_64K_SHIFT   (15)</td>
5458 </div><div class="memdoc">
5462 <a id="ae7744f04299efcff44461d22ab774673" name="ae7744f04299efcff44461d22ab774673"></a>
5463 <h2 class="memtitle"><span class="permalink"><a href="#ae7744f04299efcff44461d22ab774673">◆ </a></span>PTIM_CONTROL_AutoReload</h2>
5465 <div class="memitem">
5466 <div class="memproto">
5467 <table class="memname">
5469 <td class="memname">#define PTIM_CONTROL_AutoReload</td>
5471 <td class="paramtype"> </td>
5472 <td class="paramname">x</td><td>)</td>
5473 <td>   (((uint32_t)(((uint32_t)(x)) << <a class="el" href="core__ca_8h.html#a063285387241f2460fdade5b32c4dc46">PTIM_CONTROL_AutoReload_Pos</a>)) & <a class="el" href="core__ca_8h.html#a22f2fb180a8e8e333469f3d185d74e95">PTIM_CONTROL_AutoReload_Msk</a>)</td>
5476 </div><div class="memdoc">
5480 <a id="a22f2fb180a8e8e333469f3d185d74e95" name="a22f2fb180a8e8e333469f3d185d74e95"></a>
5481 <h2 class="memtitle"><span class="permalink"><a href="#a22f2fb180a8e8e333469f3d185d74e95">◆ </a></span>PTIM_CONTROL_AutoReload_Msk</h2>
5483 <div class="memitem">
5484 <div class="memproto">
5485 <table class="memname">
5487 <td class="memname">#define PTIM_CONTROL_AutoReload_Msk   (0x1U << <a class="el" href="core__ca_8h.html#a063285387241f2460fdade5b32c4dc46">PTIM_CONTROL_AutoReload_Pos</a>)</td>
5490 </div><div class="memdoc">
5491 <p>PTIM CONTROL: Auto Reload Mask </p>
5495 <a id="a063285387241f2460fdade5b32c4dc46" name="a063285387241f2460fdade5b32c4dc46"></a>
5496 <h2 class="memtitle"><span class="permalink"><a href="#a063285387241f2460fdade5b32c4dc46">◆ </a></span>PTIM_CONTROL_AutoReload_Pos</h2>
5498 <div class="memitem">
5499 <div class="memproto">
5500 <table class="memname">
5502 <td class="memname">#define PTIM_CONTROL_AutoReload_Pos   1U</td>
5505 </div><div class="memdoc">
5506 <p>PTIM CONTROL: Auto Reload Position </p>
5510 <a id="ae969ab086f85072b7aaaf7fd4eabc3ff" name="ae969ab086f85072b7aaaf7fd4eabc3ff"></a>
5511 <h2 class="memtitle"><span class="permalink"><a href="#ae969ab086f85072b7aaaf7fd4eabc3ff">◆ </a></span>PTIM_CONTROL_Enable</h2>
5513 <div class="memitem">
5514 <div class="memproto">
5515 <table class="memname">
5517 <td class="memname">#define PTIM_CONTROL_Enable</td>
5519 <td class="paramtype"> </td>
5520 <td class="paramname">x</td><td>)</td>
5521 <td>   (((uint32_t)(((uint32_t)(x)) /*<< <a class="el" href="core__ca_8h.html#a6fa50338a28598914fac7b848df9dd0c">PTIM_CONTROL_Enable_Pos</a>*/)) & <a class="el" href="core__ca_8h.html#a6f4e1d90070433af2918698eddd65f49">PTIM_CONTROL_Enable_Msk</a>)</td>
5524 </div><div class="memdoc">
5528 <a id="a6f4e1d90070433af2918698eddd65f49" name="a6f4e1d90070433af2918698eddd65f49"></a>
5529 <h2 class="memtitle"><span class="permalink"><a href="#a6f4e1d90070433af2918698eddd65f49">◆ </a></span>PTIM_CONTROL_Enable_Msk</h2>
5531 <div class="memitem">
5532 <div class="memproto">
5533 <table class="memname">
5535 <td class="memname">#define PTIM_CONTROL_Enable_Msk   (0x1U /*<< <a class="el" href="core__ca_8h.html#a6fa50338a28598914fac7b848df9dd0c">PTIM_CONTROL_Enable_Pos</a>*/)</td>
5538 </div><div class="memdoc">
5539 <p>PTIM CONTROL: Enable Mask </p>
5543 <a id="a6fa50338a28598914fac7b848df9dd0c" name="a6fa50338a28598914fac7b848df9dd0c"></a>
5544 <h2 class="memtitle"><span class="permalink"><a href="#a6fa50338a28598914fac7b848df9dd0c">◆ </a></span>PTIM_CONTROL_Enable_Pos</h2>
5546 <div class="memitem">
5547 <div class="memproto">
5548 <table class="memname">
5550 <td class="memname">#define PTIM_CONTROL_Enable_Pos   0U</td>
5553 </div><div class="memdoc">
5554 <p>PTIM CONTROL: Enable Position </p>
5558 <a id="ac2adbb60bcb8d5e8318e9604cee174ee" name="ac2adbb60bcb8d5e8318e9604cee174ee"></a>
5559 <h2 class="memtitle"><span class="permalink"><a href="#ac2adbb60bcb8d5e8318e9604cee174ee">◆ </a></span>PTIM_CONTROL_IRQenable</h2>
5561 <div class="memitem">
5562 <div class="memproto">
5563 <table class="memname">
5565 <td class="memname">#define PTIM_CONTROL_IRQenable</td>
5567 <td class="paramtype"> </td>
5568 <td class="paramname">x</td><td>)</td>
5569 <td>   (((uint32_t)(((uint32_t)(x)) << <a class="el" href="core__ca_8h.html#a0a4bf058b836c21a811c6619d9dcda03">PTIM_CONTROL_IRQenable_Pos</a>)) & <a class="el" href="core__ca_8h.html#adc4ee5155209dad6bfdcc00e2cff8237">PTIM_CONTROL_IRQenable_Msk</a>)</td>
5572 </div><div class="memdoc">
5576 <a id="adc4ee5155209dad6bfdcc00e2cff8237" name="adc4ee5155209dad6bfdcc00e2cff8237"></a>
5577 <h2 class="memtitle"><span class="permalink"><a href="#adc4ee5155209dad6bfdcc00e2cff8237">◆ </a></span>PTIM_CONTROL_IRQenable_Msk</h2>
5579 <div class="memitem">
5580 <div class="memproto">
5581 <table class="memname">
5583 <td class="memname">#define PTIM_CONTROL_IRQenable_Msk   (0x1U << <a class="el" href="core__ca_8h.html#a0a4bf058b836c21a811c6619d9dcda03">PTIM_CONTROL_IRQenable_Pos</a>)</td>
5586 </div><div class="memdoc">
5587 <p>PTIM CONTROL: IRQ Enabel Mask </p>
5591 <a id="a0a4bf058b836c21a811c6619d9dcda03" name="a0a4bf058b836c21a811c6619d9dcda03"></a>
5592 <h2 class="memtitle"><span class="permalink"><a href="#a0a4bf058b836c21a811c6619d9dcda03">◆ </a></span>PTIM_CONTROL_IRQenable_Pos</h2>
5594 <div class="memitem">
5595 <div class="memproto">
5596 <table class="memname">
5598 <td class="memname">#define PTIM_CONTROL_IRQenable_Pos   2U</td>
5601 </div><div class="memdoc">
5602 <p>PTIM CONTROL: IRQ Enabel Position </p>
5606 <a id="aa2ae1a6147e67806f0efc7e5d9d1b2bb" name="aa2ae1a6147e67806f0efc7e5d9d1b2bb"></a>
5607 <h2 class="memtitle"><span class="permalink"><a href="#aa2ae1a6147e67806f0efc7e5d9d1b2bb">◆ </a></span>PTIM_CONTROL_Prescaler</h2>
5609 <div class="memitem">
5610 <div class="memproto">
5611 <table class="memname">
5613 <td class="memname">#define PTIM_CONTROL_Prescaler</td>
5615 <td class="paramtype"> </td>
5616 <td class="paramname">x</td><td>)</td>
5617 <td>   (((uint32_t)(((uint32_t)(x)) << <a class="el" href="core__ca_8h.html#a3c6fc3b64ce9dfd52988ca4b9252d49d">PTIM_CONTROL_Prescaler_Pos</a>)) & <a class="el" href="core__ca_8h.html#aa1fbcd0babcbbd47d0c0d5a914a04619">PTIM_CONTROL_Prescaler_Msk</a>)</td>
5620 </div><div class="memdoc">
5624 <a id="aa1fbcd0babcbbd47d0c0d5a914a04619" name="aa1fbcd0babcbbd47d0c0d5a914a04619"></a>
5625 <h2 class="memtitle"><span class="permalink"><a href="#aa1fbcd0babcbbd47d0c0d5a914a04619">◆ </a></span>PTIM_CONTROL_Prescaler_Msk</h2>
5627 <div class="memitem">
5628 <div class="memproto">
5629 <table class="memname">
5631 <td class="memname">#define PTIM_CONTROL_Prescaler_Msk   (0xFFU << <a class="el" href="core__ca_8h.html#a3c6fc3b64ce9dfd52988ca4b9252d49d">PTIM_CONTROL_Prescaler_Pos</a>)</td>
5634 </div><div class="memdoc">
5635 <p>PTIM CONTROL: Prescaler Mask </p>
5639 <a id="a3c6fc3b64ce9dfd52988ca4b9252d49d" name="a3c6fc3b64ce9dfd52988ca4b9252d49d"></a>
5640 <h2 class="memtitle"><span class="permalink"><a href="#a3c6fc3b64ce9dfd52988ca4b9252d49d">◆ </a></span>PTIM_CONTROL_Prescaler_Pos</h2>
5642 <div class="memitem">
5643 <div class="memproto">
5644 <table class="memname">
5646 <td class="memname">#define PTIM_CONTROL_Prescaler_Pos   8U</td>
5649 </div><div class="memdoc">
5650 <p>PTIM CONTROL: Prescaler Position </p>
5654 <a id="a354e11f2b72b0a78c1b5f97357498051" name="a354e11f2b72b0a78c1b5f97357498051"></a>
5655 <h2 class="memtitle"><span class="permalink"><a href="#a354e11f2b72b0a78c1b5f97357498051">◆ </a></span>PTIM_WCONTROL_AutoReload</h2>
5657 <div class="memitem">
5658 <div class="memproto">
5659 <table class="memname">
5661 <td class="memname">#define PTIM_WCONTROL_AutoReload</td>
5663 <td class="paramtype"> </td>
5664 <td class="paramname">x</td><td>)</td>
5665 <td>   (((uint32_t)(((uint32_t)(x)) << <a class="el" href="core__ca_8h.html#a92428db9bf62796b22fa4d03a0d44f8c">PTIM_WCONTROL_AutoReload_Pos</a>)) & <a class="el" href="core__ca_8h.html#acd877c3ae391c835308d6209991b3087">PTIM_WCONTROL_AutoReload_Msk</a>)</td>
5668 </div><div class="memdoc">
5672 <a id="acd877c3ae391c835308d6209991b3087" name="acd877c3ae391c835308d6209991b3087"></a>
5673 <h2 class="memtitle"><span class="permalink"><a href="#acd877c3ae391c835308d6209991b3087">◆ </a></span>PTIM_WCONTROL_AutoReload_Msk</h2>
5675 <div class="memitem">
5676 <div class="memproto">
5677 <table class="memname">
5679 <td class="memname">#define PTIM_WCONTROL_AutoReload_Msk   (0x1U << <a class="el" href="core__ca_8h.html#a92428db9bf62796b22fa4d03a0d44f8c">PTIM_WCONTROL_AutoReload_Pos</a>)</td>
5682 </div><div class="memdoc">
5683 <p>PTIM WCONTROL: Auto Reload Mask </p>
5687 <a id="a92428db9bf62796b22fa4d03a0d44f8c" name="a92428db9bf62796b22fa4d03a0d44f8c"></a>
5688 <h2 class="memtitle"><span class="permalink"><a href="#a92428db9bf62796b22fa4d03a0d44f8c">◆ </a></span>PTIM_WCONTROL_AutoReload_Pos</h2>
5690 <div class="memitem">
5691 <div class="memproto">
5692 <table class="memname">
5694 <td class="memname">#define PTIM_WCONTROL_AutoReload_Pos   1U</td>
5697 </div><div class="memdoc">
5698 <p>PTIM WCONTROL: Auto Reload Position </p>
5702 <a id="a6b8afdf15f4c571bc4dc8dd68d94857b" name="a6b8afdf15f4c571bc4dc8dd68d94857b"></a>
5703 <h2 class="memtitle"><span class="permalink"><a href="#a6b8afdf15f4c571bc4dc8dd68d94857b">◆ </a></span>PTIM_WCONTROL_Enable</h2>
5705 <div class="memitem">
5706 <div class="memproto">
5707 <table class="memname">
5709 <td class="memname">#define PTIM_WCONTROL_Enable</td>
5711 <td class="paramtype"> </td>
5712 <td class="paramname">x</td><td>)</td>
5713 <td>   (((uint32_t)(((uint32_t)(x)) /*<< <a class="el" href="core__ca_8h.html#a766bde345c9066ff36955a46c575287b">PTIM_WCONTROL_Enable_Pos</a>*/)) & <a class="el" href="core__ca_8h.html#a3224c76fb25151decd85acaca3e07921">PTIM_WCONTROL_Enable_Msk</a>)</td>
5716 </div><div class="memdoc">
5720 <a id="a3224c76fb25151decd85acaca3e07921" name="a3224c76fb25151decd85acaca3e07921"></a>
5721 <h2 class="memtitle"><span class="permalink"><a href="#a3224c76fb25151decd85acaca3e07921">◆ </a></span>PTIM_WCONTROL_Enable_Msk</h2>
5723 <div class="memitem">
5724 <div class="memproto">
5725 <table class="memname">
5727 <td class="memname">#define PTIM_WCONTROL_Enable_Msk   (0x1U /*<< <a class="el" href="core__ca_8h.html#a766bde345c9066ff36955a46c575287b">PTIM_WCONTROL_Enable_Pos</a>*/)</td>
5730 </div><div class="memdoc">
5731 <p>PTIM WCONTROL: Enable Mask </p>
5735 <a id="a766bde345c9066ff36955a46c575287b" name="a766bde345c9066ff36955a46c575287b"></a>
5736 <h2 class="memtitle"><span class="permalink"><a href="#a766bde345c9066ff36955a46c575287b">◆ </a></span>PTIM_WCONTROL_Enable_Pos</h2>
5738 <div class="memitem">
5739 <div class="memproto">
5740 <table class="memname">
5742 <td class="memname">#define PTIM_WCONTROL_Enable_Pos   0U</td>
5745 </div><div class="memdoc">
5746 <p>PTIM WCONTROL: Enable Position </p>
5750 <a id="aa8ce36df65589c55dbdbf86e9f82eff8" name="aa8ce36df65589c55dbdbf86e9f82eff8"></a>
5751 <h2 class="memtitle"><span class="permalink"><a href="#aa8ce36df65589c55dbdbf86e9f82eff8">◆ </a></span>PTIM_WCONTROL_IRQenable</h2>
5753 <div class="memitem">
5754 <div class="memproto">
5755 <table class="memname">
5757 <td class="memname">#define PTIM_WCONTROL_IRQenable</td>
5759 <td class="paramtype"> </td>
5760 <td class="paramname">x</td><td>)</td>
5761 <td>   (((uint32_t)(((uint32_t)(x)) << <a class="el" href="core__ca_8h.html#a6b6e80f22db74334668eb35972d00075">PTIM_WCONTROL_IRQenable_Pos</a>)) & <a class="el" href="core__ca_8h.html#af00fdab72c490423a4f7e5483a89ae05">PTIM_WCONTROL_IRQenable_Msk</a>)</td>
5764 </div><div class="memdoc">
5768 <a id="af00fdab72c490423a4f7e5483a89ae05" name="af00fdab72c490423a4f7e5483a89ae05"></a>
5769 <h2 class="memtitle"><span class="permalink"><a href="#af00fdab72c490423a4f7e5483a89ae05">◆ </a></span>PTIM_WCONTROL_IRQenable_Msk</h2>
5771 <div class="memitem">
5772 <div class="memproto">
5773 <table class="memname">
5775 <td class="memname">#define PTIM_WCONTROL_IRQenable_Msk   (0x1U << <a class="el" href="core__ca_8h.html#a6b6e80f22db74334668eb35972d00075">PTIM_WCONTROL_IRQenable_Pos</a>)</td>
5778 </div><div class="memdoc">
5779 <p>PTIM WCONTROL: IRQ Enable Mask </p>
5783 <a id="a6b6e80f22db74334668eb35972d00075" name="a6b6e80f22db74334668eb35972d00075"></a>
5784 <h2 class="memtitle"><span class="permalink"><a href="#a6b6e80f22db74334668eb35972d00075">◆ </a></span>PTIM_WCONTROL_IRQenable_Pos</h2>
5786 <div class="memitem">
5787 <div class="memproto">
5788 <table class="memname">
5790 <td class="memname">#define PTIM_WCONTROL_IRQenable_Pos   2U</td>
5793 </div><div class="memdoc">
5794 <p>PTIM WCONTROL: IRQ Enable Position </p>
5798 <a id="a0002122226f327beb2448507434119dd" name="a0002122226f327beb2448507434119dd"></a>
5799 <h2 class="memtitle"><span class="permalink"><a href="#a0002122226f327beb2448507434119dd">◆ </a></span>PTIM_WCONTROL_Mode</h2>
5801 <div class="memitem">
5802 <div class="memproto">
5803 <table class="memname">
5805 <td class="memname">#define PTIM_WCONTROL_Mode</td>
5807 <td class="paramtype"> </td>
5808 <td class="paramname">x</td><td>)</td>
5809 <td>   (((uint32_t)(((uint32_t)(x)) << <a class="el" href="core__ca_8h.html#aa520a65ee0970978cccc6f71c4d7cf40">PTIM_WCONTROL_Mode_Pos</a>)) & <a class="el" href="core__ca_8h.html#a57e0ff6fa731293061548809f136db27">PTIM_WCONTROL_Mode_Msk</a>)</td>
5812 </div><div class="memdoc">
5816 <a id="a57e0ff6fa731293061548809f136db27" name="a57e0ff6fa731293061548809f136db27"></a>
5817 <h2 class="memtitle"><span class="permalink"><a href="#a57e0ff6fa731293061548809f136db27">◆ </a></span>PTIM_WCONTROL_Mode_Msk</h2>
5819 <div class="memitem">
5820 <div class="memproto">
5821 <table class="memname">
5823 <td class="memname">#define PTIM_WCONTROL_Mode_Msk   (0x1U << <a class="el" href="core__ca_8h.html#aa520a65ee0970978cccc6f71c4d7cf40">PTIM_WCONTROL_Mode_Pos</a>)</td>
5826 </div><div class="memdoc">
5827 <p>PTIM WCONTROL: Watchdog Mode Mask </p>
5831 <a id="aa520a65ee0970978cccc6f71c4d7cf40" name="aa520a65ee0970978cccc6f71c4d7cf40"></a>
5832 <h2 class="memtitle"><span class="permalink"><a href="#aa520a65ee0970978cccc6f71c4d7cf40">◆ </a></span>PTIM_WCONTROL_Mode_Pos</h2>
5834 <div class="memitem">
5835 <div class="memproto">
5836 <table class="memname">
5838 <td class="memname">#define PTIM_WCONTROL_Mode_Pos   3U</td>
5841 </div><div class="memdoc">
5842 <p>PTIM WCONTROL: Watchdog Mode Position </p>
5846 <a id="a9de73ffcb171293679abe7e4868568cc" name="a9de73ffcb171293679abe7e4868568cc"></a>
5847 <h2 class="memtitle"><span class="permalink"><a href="#a9de73ffcb171293679abe7e4868568cc">◆ </a></span>PTIM_WCONTROL_Presacler</h2>
5849 <div class="memitem">
5850 <div class="memproto">
5851 <table class="memname">
5853 <td class="memname">#define PTIM_WCONTROL_Presacler</td>
5855 <td class="paramtype"> </td>
5856 <td class="paramname">x</td><td>)</td>
5857 <td>   (((uint32_t)(((uint32_t)(x)) << <a class="el" href="core__ca_8h.html#a699863868487b60d093aaa4acb476baf">PTIM_WCONTROL_Presacler_Pos</a>)) & <a class="el" href="core__ca_8h.html#a8517f58681a489fc2e7343740104b830">PTIM_WCONTROL_Presacler_Msk</a>)</td>
5860 </div><div class="memdoc">
5864 <a id="a8517f58681a489fc2e7343740104b830" name="a8517f58681a489fc2e7343740104b830"></a>
5865 <h2 class="memtitle"><span class="permalink"><a href="#a8517f58681a489fc2e7343740104b830">◆ </a></span>PTIM_WCONTROL_Presacler_Msk</h2>
5867 <div class="memitem">
5868 <div class="memproto">
5869 <table class="memname">
5871 <td class="memname">#define PTIM_WCONTROL_Presacler_Msk   (0xFFU << <a class="el" href="core__ca_8h.html#a699863868487b60d093aaa4acb476baf">PTIM_WCONTROL_Presacler_Pos</a>)</td>
5874 </div><div class="memdoc">
5875 <p>PTIM WCONTROL: Prescaler Mask </p>
5879 <a id="a699863868487b60d093aaa4acb476baf" name="a699863868487b60d093aaa4acb476baf"></a>
5880 <h2 class="memtitle"><span class="permalink"><a href="#a699863868487b60d093aaa4acb476baf">◆ </a></span>PTIM_WCONTROL_Presacler_Pos</h2>
5882 <div class="memitem">
5883 <div class="memproto">
5884 <table class="memname">
5886 <td class="memname">#define PTIM_WCONTROL_Presacler_Pos   8U</td>
5889 </div><div class="memdoc">
5890 <p>PTIM WCONTROL: Prescaler Position </p>
5894 <a id="a30b4ad11d0b222ba1c6138a245dd0a2d" name="a30b4ad11d0b222ba1c6138a245dd0a2d"></a>
5895 <h2 class="memtitle"><span class="permalink"><a href="#a30b4ad11d0b222ba1c6138a245dd0a2d">◆ </a></span>PTIM_WISR_EventFlag</h2>
5897 <div class="memitem">
5898 <div class="memproto">
5899 <table class="memname">
5901 <td class="memname">#define PTIM_WISR_EventFlag</td>
5903 <td class="paramtype"> </td>
5904 <td class="paramname">x</td><td>)</td>
5905 <td>   (((uint32_t)(((uint32_t)(x)) /*<< <a class="el" href="core__ca_8h.html#ab0090b3d580850c9ec8583ad2083de2a">PTIM_WISR_EventFlag_Pos</a>*/)) & <a class="el" href="core__ca_8h.html#af7682c18d2684e3ef0b7a79a05800f62">PTIM_WISR_EventFlag_Msk</a>)</td>
5908 </div><div class="memdoc">
5912 <a id="af7682c18d2684e3ef0b7a79a05800f62" name="af7682c18d2684e3ef0b7a79a05800f62"></a>
5913 <h2 class="memtitle"><span class="permalink"><a href="#af7682c18d2684e3ef0b7a79a05800f62">◆ </a></span>PTIM_WISR_EventFlag_Msk</h2>
5915 <div class="memitem">
5916 <div class="memproto">
5917 <table class="memname">
5919 <td class="memname">#define PTIM_WISR_EventFlag_Msk   (0x1U /*<< <a class="el" href="core__ca_8h.html#ab0090b3d580850c9ec8583ad2083de2a">PTIM_WISR_EventFlag_Pos</a>*/)</td>
5922 </div><div class="memdoc">
5923 <p>PTIM WISR: Event Flag Mask </p>
5927 <a id="ab0090b3d580850c9ec8583ad2083de2a" name="ab0090b3d580850c9ec8583ad2083de2a"></a>
5928 <h2 class="memtitle"><span class="permalink"><a href="#ab0090b3d580850c9ec8583ad2083de2a">◆ </a></span>PTIM_WISR_EventFlag_Pos</h2>
5930 <div class="memitem">
5931 <div class="memproto">
5932 <table class="memname">
5934 <td class="memname">#define PTIM_WISR_EventFlag_Pos   0U</td>
5937 </div><div class="memdoc">
5938 <p>PTIM WISR: Event Flag Position </p>
5942 <a id="a0d426f711743bb29171559c763d2b178" name="a0d426f711743bb29171559c763d2b178"></a>
5943 <h2 class="memtitle"><span class="permalink"><a href="#a0d426f711743bb29171559c763d2b178">◆ </a></span>PTIM_WRESET_ResetFlag</h2>
5945 <div class="memitem">
5946 <div class="memproto">
5947 <table class="memname">
5949 <td class="memname">#define PTIM_WRESET_ResetFlag</td>
5951 <td class="paramtype"> </td>
5952 <td class="paramname">x</td><td>)</td>
5953 <td>   (((uint32_t)(((uint32_t)(x)) /*<< <a class="el" href="core__ca_8h.html#ab14433a719470079291e0e85afd3d4ce">PTIM_WRESET_ResetFlag_Pos</a>*/)) & <a class="el" href="core__ca_8h.html#a09ee8cf35de561687d0d2d5444557264">PTIM_WRESET_ResetFlag_Msk</a>)</td>
5956 </div><div class="memdoc">
5960 <a id="a09ee8cf35de561687d0d2d5444557264" name="a09ee8cf35de561687d0d2d5444557264"></a>
5961 <h2 class="memtitle"><span class="permalink"><a href="#a09ee8cf35de561687d0d2d5444557264">◆ </a></span>PTIM_WRESET_ResetFlag_Msk</h2>
5963 <div class="memitem">
5964 <div class="memproto">
5965 <table class="memname">
5967 <td class="memname">#define PTIM_WRESET_ResetFlag_Msk   (0x1U /*<< <a class="el" href="core__ca_8h.html#ab14433a719470079291e0e85afd3d4ce">PTIM_WRESET_ResetFlag_Pos</a>*/)</td>
5970 </div><div class="memdoc">
5971 <p>PTIM WRESET: Reset Flag Mask </p>
5975 <a id="ab14433a719470079291e0e85afd3d4ce" name="ab14433a719470079291e0e85afd3d4ce"></a>
5976 <h2 class="memtitle"><span class="permalink"><a href="#ab14433a719470079291e0e85afd3d4ce">◆ </a></span>PTIM_WRESET_ResetFlag_Pos</h2>
5978 <div class="memitem">
5979 <div class="memproto">
5980 <table class="memname">
5982 <td class="memname">#define PTIM_WRESET_ResetFlag_Pos   0U</td>
5985 </div><div class="memdoc">
5986 <p>PTIM WRESET: Reset Flag Position </p>
5990 <a id="af7f66fda711fd46e157dbb6c1af88e04" name="af7f66fda711fd46e157dbb6c1af88e04"></a>
5991 <h2 class="memtitle"><span class="permalink"><a href="#af7f66fda711fd46e157dbb6c1af88e04">◆ </a></span>RESERVED</h2>
5993 <div class="memitem">
5994 <div class="memproto">
5995 <table class="memname">
5997 <td class="memname">#define RESERVED</td>
5999 <td class="paramtype"> </td>
6000 <td class="paramname">N, </td>
6003 <td class="paramkey"></td>
6005 <td class="paramtype"> </td>
6006 <td class="paramname">T </td>
6011 <td></td><td>   T RESERVED##N;</td>
6014 </div><div class="memdoc">
6018 <a id="a1b8b0d00bfc7cbeed67b82db26d98195" name="a1b8b0d00bfc7cbeed67b82db26d98195"></a>
6019 <h2 class="memtitle"><span class="permalink"><a href="#a1b8b0d00bfc7cbeed67b82db26d98195">◆ </a></span>SECTION_AP2_SHIFT</h2>
6021 <div class="memitem">
6022 <div class="memproto">
6023 <table class="memname">
6025 <td class="memname">#define SECTION_AP2_SHIFT   (15)</td>
6028 </div><div class="memdoc">
6032 <a id="a725efc96ea9aa940fefcf013bce6ca8c" name="a725efc96ea9aa940fefcf013bce6ca8c"></a>
6033 <h2 class="memtitle"><span class="permalink"><a href="#a725efc96ea9aa940fefcf013bce6ca8c">◆ </a></span>SECTION_AP_MASK</h2>
6035 <div class="memitem">
6036 <div class="memproto">
6037 <table class="memname">
6039 <td class="memname">#define SECTION_AP_MASK   (0xFFFF73FF)</td>
6042 </div><div class="memdoc">
6046 <a id="a274fa608581b227182ce92adec4597b5" name="a274fa608581b227182ce92adec4597b5"></a>
6047 <h2 class="memtitle"><span class="permalink"><a href="#a274fa608581b227182ce92adec4597b5">◆ </a></span>SECTION_AP_SHIFT</h2>
6049 <div class="memitem">
6050 <div class="memproto">
6051 <table class="memname">
6053 <td class="memname">#define SECTION_AP_SHIFT   (10)</td>
6056 </div><div class="memdoc">
6060 <a id="a90a30c02512cbea24791212af9f2cd9f" name="a90a30c02512cbea24791212af9f2cd9f"></a>
6061 <h2 class="memtitle"><span class="permalink"><a href="#a90a30c02512cbea24791212af9f2cd9f">◆ </a></span>SECTION_DOMAIN_MASK</h2>
6063 <div class="memitem">
6064 <div class="memproto">
6065 <table class="memname">
6067 <td class="memname">#define SECTION_DOMAIN_MASK   (0xFFFFFE1F)</td>
6070 </div><div class="memdoc">
6074 <a id="a70cc38b984789323feecd97033a66757" name="a70cc38b984789323feecd97033a66757"></a>
6075 <h2 class="memtitle"><span class="permalink"><a href="#a70cc38b984789323feecd97033a66757">◆ </a></span>SECTION_DOMAIN_SHIFT</h2>
6077 <div class="memitem">
6078 <div class="memproto">
6079 <table class="memname">
6081 <td class="memname">#define SECTION_DOMAIN_SHIFT   (5)</td>
6084 </div><div class="memdoc">
6088 <a id="a16f225cca51a80c5cf1c9c002cfd2dba" name="a16f225cca51a80c5cf1c9c002cfd2dba"></a>
6089 <h2 class="memtitle"><span class="permalink"><a href="#a16f225cca51a80c5cf1c9c002cfd2dba">◆ </a></span>SECTION_MASK</h2>
6091 <div class="memitem">
6092 <div class="memproto">
6093 <table class="memname">
6095 <td class="memname">#define SECTION_MASK   (0xFFFFFFFC)</td>
6098 </div><div class="memdoc">
6102 <a id="a01ceacdb3888d7cddcfeccfea9eb3658" name="a01ceacdb3888d7cddcfeccfea9eb3658"></a>
6103 <h2 class="memtitle"><span class="permalink"><a href="#a01ceacdb3888d7cddcfeccfea9eb3658">◆ </a></span>SECTION_NG_MASK</h2>
6105 <div class="memitem">
6106 <div class="memproto">
6107 <table class="memname">
6109 <td class="memname">#define SECTION_NG_MASK   (0xFFFDFFFF)</td>
6112 </div><div class="memdoc">
6116 <a id="a7af8adbf033d0a5c7b0889dd085041d1" name="a7af8adbf033d0a5c7b0889dd085041d1"></a>
6117 <h2 class="memtitle"><span class="permalink"><a href="#a7af8adbf033d0a5c7b0889dd085041d1">◆ </a></span>SECTION_NG_SHIFT</h2>
6119 <div class="memitem">
6120 <div class="memproto">
6121 <table class="memname">
6123 <td class="memname">#define SECTION_NG_SHIFT   (17)</td>
6126 </div><div class="memdoc">
6130 <a id="a470b88645153aad94b09485f3108c641" name="a470b88645153aad94b09485f3108c641"></a>
6131 <h2 class="memtitle"><span class="permalink"><a href="#a470b88645153aad94b09485f3108c641">◆ </a></span>section_normal_nc</h2>
6133 <div class="memitem">
6134 <div class="memproto">
6135 <table class="memname">
6137 <td class="memname">#define section_normal_nc</td>
6139 <td class="paramtype"> </td>
6140 <td class="paramname">descriptor_l1, </td>
6143 <td class="paramkey"></td>
6145 <td class="paramtype"> </td>
6146 <td class="paramname">region </td>
6154 </div><div class="memdoc">
6158 <a id="a057533871fa1af6db7a27b39d976ac95" name="a057533871fa1af6db7a27b39d976ac95"></a>
6159 <h2 class="memtitle"><span class="permalink"><a href="#a057533871fa1af6db7a27b39d976ac95">◆ </a></span>SECTION_NS_MASK</h2>
6161 <div class="memitem">
6162 <div class="memproto">
6163 <table class="memname">
6165 <td class="memname">#define SECTION_NS_MASK   (0xFFF7FFFF)</td>
6168 </div><div class="memdoc">
6172 <a id="a502d55a107c909e15be282d8fbe4a8ce" name="a502d55a107c909e15be282d8fbe4a8ce"></a>
6173 <h2 class="memtitle"><span class="permalink"><a href="#a502d55a107c909e15be282d8fbe4a8ce">◆ </a></span>SECTION_NS_SHIFT</h2>
6175 <div class="memitem">
6176 <div class="memproto">
6177 <table class="memname">
6179 <td class="memname">#define SECTION_NS_SHIFT   (19)</td>
6182 </div><div class="memdoc">
6186 <a id="ad32d146d84a9d7f964f28f1dadc98bcb" name="ad32d146d84a9d7f964f28f1dadc98bcb"></a>
6187 <h2 class="memtitle"><span class="permalink"><a href="#ad32d146d84a9d7f964f28f1dadc98bcb">◆ </a></span>SECTION_P_MASK</h2>
6189 <div class="memitem">
6190 <div class="memproto">
6191 <table class="memname">
6193 <td class="memname">#define SECTION_P_MASK   (0xFFFFFDFF)</td>
6196 </div><div class="memdoc">
6200 <a id="a8f27fa21cb70abad114374f33a562988" name="a8f27fa21cb70abad114374f33a562988"></a>
6201 <h2 class="memtitle"><span class="permalink"><a href="#a8f27fa21cb70abad114374f33a562988">◆ </a></span>SECTION_P_SHIFT</h2>
6203 <div class="memitem">
6204 <div class="memproto">
6205 <table class="memname">
6207 <td class="memname">#define SECTION_P_SHIFT   (9)</td>
6210 </div><div class="memdoc">
6214 <a id="a42d3645aad501af4ef447186c01685b7" name="a42d3645aad501af4ef447186c01685b7"></a>
6215 <h2 class="memtitle"><span class="permalink"><a href="#a42d3645aad501af4ef447186c01685b7">◆ </a></span>SECTION_S_MASK</h2>
6217 <div class="memitem">
6218 <div class="memproto">
6219 <table class="memname">
6221 <td class="memname">#define SECTION_S_MASK   (0xFFFEFFFF)</td>
6224 </div><div class="memdoc">
6228 <a id="a83a5fc538dad79161b122fb164d630fe" name="a83a5fc538dad79161b122fb164d630fe"></a>
6229 <h2 class="memtitle"><span class="permalink"><a href="#a83a5fc538dad79161b122fb164d630fe">◆ </a></span>SECTION_S_SHIFT</h2>
6231 <div class="memitem">
6232 <div class="memproto">
6233 <table class="memname">
6235 <td class="memname">#define SECTION_S_SHIFT   (16)</td>
6238 </div><div class="memdoc">
6242 <a id="ad84432cb37ae093f7609f8f29f42c1f4" name="ad84432cb37ae093f7609f8f29f42c1f4"></a>
6243 <h2 class="memtitle"><span class="permalink"><a href="#ad84432cb37ae093f7609f8f29f42c1f4">◆ </a></span>SECTION_TEX0_SHIFT</h2>
6245 <div class="memitem">
6246 <div class="memproto">
6247 <table class="memname">
6249 <td class="memname">#define SECTION_TEX0_SHIFT   (12)</td>
6252 </div><div class="memdoc">
6256 <a id="a531cafc5eca8ade67a6fb83b35f8520e" name="a531cafc5eca8ade67a6fb83b35f8520e"></a>
6257 <h2 class="memtitle"><span class="permalink"><a href="#a531cafc5eca8ade67a6fb83b35f8520e">◆ </a></span>SECTION_TEX1_SHIFT</h2>
6259 <div class="memitem">
6260 <div class="memproto">
6261 <table class="memname">
6263 <td class="memname">#define SECTION_TEX1_SHIFT   (13)</td>
6266 </div><div class="memdoc">
6270 <a id="a8a6d854746a9c0049f9a91188092a55f" name="a8a6d854746a9c0049f9a91188092a55f"></a>
6271 <h2 class="memtitle"><span class="permalink"><a href="#a8a6d854746a9c0049f9a91188092a55f">◆ </a></span>SECTION_TEX2_SHIFT</h2>
6273 <div class="memitem">
6274 <div class="memproto">
6275 <table class="memname">
6277 <td class="memname">#define SECTION_TEX2_SHIFT   (14)</td>
6280 </div><div class="memdoc">
6284 <a id="a3052ba3d97ad157189a6c6fce15b1b6a" name="a3052ba3d97ad157189a6c6fce15b1b6a"></a>
6285 <h2 class="memtitle"><span class="permalink"><a href="#a3052ba3d97ad157189a6c6fce15b1b6a">◆ </a></span>SECTION_TEXCB_MASK</h2>
6287 <div class="memitem">
6288 <div class="memproto">
6289 <table class="memname">
6291 <td class="memname">#define SECTION_TEXCB_MASK   (0xFFFF8FF3)</td>
6294 </div><div class="memdoc">
6298 <a id="a83cb551c9fa708e33082c682be614334" name="a83cb551c9fa708e33082c682be614334"></a>
6299 <h2 class="memtitle"><span class="permalink"><a href="#a83cb551c9fa708e33082c682be614334">◆ </a></span>SECTION_XN_MASK</h2>
6301 <div class="memitem">
6302 <div class="memproto">
6303 <table class="memname">
6305 <td class="memname">#define SECTION_XN_MASK   (0xFFFFFFEF)</td>
6308 </div><div class="memdoc">
6312 <a id="a6cdc2db0ca695fd1191305a13e66c0a7" name="a6cdc2db0ca695fd1191305a13e66c0a7"></a>
6313 <h2 class="memtitle"><span class="permalink"><a href="#a6cdc2db0ca695fd1191305a13e66c0a7">◆ </a></span>SECTION_XN_SHIFT</h2>
6315 <div class="memitem">
6316 <div class="memproto">
6317 <table class="memname">
6319 <td class="memname">#define SECTION_XN_SHIFT   (4)</td>
6322 </div><div class="memdoc">
6326 <h2 class="groupheader">Function Documentation</h2>
6327 <a id="a5ace5c651cf18aaa7659e1fbe6e77988" name="a5ace5c651cf18aaa7659e1fbe6e77988"></a>
6328 <h2 class="memtitle"><span class="permalink"><a href="#a5ace5c651cf18aaa7659e1fbe6e77988">◆ </a></span>__L1C_MaintainDCacheSetWay()</h2>
6330 <div class="memitem">
6331 <div class="memproto">
6332 <table class="memname">
6334 <td class="memname"><a class="el" href="group__comp__cntrl__gr.html#gab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void __L1C_MaintainDCacheSetWay </td>
6336 <td class="paramtype">uint32_t </td>
6337 <td class="paramname"><em>level</em>, </td>
6340 <td class="paramkey"></td>
6342 <td class="paramtype">uint32_t </td>
6343 <td class="paramname"><em>maint</em> </td>
6351 </div><div class="memdoc">
6353 <p>Apply cache maintenance to given cache level. </p>
6354 <dl class="params"><dt>Parameters</dt><dd>
6355 <table class="params">
6356 <tr><td class="paramdir">[in]</td><td class="paramname">level</td><td>cache level to be maintained </td></tr>
6357 <tr><td class="paramdir">[in]</td><td class="paramname">maint</td><td>0 - invalidate, 1 - clean, otherwise - invalidate and clean </td></tr>
6364 <a id="a35988a42567ca868bffd0b6171021ecb" name="a35988a42567ca868bffd0b6171021ecb"></a>
6365 <h2 class="memtitle"><span class="permalink"><a href="#a35988a42567ca868bffd0b6171021ecb">◆ </a></span>__log2_up()</h2>
6367 <div class="memitem">
6368 <div class="memproto">
6369 <table class="memname">
6371 <td class="memname"><a class="el" href="group__comp__cntrl__gr.html#gab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> uint8_t __log2_up </td>
6373 <td class="paramtype">uint32_t </td>
6374 <td class="paramname"><em>n</em></td><td>)</td>
6378 </div><div class="memdoc">
6380 <p>Calculate log2 rounded up. </p>
6382 <li>log(0) => 0</li>
6383 <li>log(1) => 0</li>
6384 <li>log(2) => 1</li>
6385 <li>log(3) => 2</li>
6386 <li>log(4) => 2</li>
6387 <li>log(5) => 3 : :</li>
6388 <li>log(16) => 4</li>
6389 <li>log(32) => 5 : : <dl class="params"><dt>Parameters</dt><dd>
6390 <table class="params">
6391 <tr><td class="paramdir">[in]</td><td class="paramname">n</td><td>input value parameter </td></tr>
6395 <dl class="section return"><dt>Returns</dt><dd>log2(n) </dd></dl>
6401 <a id="a43cfac7327b49e2a89d63abc99b6b06a" name="a43cfac7327b49e2a89d63abc99b6b06a"></a>
6402 <h2 class="memtitle"><span class="permalink"><a href="#a43cfac7327b49e2a89d63abc99b6b06a">◆ </a></span>GIC_GetConfiguration()</h2>
6404 <div class="memitem">
6405 <div class="memproto">
6406 <table class="memname">
6408 <td class="memname">__STATIC_INLINE uint32_t GIC_GetConfiguration </td>
6410 <td class="paramtype"><a class="el" href="group__irq__ctrl__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> </td>
6411 <td class="paramname"><em>IRQn</em></td><td>)</td>
6415 </div><div class="memdoc">
6417 <p>Get the interrupt configuration from the GIC's ICFGR register. </p>
6418 <dl class="params"><dt>Parameters</dt><dd>
6419 <table class="params">
6420 <tr><td class="paramdir">[in]</td><td class="paramname">IRQn</td><td>Interrupt to acquire the configuration for. </td></tr>
6424 <dl class="section return"><dt>Returns</dt><dd>Int_config field value. Bit 0: Reserved (0 - N-N model, 1 - 1-N model for some GIC before v1) Bit 1: 0 - level sensitive, 1 - edge triggered </dd></dl>
6428 <a id="abcd7d576ea634b1a708db9fda95d09df" name="abcd7d576ea634b1a708db9fda95d09df"></a>
6429 <h2 class="memtitle"><span class="permalink"><a href="#abcd7d576ea634b1a708db9fda95d09df">◆ </a></span>GIC_GetEnableIRQ()</h2>
6431 <div class="memitem">
6432 <div class="memproto">
6433 <table class="memname">
6435 <td class="memname">__STATIC_INLINE uint32_t GIC_GetEnableIRQ </td>
6437 <td class="paramtype"><a class="el" href="group__irq__ctrl__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> </td>
6438 <td class="paramname"><em>IRQn</em></td><td>)</td>
6442 </div><div class="memdoc">
6444 <p>Get interrupt enable status using GIC's ISENABLER register. </p>
6445 <dl class="params"><dt>Parameters</dt><dd>
6446 <table class="params">
6447 <tr><td class="paramdir">[in]</td><td class="paramname">IRQn</td><td>The interrupt to be queried. </td></tr>
6451 <dl class="section return"><dt>Returns</dt><dd>0 - interrupt is not enabled, 1 - interrupt is enabled. </dd></dl>
6455 <a id="ae161d7a866cb61f92b808ae98fa7c812" name="ae161d7a866cb61f92b808ae98fa7c812"></a>
6456 <h2 class="memtitle"><span class="permalink"><a href="#ae161d7a866cb61f92b808ae98fa7c812">◆ </a></span>GIC_GetGroup()</h2>
6458 <div class="memitem">
6459 <div class="memproto">
6460 <table class="memname">
6462 <td class="memname">__STATIC_INLINE uint32_t GIC_GetGroup </td>
6464 <td class="paramtype"><a class="el" href="group__irq__ctrl__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> </td>
6465 <td class="paramname"><em>IRQn</em></td><td>)</td>
6469 </div><div class="memdoc">
6471 <p>Get the interrupt group from the GIC's IGROUPR register. </p>
6472 <dl class="params"><dt>Parameters</dt><dd>
6473 <table class="params">
6474 <tr><td class="paramdir">[in]</td><td class="paramname">IRQn</td><td>The interrupt to be queried. </td></tr>
6478 <dl class="section return"><dt>Returns</dt><dd>0 - Group 0, 1 - Group 1 </dd></dl>
6482 <a id="ab726a01df6ee9a480cc73910a06ddfb7" name="ab726a01df6ee9a480cc73910a06ddfb7"></a>
6483 <h2 class="memtitle"><span class="permalink"><a href="#ab726a01df6ee9a480cc73910a06ddfb7">◆ </a></span>GIC_GetPendingIRQ()</h2>
6485 <div class="memitem">
6486 <div class="memproto">
6487 <table class="memname">
6489 <td class="memname">__STATIC_INLINE uint32_t GIC_GetPendingIRQ </td>
6491 <td class="paramtype"><a class="el" href="group__irq__ctrl__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> </td>
6492 <td class="paramname"><em>IRQn</em></td><td>)</td>
6496 </div><div class="memdoc">
6498 <p>Get interrupt pending status from GIC's ISPENDR register. </p>
6499 <dl class="params"><dt>Parameters</dt><dd>
6500 <table class="params">
6501 <tr><td class="paramdir">[in]</td><td class="paramname">IRQn</td><td>The interrupt to be queried. </td></tr>
6505 <dl class="section return"><dt>Returns</dt><dd>0 - interrupt is not pending, 1 - interrupt is pendig. </dd></dl>
6509 <a id="a5dffcd04b18d2c3ee5a410e185ce5108" name="a5dffcd04b18d2c3ee5a410e185ce5108"></a>
6510 <h2 class="memtitle"><span class="permalink"><a href="#a5dffcd04b18d2c3ee5a410e185ce5108">◆ </a></span>GIC_SetConfiguration()</h2>
6512 <div class="memitem">
6513 <div class="memproto">
6514 <table class="memname">
6516 <td class="memname">__STATIC_INLINE void GIC_SetConfiguration </td>
6518 <td class="paramtype"><a class="el" href="group__irq__ctrl__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> </td>
6519 <td class="paramname"><em>IRQn</em>, </td>
6522 <td class="paramkey"></td>
6524 <td class="paramtype">uint32_t </td>
6525 <td class="paramname"><em>int_config</em> </td>
6533 </div><div class="memdoc">
6535 <p>Sets the interrupt configuration using GIC's ICFGR register. </p>
6536 <dl class="params"><dt>Parameters</dt><dd>
6537 <table class="params">
6538 <tr><td class="paramdir">[in]</td><td class="paramname">IRQn</td><td>The interrupt to be configured. </td></tr>
6539 <tr><td class="paramdir">[in]</td><td class="paramname">int_config</td><td>Int_config field value. Bit 0: Reserved (0 - N-N model, 1 - 1-N model for some GIC before v1) Bit 1: 0 - level sensitive, 1 - edge triggered </td></tr>
6546 <a id="ab875d63dc51a75149802945bb00e2695" name="ab875d63dc51a75149802945bb00e2695"></a>
6547 <h2 class="memtitle"><span class="permalink"><a href="#ab875d63dc51a75149802945bb00e2695">◆ </a></span>GIC_SetGroup()</h2>
6549 <div class="memitem">
6550 <div class="memproto">
6551 <table class="memname">
6553 <td class="memname">__STATIC_INLINE void GIC_SetGroup </td>
6555 <td class="paramtype"><a class="el" href="group__irq__ctrl__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> </td>
6556 <td class="paramname"><em>IRQn</em>, </td>
6559 <td class="paramkey"></td>
6561 <td class="paramtype">uint32_t </td>
6562 <td class="paramname"><em>group</em> </td>
6570 </div><div class="memdoc">
6572 <p>Set the interrupt group from the GIC's IGROUPR register. </p>
6573 <dl class="params"><dt>Parameters</dt><dd>
6574 <table class="params">
6575 <tr><td class="paramdir">[in]</td><td class="paramname">IRQn</td><td>The interrupt to be queried. </td></tr>
6576 <tr><td class="paramdir">[in]</td><td class="paramname">group</td><td>Interrupt group number: 0 - Group 0, 1 - Group 1 </td></tr>
6583 <a id="a703d60af8047cc0d56b74d6814e375c5" name="a703d60af8047cc0d56b74d6814e375c5"></a>
6584 <h2 class="memtitle"><span class="permalink"><a href="#a703d60af8047cc0d56b74d6814e375c5">◆ </a></span>L1C_InvalidateICacheMVA()</h2>
6586 <div class="memitem">
6587 <div class="memproto">
6588 <table class="memname">
6590 <td class="memname"><a class="el" href="group__comp__cntrl__gr.html#gab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void L1C_InvalidateICacheMVA </td>
6592 <td class="paramtype">void * </td>
6593 <td class="paramname"><em>va</em></td><td>)</td>
6597 </div><div class="memdoc">
6599 <p>Clean instruction cache line by address. </p>
6600 <dl class="params"><dt>Parameters</dt><dd>
6601 <table class="params">
6602 <tr><td class="paramdir">[in]</td><td class="paramname">va</td><td>Pointer to instructions to clear the cache for. </td></tr>
6609 <a id="a2c3f9f942e8a08630562f35802dbe942" name="a2c3f9f942e8a08630562f35802dbe942"></a>
6610 <h2 class="memtitle"><span class="permalink"><a href="#a2c3f9f942e8a08630562f35802dbe942">◆ </a></span>PTIM_GetEventFlag()</h2>
6612 <div class="memitem">
6613 <div class="memproto">
6614 <table class="memname">
6616 <td class="memname">__STATIC_INLINE uint32_t PTIM_GetEventFlag </td>
6618 <td class="paramtype">void </td>
6619 <td class="paramname"></td><td>)</td>
6623 </div><div class="memdoc">
6624 <p>ref <a class="el" href="structTimer__Type.html#a91845c88231f4f337be2810d73bc79e4" title="Offset: 0x008 (R/W) Private Timer Control Register.">Timer_Type::CONTROL</a> Get the event flag in timers ISR register. </p><dl class="section return"><dt>Returns</dt><dd>0 - flag is not set, 1- flag is set </dd></dl>
6628 <a id="a323bf405e32846a7e57344935e51de66" name="a323bf405e32846a7e57344935e51de66"></a>
6629 <h2 class="memtitle"><span class="permalink"><a href="#a323bf405e32846a7e57344935e51de66">◆ </a></span>PTIM_SetCurrentValue()</h2>
6631 <div class="memitem">
6632 <div class="memproto">
6633 <table class="memname">
6635 <td class="memname">__STATIC_INLINE void PTIM_SetCurrentValue </td>
6637 <td class="paramtype">uint32_t </td>
6638 <td class="paramname"><em>value</em></td><td>)</td>
6642 </div><div class="memdoc">
6644 <p>Set current counter value from its COUNTER register. </p>
6648 <a id="af7e103fe79be50a7f314cdcac33612ef" name="af7e103fe79be50a7f314cdcac33612ef"></a>
6649 <h2 class="memtitle"><span class="permalink"><a href="#af7e103fe79be50a7f314cdcac33612ef">◆ </a></span>VL1_GetControl()</h2>
6651 <div class="memitem">
6652 <div class="memproto">
6653 <table class="memname">
6655 <td class="memname">__STATIC_INLINE uint32_t VL1_GetControl </td>
6657 <td class="paramtype">void </td>
6658 <td class="paramname"></td><td>)</td>
6662 </div><div class="memdoc">
6664 <p>Get the virtual timer control value. </p>
6665 <dl class="section return"><dt>Returns</dt><dd>Virtual timer control value. </dd></dl>
6669 <a id="af3ebcde97e7b5d2096516b06f4ab70be" name="af3ebcde97e7b5d2096516b06f4ab70be"></a>
6670 <h2 class="memtitle"><span class="permalink"><a href="#af3ebcde97e7b5d2096516b06f4ab70be">◆ </a></span>VL1_GetCurrentCountValue()</h2>
6672 <div class="memitem">
6673 <div class="memproto">
6674 <table class="memname">
6676 <td class="memname">__STATIC_INLINE uint64_t VL1_GetCurrentCountValue </td>
6678 <td class="paramtype">void </td>
6679 <td class="paramname"></td><td>)</td>
6683 </div><div class="memdoc">
6685 <p>Get the current virtual count value. </p>
6686 <dl class="section return"><dt>Returns</dt><dd>Current virtual count value. </dd></dl>
6690 <a id="a6eb9e1aae071d51af457899a6ff2c7b6" name="a6eb9e1aae071d51af457899a6ff2c7b6"></a>
6691 <h2 class="memtitle"><span class="permalink"><a href="#a6eb9e1aae071d51af457899a6ff2c7b6">◆ </a></span>VL1_GetCurrentTimerValue()</h2>
6693 <div class="memitem">
6694 <div class="memproto">
6695 <table class="memname">
6697 <td class="memname">__STATIC_INLINE uint32_t VL1_GetCurrentTimerValue </td>
6699 <td class="paramtype">void </td>
6700 <td class="paramname"></td><td>)</td>
6704 </div><div class="memdoc">
6706 <p>Get the current virtual timer value. </p>
6707 <dl class="section return"><dt>Returns</dt><dd>Current virtual timer value. </dd></dl>
6711 <a id="aa317cc419b7ed37b2e6e86d23152caeb" name="aa317cc419b7ed37b2e6e86d23152caeb"></a>
6712 <h2 class="memtitle"><span class="permalink"><a href="#aa317cc419b7ed37b2e6e86d23152caeb">◆ </a></span>VL1_GetTimerCompareValue()</h2>
6714 <div class="memitem">
6715 <div class="memproto">
6716 <table class="memname">
6718 <td class="memname">__STATIC_INLINE uint64_t VL1_GetTimerCompareValue </td>
6720 <td class="paramtype">void </td>
6721 <td class="paramname"></td><td>)</td>
6725 </div><div class="memdoc">
6727 <p>Get the virtual timer compare value. </p>
6728 <dl class="section return"><dt>Returns</dt><dd>Virtual timer compare value. </dd></dl>
6732 <a id="ae1fa0c37d9bea7d4a2d039be754d1676" name="ae1fa0c37d9bea7d4a2d039be754d1676"></a>
6733 <h2 class="memtitle"><span class="permalink"><a href="#ae1fa0c37d9bea7d4a2d039be754d1676">◆ </a></span>VL1_SetControl()</h2>
6735 <div class="memitem">
6736 <div class="memproto">
6737 <table class="memname">
6739 <td class="memname">__STATIC_INLINE void VL1_SetControl </td>
6741 <td class="paramtype">uint32_t </td>
6742 <td class="paramname"><em>value</em></td><td>)</td>
6746 </div><div class="memdoc">
6748 <p>Configure the virtual timer by setting the control value. </p>
6749 <dl class="params"><dt>Parameters</dt><dd>
6750 <table class="params">
6751 <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>New virtual timer control value. </td></tr>
6758 <a id="aead4ebf7c19a2edb6643a88a948015b9" name="aead4ebf7c19a2edb6643a88a948015b9"></a>
6759 <h2 class="memtitle"><span class="permalink"><a href="#aead4ebf7c19a2edb6643a88a948015b9">◆ </a></span>VL1_SetCurrentTimerValue()</h2>
6761 <div class="memitem">
6762 <div class="memproto">
6763 <table class="memname">
6765 <td class="memname">__STATIC_INLINE void VL1_SetCurrentTimerValue </td>
6767 <td class="paramtype">uint32_t </td>
6768 <td class="paramname"><em>value</em></td><td>)</td>
6772 </div><div class="memdoc">
6774 <p>Virtual Timer Control register. </p>
6775 <p>Sets the reset value of the virtual timer. </p><dl class="params"><dt>Parameters</dt><dd>
6776 <table class="params">
6777 <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>The value the virtual timer is loaded with. </td></tr>
6784 <a id="a85248310b22171e66951267124f2ff85" name="a85248310b22171e66951267124f2ff85"></a>
6785 <h2 class="memtitle"><span class="permalink"><a href="#a85248310b22171e66951267124f2ff85">◆ </a></span>VL1_SetTimerCompareValue()</h2>
6787 <div class="memitem">
6788 <div class="memproto">
6789 <table class="memname">
6791 <td class="memname">__STATIC_INLINE void VL1_SetTimerCompareValue </td>
6793 <td class="paramtype">uint64_t </td>
6794 <td class="paramname"><em>value</em></td><td>)</td>
6798 </div><div class="memdoc">
6800 <p>Set the virtual timer compare value. </p>
6801 <dl class="params"><dt>Parameters</dt><dd>
6802 <table class="params">
6803 <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>New virtual timer compare value. </td></tr>
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