begriffs open source - cmsis/blob - CMSIS/Documentation/Core/html/partition_h_pg.html

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 110   <div class="headertitle">
 111 <div class="title">System Partition Header File partition_&lt;device&gt;.h </div>  </div>
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 113 <div class="contents">
 114 <div class="textblock"><p>The <a class="el" href="partition_h_pg.html">System Partition Header File partition_&lt;device&gt;.h</a> contains the initial setup of the TrustZone hardware in an ARMv8-M system. The function <a class="el" href="group__sau__trustzone__functions.html#ga6093bc5939ea8924fbcfdffb8f0553f1">TZ_SAU_Setup</a> is call from <a class="el" href="group__system__init__gr.html#ga93f514700ccf00d08dbdcff7f1224eb2">SystemInit</a> and uses the settings in this file to initialize the Secure Attribute Unit (SAU) and define non-secure interrupts (register NVIC_INIT_ITNS). The following initializations are performed:</p>
 115 <ul>
 116 <li><a class="el" href="partition_h_pg.html#sau_ctrlregister_sec">SAU CTRL register settings</a> provides settings for the SAU CTRL register.</li>
 117 <li><a class="el" href="partition_h_pg.html#sau_regions_sect">Configuration of the SAU Address Regions</a> provides configuration of the SAU Address Regions.</li>
 118 <li><a class="el" href="partition_h_pg.html#sau_sleepexception_sec">Configuration of Sleep and Exception behaviour</a> provides device-specific deepsleep and exception settings.</li>
 119 <li><a class="el" href="partition_h_pg.html#sau_interrupttarget_sec">Configuration of Interrupt Target settings</a> provides device-specific interrupt target settings.</li>
 120 </ul>
 121 <h1><a class="anchor" id="sau_ctrlregister_sec"></a>
 122 SAU CTRL register settings</h1>
 123 <table  class="cmtable">
 124 <tr>
 125 <th>#define </th><th>Value Range </th><th>Default </th><th>Description  </th></tr>
 126 <tr>
 127 <td>SAU_INIT_CTRL </td><td>0 .. 1 </td><td>0 </td><td>Initialize SAU CTRL register or not<ul>
 128 <li>0: do not initialize SAU CTRL register</li>
 129 <li>1: initialize SAU CTRL register  </li>
 130 </ul>
 131 </td></tr>
 132 <tr>
 133 <td>SAU_INIT_CTRL_ENABLE </td><td>0 .. 1 </td><td>0 </td><td>enable/disable the SAU<ul>
 134 <li>0: disable SAU</li>
 135 <li>1: enable SAU  </li>
 136 </ul>
 137 </td></tr>
 138 <tr>
 139 <td>SAU_INIT_CTRL_ALLNS </td><td>0 .. 1 </td><td>0 </td><td>value for SAU_CTRL register bit ALLNS<ul>
 140 <li>0: all Memory is Secure</li>
 141 <li>1: all Memory is Non-Secure  </li>
 142 </ul>
 143 </td></tr>
 144 </table>
 145 <h1><a class="anchor" id="sau_regions_sect"></a>
 146 Configuration of the SAU Address Regions</h1>
 147 <table  class="cmtable">
 148 <tr>
 149 <th>#define </th><th>Value Range </th><th>Default </th><th>Description  </th></tr>
 150 <tr>
 151 <td>SAU_REGIONS_MAX </td><td>0 .. tbd </td><td>8 </td><td>maximum number of SAU regions  </td></tr>
 152 <tr>
 153 <td>SAU_INIT_REGION&lt;number&gt; </td><td>0 .. 1 </td><td>0 </td><td>initialize SAU region or not<ul>
 154 <li>0: do not initialize SAU region</li>
 155 <li>1: initialize SAU region  </li>
 156 </ul>
 157 </td></tr>
 158 <tr>
 159 <td>SAU_INIT_START&lt;number&gt; </td><td>0x00000000 .. 0xFFFFFFE0<br/>
 160  [in steps of 32] </td><td>0x00000000 </td><td>region start address  </td></tr>
 161 <tr>
 162 <td>SAU_INIT_END&lt;number&gt; </td><td>0x00000000 .. 0xFFFFFFE0<br/>
 163  [in steps of 32] </td><td>0x00000000 </td><td>region start address  </td></tr>
 164 <tr>
 165 <td>SAU_INIT_NSC&lt;number&gt; </td><td>0 .. 1 </td><td>0 </td><td>SAU region attribute<ul>
 166 <li>0: Non-Secure</li>
 167 <li>1: Secure, Non-Secure callable  </li>
 168 </ul>
 169 </td></tr>
 170 </table>
 171 <p>The range of &lt;number&gt; is from 0 .. SAU_REGIONS_MAX. A set of these macros must exist for each &lt;number&gt;.</p>
 172 <p>The following example shows a set of SAU region macros.</p>
 173 <div class="fragment"><div class="line"><span class="preprocessor">#define SAU_REGIONS_MAX   8                 </span><span class="comment">/* Max. number of SAU regions */</span><span class="preprocessor"></span></div>
 174 <div class="line"><span class="preprocessor"></span> </div>
 175 <div class="line"><span class="preprocessor">#define SAU_INIT_REGION0    1</span></div>
 176 <div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_START0     0x00000000      </span><span class="comment">/* start address of SAU region 0 */</span><span class="preprocessor"></span></div>
 177 <div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_END0       0x001FFFE0      </span><span class="comment">/* end address of SAU region 0 */</span><span class="preprocessor"></span></div>
 178 <div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_NSC0       1</span></div>
 179 <div class="line"><span class="preprocessor"></span> </div>
 180 <div class="line"><span class="preprocessor">#define SAU_INIT_REGION1    1</span></div>
 181 <div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_START1     0x00200000      </span><span class="comment">/* start address of SAU region 1 */</span><span class="preprocessor"></span></div>
 182 <div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_END1       0x003FFFE0      </span><span class="comment">/* end address of SAU region 1 */</span><span class="preprocessor"></span></div>
 183 <div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_NSC1       0</span></div>
 184 <div class="line"><span class="preprocessor"></span> </div>
 185 <div class="line"><span class="preprocessor">#define SAU_INIT_REGION2    1</span></div>
 186 <div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_START2     0x20200000      </span><span class="comment">/* start address of SAU region 2 */</span><span class="preprocessor"></span></div>
 187 <div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_END2       0x203FFFE0      </span><span class="comment">/* end address of SAU region 2 */</span><span class="preprocessor"></span></div>
 188 <div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_NSC2       0</span></div>
 189 <div class="line"><span class="preprocessor"></span> </div>
 190 <div class="line"><span class="preprocessor">#define SAU_INIT_REGION3    1</span></div>
 191 <div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_START3     0x40000000      </span><span class="comment">/* start address of SAU region 3 */</span><span class="preprocessor"></span></div>
 192 <div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_END3       0x40040000      </span><span class="comment">/* end address of SAU region 3 */</span><span class="preprocessor"></span></div>
 193 <div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_NSC3       0</span></div>
 194 <div class="line"><span class="preprocessor"></span> </div>
 195 <div class="line"><span class="preprocessor">#define SAU_INIT_REGION4    0</span></div>
 196 <div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_START4     0x00000000      </span><span class="comment">/* start address of SAU region 4 */</span><span class="preprocessor"></span></div>
 197 <div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_END4       0x00000000      </span><span class="comment">/* end address of SAU region 4 */</span><span class="preprocessor"></span></div>
 198 <div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_NSC4       0</span></div>
 199 <div class="line"><span class="preprocessor"></span> </div>
 200 <div class="line"><span class="preprocessor">#define SAU_INIT_REGION5    0</span></div>
 201 <div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_START5     0x00000000      </span><span class="comment">/* start address of SAU region 5 */</span><span class="preprocessor"></span></div>
 202 <div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_END5       0x00000000      </span><span class="comment">/* end address of SAU region 5 */</span><span class="preprocessor"></span></div>
 203 <div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_NSC5       0</span></div>
 204 <div class="line"><span class="preprocessor"></span> </div>
 205 <div class="line"><span class="preprocessor">#define SAU_INIT_REGION6    0</span></div>
 206 <div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_START6     0x00000000      </span><span class="comment">/* start address of SAU region 6 */</span><span class="preprocessor"></span></div>
 207 <div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_END6       0x00000000      </span><span class="comment">/* end address of SAU region 6 */</span><span class="preprocessor"></span></div>
 208 <div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_NSC6       0</span></div>
 209 <div class="line"><span class="preprocessor"></span> </div>
 210 <div class="line"><span class="preprocessor">#define SAU_INIT_REGION7    0</span></div>
 211 <div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_START7     0x00000000      </span><span class="comment">/* start address of SAU region 7 */</span><span class="preprocessor"></span></div>
 212 <div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_END7       0x00000000      </span><span class="comment">/* end address of SAU region 7 */</span><span class="preprocessor"></span></div>
 213 <div class="line"><span class="preprocessor">#define SAU_INIT_NSC7       0</span></div>
 214 </div><!-- fragment --><h1><a class="anchor" id="sau_sleepexception_sec"></a>
 215 Configuration of Sleep and Exception behaviour</h1>
 216 <table  class="cmtable">
 217 <tr>
 218 <th>#define </th><th>Value Range </th><th>Default </th><th>Description  </th></tr>
 219 <tr>
 220 <td>CSR_INIT_DEEPSLEEPS </td><td>0 .. 1 </td><td>0 </td><td>value for SCB_CSR register bit DEEPSLEEPS<ul>
 221 <li>0: Deep Sleep can be enabled by Secure and Non-Secure state</li>
 222 <li>1: Deep Sleep can be enabled by Secure state only  </li>
 223 </ul>
 224 </td></tr>
 225 <tr>
 226 <td>AIRCR_INIT_SYSRESETREQS </td><td>0 .. 1 </td><td>0 </td><td>value for SCB_AIRCR register bit SYSRESETREQS<ul>
 227 <li>0: System reset request accessible from Secure and Non-Secure state</li>
 228 <li>1: System reset request accessible from Secure state only  </li>
 229 </ul>
 230 </td></tr>
 231 <tr>
 232 <td>AIRCR_INIT_PRIS </td><td>0 .. 1 </td><td>0 </td><td>value for SCB_AIRCR register bit PRIS<ul>
 233 <li>0: Priority of Non-Secure exceptions is Not altered</li>
 234 <li>1: Priority of Non-Secure exceptions is Lowered to 0x80-0xFF  </li>
 235 </ul>
 236 </td></tr>
 237 <tr>
 238 <td>AIRCR_INIT_BFHFNMINS </td><td>0 .. 1 </td><td>0 </td><td>value for SCB_AIRCR register bit BFHFNMINS<ul>
 239 <li>0: BusFault, HardFault, and NMI target are Secure state</li>
 240 <li>1: BusFault, HardFault, and NMI target are Non-Secure state  </li>
 241 </ul>
 242 </td></tr>
 243 </table>
 244 <h1><a class="anchor" id="sau_interrupttarget_sec"></a>
 245 Configuration of Interrupt Target settings</h1>
 246 <p>Each interrupt has a configuration bit that defines the execution in Secure or Non-secure state. The Non-Secure interrupts have a separate vector table. Refer to <a class="el" href="using_TrustZone_pg.html#Model_TrustZone">Programmers Model with TrustZone</a> for more information.</p>
 247 <table  class="cmtable">
 248 <tr>
 249 <th>#define </th><th>Value Range </th><th>Default </th><th>Description  </th></tr>
 250 <tr>
 251 <td>NVIC_INIT_ITNS&lt;number&gt; </td><td>0x00000000 .. 0xFFFFFFFF<br/>
 252  [each bit represents an interrupt] </td><td>0x00000000 </td><td>Interrupt vector target<ul>
 253 <li>0: Secure state</li>
 254 <li>1: Non-Secure state  </li>
 255 </ul>
 256 </td></tr>
 257 </table>
 258 <p>The range of &lt;number&gt; is 0 .. (&lt;number of external interrupts&gt; + 31) / 32.</p>
 259 <p>The following example shows the configuration for a maximum of 64 external interrupts.</p>
 260 <div class="fragment"><div class="line"><span class="preprocessor">#define NVIC_INIT_ITNS0      0x0000122B</span></div>
 261 <div class="line"><span class="preprocessor">#define NVIC_INIT_ITNS1      0x0000003A</span></div>
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