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  34    <div id="projectname">CMSIS-CORE
  35    &#160;<span id="projectnumber">Version 5.0.0 - Beta</span>
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  37    <div id="projectbrief">CMSIS-CORE support for Cortex-M processor-based devices</div>
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 110   <div class="headertitle">
 111 <div class="title">Register Mapping </div>  </div>
 112 </div><!--header-->
 113 <div class="contents">
 114 <div class="textblock"><p>The table below associates some common register names used in CMSIS to the register names used in Technical Reference Manuals.</p>
 115 <table  class="cmtable" summary="Register Mapping">
 116 <tr>
 117 <th>CMSIS Register Name </th><th>Cortex-M3, Cortex-M4, and Cortex-M7 </th><th>Cortex-M0 and Cortex-M0+ </th><th>Register Name  </th></tr>
 118 <tr>
 119 <th colspan="4">Nested Vectored Interrupt Controller (NVIC) Register Access  </th></tr>
 120 <tr>
 121 <td>NVIC-&gt;ISER[] </td><td>NVIC_ISER0..7 </td><td>ISER </td><td>Interrupt Set-Enable Registers  </td></tr>
 122 <tr>
 123 <td>NVIC-&gt;ICER[] </td><td>NVIC_ICER0..7 </td><td>ICER </td><td>Interrupt Clear-Enable Registers  </td></tr>
 124 <tr>
 125 <td>NVIC-&gt;ISPR[] </td><td>NVIC_ISPR0..7 </td><td>ISPR </td><td>Interrupt Set-Pending Registers  </td></tr>
 126 <tr>
 127 <td>NVIC-&gt;ICPR[] </td><td>NVIC_ICPR0..7 </td><td>ICPR </td><td>Interrupt Clear-Pending Registers  </td></tr>
 128 <tr>
 129 <td>NVIC-&gt;IABR[] </td><td>NVIC_IABR0..7 </td><td>- </td><td>Interrupt Active Bit Register  </td></tr>
 130 <tr>
 131 <td>NVIC-&gt;IP[] </td><td>NVIC_IPR0..59 </td><td>IPR0..7 </td><td>Interrupt Priority Register  </td></tr>
 132 <tr>
 133 <td>NVIC-&gt;STIR </td><td>STIR </td><td>- </td><td>Software Triggered Interrupt Register  </td></tr>
 134 <tr>
 135 <th colspan="4">System Control Block (SCB) Register Access  </th></tr>
 136 <tr>
 137 <td>SCB-&gt;CPUID </td><td>CPUID </td><td>CPUID </td><td>CPUID Base Register  </td></tr>
 138 <tr>
 139 <td>SCB-&gt;ICSR </td><td>ICSR </td><td>ICSR </td><td>Interrupt Control and State Register  </td></tr>
 140 <tr>
 141 <td>SCB-&gt;VTOR </td><td>VTOR </td><td>- </td><td>Vector Table Offset Register  </td></tr>
 142 <tr>
 143 <td>SCB-&gt;AIRCR </td><td>AIRCR </td><td>AIRCR </td><td>Application Interrupt and Reset Control Register  </td></tr>
 144 <tr>
 145 <td>SCB-&gt;SCR </td><td>SCR </td><td>SCR </td><td>System Control Register  </td></tr>
 146 <tr>
 147 <td>SCB-&gt;CCR </td><td>CCR </td><td>CCR </td><td>Configuration and Control Register  </td></tr>
 148 <tr>
 149 <td>SCB-&gt;SHP[] </td><td>SHPR1..3 </td><td>SHPR2..3 </td><td>System Handler Priority Registers  </td></tr>
 150 <tr>
 151 <td>SCB-&gt;SHCSR </td><td>SHCSR </td><td>SHCSR </td><td>System Handler Control and State Register  </td></tr>
 152 <tr>
 153 <td>SCB-&gt;CFSR </td><td>CFSR </td><td>- </td><td>Configurable Fault Status Registers  </td></tr>
 154 <tr>
 155 <td>SCB-&gt;HFSR </td><td>HFSR </td><td>- </td><td>HardFault Status Register  </td></tr>
 156 <tr>
 157 <td>SCB-&gt;DFSR </td><td>DFSR </td><td>- </td><td>Debug Fault Status Register  </td></tr>
 158 <tr>
 159 <td>SCB-&gt;MMFAR </td><td>MMFAR </td><td>- </td><td>MemManage Fault Address Register  </td></tr>
 160 <tr>
 161 <td>SCB-&gt;BFAR </td><td>BFAR </td><td>- </td><td>BusFault Address Register  </td></tr>
 162 <tr>
 163 <td>SCB-&gt;AFSR </td><td>AFSR </td><td>- </td><td>Auxiliary Fault Status Register  </td></tr>
 164 <tr>
 165 <td>SCB-&gt;PFR[] </td><td>ID_PFR0..1 </td><td>- </td><td>Processor Feature Registers  </td></tr>
 166 <tr>
 167 <td>SCB-&gt;DFR </td><td>ID_DFR0 </td><td>- </td><td>Debug Feature Register  </td></tr>
 168 <tr>
 169 <td>SCB-&gt;ADR </td><td>ID_AFR0 </td><td>- </td><td>Auxiliary Feature Register  </td></tr>
 170 <tr>
 171 <td>SCB-&gt;MMFR[] </td><td>ID_MMFR0..3 </td><td>- </td><td>Memory Model Feature Registers  </td></tr>
 172 <tr>
 173 <td>SCB-&gt;ISAR[] </td><td>ID_ISAR0..4 </td><td>- </td><td>Instruction Set Attributes Registers  </td></tr>
 174 <tr>
 175 <td>SCB-&gt;CPACR </td><td>CPACR </td><td>- </td><td>Coprocessor Access Control Register  </td></tr>
 176 <tr>
 177 <th colspan="4">System Control and ID Registers not in the SCB (SCnSCB) Register Access  </th></tr>
 178 <tr>
 179 <td>SCnSCB-&gt;ICTR </td><td>ICTR </td><td>- </td><td>Interrupt Controller Type Register  </td></tr>
 180 <tr>
 181 <td>SCnSCB-&gt;ACTLR </td><td>ACTLR </td><td>- </td><td>Auxiliary Control Register  </td></tr>
 182 <tr>
 183 <th colspan="4">System Timer (SysTick) Control and Status Register Access  </th></tr>
 184 <tr>
 185 <td>SysTick-&gt;CTRL </td><td>STCSR </td><td>SYST_CSR </td><td>SysTick Control and Status Register  </td></tr>
 186 <tr>
 187 <td>SysTick-&gt;LOAD </td><td>STRVR </td><td>SYST_RVR </td><td>SysTick Reload Value Register  </td></tr>
 188 <tr>
 189 <td>SysTick-&gt;VAL </td><td>STCVR </td><td>SYST_CVR </td><td>SysTick Current Value Register  </td></tr>
 190 <tr>
 191 <td>SysTick-&gt;CALIB </td><td>STCR </td><td>SYST_CALIB </td><td>SysTick Calibaration Value Register  </td></tr>
 192 <tr>
 193 <th colspan="4">Data Watchpoint and Trace (DWT) Register Access  </th></tr>
 194 <tr>
 195 <td>DWT-&gt;CTRL </td><td>DWT_CTRL </td><td>- </td><td>Control Register  </td></tr>
 196 <tr>
 197 <td>DWT-&gt;CYCCNT </td><td>DWT_CYCCNT </td><td>- </td><td>Cycle Count Register  </td></tr>
 198 <tr>
 199 <td>DWT-&gt;CPICNT </td><td>DWT_CPICNT </td><td>- </td><td>CPI Count Register  </td></tr>
 200 <tr>
 201 <td>DWT-&gt;EXCCNT </td><td>DWT_EXCCNT </td><td>- </td><td>Exception Overhead Count Register  </td></tr>
 202 <tr>
 203 <td>DWT-&gt;SLEEPCNT </td><td>DWT_SLEEPCNT </td><td>- </td><td>Sleep Count Register  </td></tr>
 204 <tr>
 205 <td>DWT-&gt;LSUCNT </td><td>DWT_LSUCNT </td><td>- </td><td>LSU Count Register  </td></tr>
 206 <tr>
 207 <td>DWT-&gt;FOLDCNT </td><td>DWT_FOLDCNT </td><td>- </td><td>Folded-instruction Count Register  </td></tr>
 208 <tr>
 209 <td>DWT-&gt;PCSR </td><td>DWT_PCSR </td><td>- </td><td>Program Counter Sample Register  </td></tr>
 210 <tr>
 211 <td>DWT-&gt;COMP0..3 </td><td>DWT_COMP0..3 </td><td>- </td><td>Comparator Register 0..3  </td></tr>
 212 <tr>
 213 <td>DWT-&gt;MASK0..3 </td><td>DWT_MASK0..3 </td><td>- </td><td>Mask Register 0..3  </td></tr>
 214 <tr>
 215 <td>DWT-&gt;FUNCTION0..3 </td><td>DWT_FUNCTION0..3 </td><td>- </td><td>Function Register 0..3  </td></tr>
 216 <tr>
 217 <th colspan="4">Instrumentation Trace Macrocell (ITM) Register Access  </th></tr>
 218 <tr>
 219 <td>ITM-&gt;PORT[] </td><td>ITM_STIM0..31 </td><td>- </td><td>Stimulus Port Registers  </td></tr>
 220 <tr>
 221 <td>ITM-&gt;TER </td><td>ITM_TER </td><td>- </td><td>Trace Enable Register  </td></tr>
 222 <tr>
 223 <td>ITM-&gt;TPR </td><td>ITM_TPR </td><td>- </td><td>ITM Trace Privilege Register  </td></tr>
 224 <tr>
 225 <td>ITM-&gt;TCR </td><td>ITM_TCR </td><td>- </td><td>Trace Control Register  </td></tr>
 226 <tr>
 227 <th colspan="4">Trace Port Interface (TPIU) Register Access  </th></tr>
 228 <tr>
 229 <td>TPI-&gt;SSPSR </td><td>TPIU_SSPR </td><td>- </td><td>Supported Parallel Port Size Register  </td></tr>
 230 <tr>
 231 <td>TPI-&gt;CSPSR </td><td>TPIU_CSPSR </td><td>- </td><td>Current Parallel Port Size Register  </td></tr>
 232 <tr>
 233 <td>TPI-&gt;ACPR </td><td>TPIU_ACPR </td><td>- </td><td>Asynchronous Clock Prescaler Register  </td></tr>
 234 <tr>
 235 <td>TPI-&gt;SPPR </td><td>TPIU_SPPR </td><td>- </td><td>Selected Pin Protocol Register  </td></tr>
 236 <tr>
 237 <td>TPI-&gt;FFSR </td><td>TPIU_FFSR </td><td>- </td><td>Formatter and Flush Status Register  </td></tr>
 238 <tr>
 239 <td>TPI-&gt;FFCR </td><td>TPIU_FFCR </td><td>- </td><td>Formatter and Flush Control Register  </td></tr>
 240 <tr>
 241 <td>TPI-&gt;FSCR </td><td>TPIU_FSCR </td><td>- </td><td>Formatter Synchronization Counter Register  </td></tr>
 242 <tr>
 243 <td>TPI-&gt;TRIGGER </td><td>TRIGGER </td><td>- </td><td>TRIGGER  </td></tr>
 244 <tr>
 245 <td>TPI-&gt;FIFO0 </td><td>FIFO data 0 </td><td>- </td><td>Integration ETM Data  </td></tr>
 246 <tr>
 247 <td>TPI-&gt;ITATBCTR2 </td><td>ITATBCTR2 </td><td>- </td><td>ITATBCTR2  </td></tr>
 248 <tr>
 249 <td>TPI-&gt;ITATBCTR0 </td><td>ITATBCTR0 </td><td>- </td><td>ITATBCTR0  </td></tr>
 250 <tr>
 251 <td>TPI-&gt;FIFO1 </td><td>FIFO data 1 </td><td>- </td><td>Integration ITM Data  </td></tr>
 252 <tr>
 253 <td>TPI-&gt;ITCTRL </td><td>TPIU_ITCTRL </td><td>- </td><td>Integration Mode Control  </td></tr>
 254 <tr>
 255 <td>TPI-&gt;CLAIMSET </td><td>CLAIMSET </td><td>- </td><td>Claim tag set  </td></tr>
 256 <tr>
 257 <td>TPI-&gt;CLAIMCLR </td><td>CLAIMCLR </td><td>- </td><td>Claim tag clear  </td></tr>
 258 <tr>
 259 <td>TPI-&gt;DEVID </td><td>TPIU_DEVID </td><td>- </td><td>TPIU_DEVID  </td></tr>
 260 <tr>
 261 <td>TPI-&gt;DEVTYPE </td><td>TPIU_DEVTYPE </td><td>- </td><td>TPIU_DEVTYPE  </td></tr>
 262 <tr>
 263 <th colspan="4">Memory Protection Unit (MPU) Register Access  </th></tr>
 264 <tr>
 265 <td>MPU-&gt;TYPE </td><td>MPU_TYPE </td><td>- </td><td>MPU Type Register  </td></tr>
 266 <tr>
 267 <td>MPU-&gt;CTRL </td><td>MPU_CTRL </td><td>- </td><td>MPU Control Register  </td></tr>
 268 <tr>
 269 <td>MPU-&gt;RNR </td><td>MPU_RNR </td><td>- </td><td>MPU Region Number Register  </td></tr>
 270 <tr>
 271 <td>MPU-&gt;RBAR </td><td>MPU_RBAR </td><td>- </td><td>MPU Region Base Address Register  </td></tr>
 272 <tr>
 273 <td>MPU-&gt;RASR </td><td>MPU_RASR </td><td>- </td><td>MPU Region Attribute and Size Register  </td></tr>
 274 <tr>
 275 <td>MPU-&gt;RBAR_A1..3 </td><td>MPU_RBAR_A1..3 </td><td>- </td><td>MPU alias Register  </td></tr>
 276 <tr>
 277 <td>MPU-&gt;RSAR_A1..3 </td><td>MPU_RSAR_A1..3 </td><td>- </td><td>MPU alias Register  </td></tr>
 278 <tr>
 279 <th colspan="4">Floating Point Unit (FPU) Register Access [only Cortex-M4 and Cortex-M7 both with FPU]  </th></tr>
 280 <tr>
 281 <td>FPU-&gt;FPCCR </td><td>FPCCR </td><td>- </td><td>FP Context Control Register  </td></tr>
 282 <tr>
 283 <td>FPU-&gt;FPCAR </td><td>FPCAR </td><td>- </td><td>FP Context Address Register  </td></tr>
 284 <tr>
 285 <td>FPU-&gt;FPDSCR </td><td>FPDSCR </td><td>- </td><td>FP Default Status Control Register  </td></tr>
 286 <tr>
 287 <td>FPU-&gt;MVFR0..1 </td><td>MVFR0..1 </td><td>- </td><td>Media and VFP Feature Registers  </td></tr>
 288 </table>
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