begriffs open source - cmsis/blob - main/Core_A/group__GIC__functions.html

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 128 <a href="#nested-classes">Data Structures</a> &#124;
 129 <a href="#define-members">Macros</a> &#124;
 130 <a href="#func-members">Functions</a>  </div>
 131   <div class="headertitle"><div class="title">Generic Interrupt Controller Functions<div class="ingroups"><a class="el" href="group__CMSIS__Core__FunctionInterface.html">Core Peripherals</a></div></div></div>
 132 </div><!--header-->
 133 <div class="contents">
 134
 135 <p>The Generic Interrupt Controller Functions grant access to the configuration, control and status registers of the Generic Interrupt Controller (GIC).
 136 <a href="#details">More...</a></p>
 137 <table class="memberdecls">
 138 <tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="nested-classes" name="nested-classes"></a>
 139 Data Structures</h2></td></tr>
 140 <tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structGICInterface__Type.html">GICInterface_Type</a></td></tr>
 141 <tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">Structure type to access the Generic Interrupt Controller Interface (GICC)  <a href="structGICInterface__Type.html#details">More...</a><br /></td></tr>
 142 <tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
 143 <tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structGICDistributor__Type.html">GICDistributor_Type</a></td></tr>
 144 <tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">Structure type to access the Generic Interrupt Controller Distributor (GICD)  <a href="structGICDistributor__Type.html#details">More...</a><br /></td></tr>
 145 <tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
 146 </table><table class="memberdecls">
 147 <tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="define-members" name="define-members"></a>
 148 Macros</h2></td></tr>
 149 <tr class="memitem:ga82e193c0016a9377274756b2673464a6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#ga82e193c0016a9377274756b2673464a6">GICDistributor</a>&#160;&#160;&#160;((<a class="el" href="structGICDistributor__Type.html">GICDistributor_Type</a>      *)     GIC_DISTRIBUTOR_BASE )</td></tr>
 150 <tr class="memdesc:ga82e193c0016a9377274756b2673464a6"><td class="mdescLeft">&#160;</td><td class="mdescRight">GIC Distributor register set access pointer.  <br /></td></tr>
 151 <tr class="separator:ga82e193c0016a9377274756b2673464a6"><td class="memSeparator" colspan="2">&#160;</td></tr>
 152 <tr class="memitem:ga31a083dbdc5cb84178dbf184286180e3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#ga31a083dbdc5cb84178dbf184286180e3">GICInterface</a>&#160;&#160;&#160;((<a class="el" href="structGICInterface__Type.html">GICInterface_Type</a>        *)     GIC_INTERFACE_BASE )</td></tr>
 153 <tr class="memdesc:ga31a083dbdc5cb84178dbf184286180e3"><td class="mdescLeft">&#160;</td><td class="mdescRight">GIC Interface register set access pointer.  <br /></td></tr>
 154 <tr class="separator:ga31a083dbdc5cb84178dbf184286180e3"><td class="memSeparator" colspan="2">&#160;</td></tr>
 155 </table><table class="memberdecls">
 156 <tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="func-members" name="func-members"></a>
 157 Functions</h2></td></tr>
 158 <tr class="memitem:ga0f44df6823e90178183257e096e5cac6"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#ga0f44df6823e90178183257e096e5cac6">GIC_EnableDistributor</a> (void)</td></tr>
 159 <tr class="memdesc:ga0f44df6823e90178183257e096e5cac6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable the interrupt distributor using the GIC's CTLR register.  <br /></td></tr>
 160 <tr class="separator:ga0f44df6823e90178183257e096e5cac6"><td class="memSeparator" colspan="2">&#160;</td></tr>
 161 <tr class="memitem:ga363311538d4a4d750197b9936505d466"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#ga363311538d4a4d750197b9936505d466">GIC_DisableDistributor</a> (void)</td></tr>
 162 <tr class="memdesc:ga363311538d4a4d750197b9936505d466"><td class="mdescLeft">&#160;</td><td class="mdescRight">Disable the interrupt distributor using the GIC's CTLR register.  <br /></td></tr>
 163 <tr class="separator:ga363311538d4a4d750197b9936505d466"><td class="memSeparator" colspan="2">&#160;</td></tr>
 164 <tr class="memitem:ga7d93d39736ef5e379e6511430ee6e75f"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#ga7d93d39736ef5e379e6511430ee6e75f">GIC_DistributorInfo</a> (void)</td></tr>
 165 <tr class="memdesc:ga7d93d39736ef5e379e6511430ee6e75f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read the GIC's TYPER register.  <br /></td></tr>
 166 <tr class="separator:ga7d93d39736ef5e379e6511430ee6e75f"><td class="memSeparator" colspan="2">&#160;</td></tr>
 167 <tr class="memitem:ga1481d0cdf78f8c93fb2a710a519c4dc6"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#ga1481d0cdf78f8c93fb2a710a519c4dc6">GIC_DistributorImplementer</a> (void)</td></tr>
 168 <tr class="memdesc:ga1481d0cdf78f8c93fb2a710a519c4dc6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Reads the GIC's IIDR register.  <br /></td></tr>
 169 <tr class="separator:ga1481d0cdf78f8c93fb2a710a519c4dc6"><td class="memSeparator" colspan="2">&#160;</td></tr>
 170 <tr class="memitem:gae86bba705d0d4ef812b84d29d7b3ca2b"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#gae86bba705d0d4ef812b84d29d7b3ca2b">GIC_SetTarget</a> (<a class="el" href="group__irq__ctrl__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn, uint32_t cpu_target)</td></tr>
 171 <tr class="memdesc:gae86bba705d0d4ef812b84d29d7b3ca2b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Sets the GIC's ITARGETSR register for the given interrupt.  <br /></td></tr>
 172 <tr class="separator:gae86bba705d0d4ef812b84d29d7b3ca2b"><td class="memSeparator" colspan="2">&#160;</td></tr>
 173 <tr class="memitem:gafccf881f9517592f30489bcabcb738a8"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#gafccf881f9517592f30489bcabcb738a8">GIC_GetTarget</a> (<a class="el" href="group__irq__ctrl__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn)</td></tr>
 174 <tr class="memdesc:gafccf881f9517592f30489bcabcb738a8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read the GIC's ITARGETSR register.  <br /></td></tr>
 175 <tr class="separator:gafccf881f9517592f30489bcabcb738a8"><td class="memSeparator" colspan="2">&#160;</td></tr>
 176 <tr class="memitem:ga758e5600d7f891e4f2f551bb45d07fce"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#ga758e5600d7f891e4f2f551bb45d07fce">GIC_EnableInterface</a> (void)</td></tr>
 177 <tr class="memdesc:ga758e5600d7f891e4f2f551bb45d07fce"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable the CPU's interrupt interface.  <br /></td></tr>
 178 <tr class="separator:ga758e5600d7f891e4f2f551bb45d07fce"><td class="memSeparator" colspan="2">&#160;</td></tr>
 179 <tr class="memitem:ga0605877ad627c1f4320e518725fd103e"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#ga0605877ad627c1f4320e518725fd103e">GIC_DisableInterface</a> (void)</td></tr>
 180 <tr class="memdesc:ga0605877ad627c1f4320e518725fd103e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Disable the CPU's interrupt interface.  <br /></td></tr>
 181 <tr class="separator:ga0605877ad627c1f4320e518725fd103e"><td class="memSeparator" colspan="2">&#160;</td></tr>
 182 <tr class="memitem:gafc08bbc58b25fef0d24003313fd16eb8"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE <a class="el" href="group__irq__ctrl__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#gafc08bbc58b25fef0d24003313fd16eb8">GIC_AcknowledgePending</a> (void)</td></tr>
 183 <tr class="memdesc:gafc08bbc58b25fef0d24003313fd16eb8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read the CPU's IAR register.  <br /></td></tr>
 184 <tr class="separator:gafc08bbc58b25fef0d24003313fd16eb8"><td class="memSeparator" colspan="2">&#160;</td></tr>
 185 <tr class="memitem:gac23f090f572a058b4a737f6613ded9cd"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#gac23f090f572a058b4a737f6613ded9cd">GIC_EndInterrupt</a> (<a class="el" href="group__irq__ctrl__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn)</td></tr>
 186 <tr class="memdesc:gac23f090f572a058b4a737f6613ded9cd"><td class="mdescLeft">&#160;</td><td class="mdescRight">Writes the given interrupt number to the CPU's EOIR register.  <br /></td></tr>
 187 <tr class="separator:gac23f090f572a058b4a737f6613ded9cd"><td class="memSeparator" colspan="2">&#160;</td></tr>
 188 <tr class="memitem:gaeba215d9c4ec3599e0a168800288c3f3"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#gaeba215d9c4ec3599e0a168800288c3f3">GIC_EnableIRQ</a> (<a class="el" href="group__irq__ctrl__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn)</td></tr>
 189 <tr class="memdesc:gaeba215d9c4ec3599e0a168800288c3f3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enables the given interrupt using GIC's ISENABLER register.  <br /></td></tr>
 190 <tr class="separator:gaeba215d9c4ec3599e0a168800288c3f3"><td class="memSeparator" colspan="2">&#160;</td></tr>
 191 <tr class="memitem:ga2102399d255690c0674209a6faeec13d"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#ga2102399d255690c0674209a6faeec13d">GIC_DisableIRQ</a> (<a class="el" href="group__irq__ctrl__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn)</td></tr>
 192 <tr class="memdesc:ga2102399d255690c0674209a6faeec13d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Disables the given interrupt using GIC's ICENABLER register.  <br /></td></tr>
 193 <tr class="separator:ga2102399d255690c0674209a6faeec13d"><td class="memSeparator" colspan="2">&#160;</td></tr>
 194 <tr class="memitem:ga18fbddf7f3594df141c97f61a71da47c"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#ga18fbddf7f3594df141c97f61a71da47c">GIC_SetPendingIRQ</a> (<a class="el" href="group__irq__ctrl__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn)</td></tr>
 195 <tr class="memdesc:ga18fbddf7f3594df141c97f61a71da47c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Sets the given interrupt as pending using GIC's ISPENDR register.  <br /></td></tr>
 196 <tr class="separator:ga18fbddf7f3594df141c97f61a71da47c"><td class="memSeparator" colspan="2">&#160;</td></tr>
 197 <tr class="memitem:ga5ad17ad70f23d1ff36015ffac33d383d"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#ga5ad17ad70f23d1ff36015ffac33d383d">GIC_ClearPendingIRQ</a> (<a class="el" href="group__irq__ctrl__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn)</td></tr>
 198 <tr class="memdesc:ga5ad17ad70f23d1ff36015ffac33d383d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Clears the given interrupt from being pending using GIC's ICPENDR register.  <br /></td></tr>
 199 <tr class="separator:ga5ad17ad70f23d1ff36015ffac33d383d"><td class="memSeparator" colspan="2">&#160;</td></tr>
 200 <tr class="memitem:ga27b9862b58290276851ec669cabf0f71"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#ga27b9862b58290276851ec669cabf0f71">GIC_SetPriority</a> (<a class="el" href="group__irq__ctrl__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn, uint32_t priority)</td></tr>
 201 <tr class="memdesc:ga27b9862b58290276851ec669cabf0f71"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set the priority for the given interrupt in the GIC's IPRIORITYR register.  <br /></td></tr>
 202 <tr class="separator:ga27b9862b58290276851ec669cabf0f71"><td class="memSeparator" colspan="2">&#160;</td></tr>
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 204 <tr class="memdesc:ga397048004654f792649742f95bf8ae67"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read the current interrupt priority from GIC's IPRIORITYR register.  <br /></td></tr>
 205 <tr class="separator:ga397048004654f792649742f95bf8ae67"><td class="memSeparator" colspan="2">&#160;</td></tr>
 206 <tr class="memitem:gaa5eb0e76dbc89596e1ce47ddb9edc4a0"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#gaa5eb0e76dbc89596e1ce47ddb9edc4a0">GIC_SetInterfacePriorityMask</a> (uint32_t priority)</td></tr>
 207 <tr class="memdesc:gaa5eb0e76dbc89596e1ce47ddb9edc4a0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set the interrupt priority mask using CPU's PMR register.  <br /></td></tr>
 208 <tr class="separator:gaa5eb0e76dbc89596e1ce47ddb9edc4a0"><td class="memSeparator" colspan="2">&#160;</td></tr>
 209 <tr class="memitem:ga2c5f9e5637560fc9d5c29d772580a728"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#ga2c5f9e5637560fc9d5c29d772580a728">GIC_GetInterfacePriorityMask</a> (void)</td></tr>
 210 <tr class="memdesc:ga2c5f9e5637560fc9d5c29d772580a728"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read the current interrupt priority mask from CPU's PMR register.  <br /></td></tr>
 211 <tr class="separator:ga2c5f9e5637560fc9d5c29d772580a728"><td class="memSeparator" colspan="2">&#160;</td></tr>
 212 <tr class="memitem:ga5dfedeb5403656a77e0fef4e1cc2c0c6"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#ga5dfedeb5403656a77e0fef4e1cc2c0c6">GIC_SetBinaryPoint</a> (uint32_t binary_point)</td></tr>
 213 <tr class="memdesc:ga5dfedeb5403656a77e0fef4e1cc2c0c6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Configures the group priority and subpriority split point using CPU's BPR register.  <br /></td></tr>
 214 <tr class="separator:ga5dfedeb5403656a77e0fef4e1cc2c0c6"><td class="memSeparator" colspan="2">&#160;</td></tr>
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 216 <tr class="memdesc:gaa7046d8206ddd4696716726e68f85906"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read the current group priority and subpriority split point from CPU's BPR register.  <br /></td></tr>
 217 <tr class="separator:gaa7046d8206ddd4696716726e68f85906"><td class="memSeparator" colspan="2">&#160;</td></tr>
 218 <tr class="memitem:gabc88483ecf94a2c222b644ecfa60eb9f"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#gabc88483ecf94a2c222b644ecfa60eb9f">GIC_GetIRQStatus</a> (<a class="el" href="group__irq__ctrl__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn)</td></tr>
 219 <tr class="memdesc:gabc88483ecf94a2c222b644ecfa60eb9f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Get the status for a given interrupt.  <br /></td></tr>
 220 <tr class="separator:gabc88483ecf94a2c222b644ecfa60eb9f"><td class="memSeparator" colspan="2">&#160;</td></tr>
 221 <tr class="memitem:ga2de8850780af26e802ee4cc43e9da6e9"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#ga2de8850780af26e802ee4cc43e9da6e9">GIC_SendSGI</a> (<a class="el" href="group__irq__ctrl__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn, uint32_t target_list, uint32_t filter_list)</td></tr>
 222 <tr class="memdesc:ga2de8850780af26e802ee4cc43e9da6e9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Generate a software interrupt using GIC's SGIR register.  <br /></td></tr>
 223 <tr class="separator:ga2de8850780af26e802ee4cc43e9da6e9"><td class="memSeparator" colspan="2">&#160;</td></tr>
 224 <tr class="memitem:ga8bb27e1bab132a8df44190adb996c2a1"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#ga8bb27e1bab132a8df44190adb996c2a1">GIC_GetHighPendingIRQ</a> (void)</td></tr>
 225 <tr class="memdesc:ga8bb27e1bab132a8df44190adb996c2a1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Get the interrupt number of the highest interrupt pending from CPU's HPPIR register.  <br /></td></tr>
 226 <tr class="separator:ga8bb27e1bab132a8df44190adb996c2a1"><td class="memSeparator" colspan="2">&#160;</td></tr>
 227 <tr class="memitem:gaba1b2665cdda47fc0bc3d7b90690dc50"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#gaba1b2665cdda47fc0bc3d7b90690dc50">GIC_GetInterfaceId</a> (void)</td></tr>
 228 <tr class="memdesc:gaba1b2665cdda47fc0bc3d7b90690dc50"><td class="mdescLeft">&#160;</td><td class="mdescRight">Provides information about the implementer and revision of the CPU interface.  <br /></td></tr>
 229 <tr class="separator:gaba1b2665cdda47fc0bc3d7b90690dc50"><td class="memSeparator" colspan="2">&#160;</td></tr>
 230 <tr class="memitem:ga07acd03d02683bb6e33e7f57f5f371d1"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#ga07acd03d02683bb6e33e7f57f5f371d1">GIC_DistInit</a> (void)</td></tr>
 231 <tr class="memdesc:ga07acd03d02683bb6e33e7f57f5f371d1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Initialize the interrupt distributor.  <br /></td></tr>
 232 <tr class="separator:ga07acd03d02683bb6e33e7f57f5f371d1"><td class="memSeparator" colspan="2">&#160;</td></tr>
 233 <tr class="memitem:ga1c93f8af9f428cda8ec066bf4bfbade9"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#ga1c93f8af9f428cda8ec066bf4bfbade9">GIC_CPUInterfaceInit</a> (void)</td></tr>
 234 <tr class="memdesc:ga1c93f8af9f428cda8ec066bf4bfbade9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Initialize the CPU's interrupt interface.  <br /></td></tr>
 235 <tr class="separator:ga1c93f8af9f428cda8ec066bf4bfbade9"><td class="memSeparator" colspan="2">&#160;</td></tr>
 236 <tr class="memitem:ga818881f69aae3eef6eb996bee6f6c63e"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#ga818881f69aae3eef6eb996bee6f6c63e">GIC_Enable</a> (void)</td></tr>
 237 <tr class="memdesc:ga818881f69aae3eef6eb996bee6f6c63e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Initialize and enable the GIC.  <br /></td></tr>
 238 <tr class="separator:ga818881f69aae3eef6eb996bee6f6c63e"><td class="memSeparator" colspan="2">&#160;</td></tr>
 239 </table>
 240 <a name="details" id="details"></a><h2 class="groupheader">Description</h2>
 241 <p>The Generic Interrupt Controller Functions grant access to the configuration, control and status registers of the Generic Interrupt Controller (GIC). </p>
 242 <p>Reference: <a href="http://infocenter.arm.com/help/topic/com.arm.doc.ihi0069c/index.html">Generic Interrupt Controller Architecture Specificaton</a>.</p>
 243 <p>The following table shows the register naming of CMSIS in correlation with various technical reference manuals.</p>
 244 <table class="markdownTable">
 245 <tr class="markdownTableHead">
 246 <th class="markdownTableHeadLeft">CMSIS Register Name   </th><th class="markdownTableHeadLeft">Cortex-A5 TRM   </th><th class="markdownTableHeadLeft">Cortex-A7 TRM   </th><th class="markdownTableHeadLeft">Cortex-A9 TRM    </th></tr>
 247 <tr class="markdownTableRowOdd">
 248 <td class="markdownTableBodyLeft"><b>GIC Distributor</b>   </td><td class="markdownTableBodyLeft"></td><td class="markdownTableBodyLeft"></td><td class="markdownTableBodyLeft"></td></tr>
 249 <tr class="markdownTableRowEven">
 250 <td class="markdownTableBodyLeft"><a class="el" href="structGICDistributor__Type.html#a6ca67d9838ab3425864207c3a0399bd7">GICDistributor-&gt;CTLR</a>   </td><td class="markdownTableBodyLeft">ICDDCR   </td><td class="markdownTableBodyLeft">GICD_CTLR   </td><td class="markdownTableBodyLeft">ICDDCR    </td></tr>
 251 <tr class="markdownTableRowOdd">
 252 <td class="markdownTableBodyLeft"><a class="el" href="structGICDistributor__Type.html#a405823d97dc90dd9d397a3980e2cd207">GICDistributor-&gt;TYPER</a>   </td><td class="markdownTableBodyLeft">ICDICTR   </td><td class="markdownTableBodyLeft">GICD_TYPER   </td><td class="markdownTableBodyLeft">ICDICTR    </td></tr>
 253 <tr class="markdownTableRowEven">
 254 <td class="markdownTableBodyLeft"><a class="el" href="structGICDistributor__Type.html#acebf65dae4cb82cd3c7deeefca9c9722">GICDistributor-&gt;IIDR</a>   </td><td class="markdownTableBodyLeft">ICDIIDR   </td><td class="markdownTableBodyLeft">GICD_IIDR   </td><td class="markdownTableBodyLeft">ICDIIDR    </td></tr>
 255 <tr class="markdownTableRowOdd">
 256 <td class="markdownTableBodyLeft"><a class="el" href="structGICDistributor__Type.html#ae24f260e27065660a2059803293084f2">GICDistributor-&gt;STATUSR</a>   </td><td class="markdownTableBodyLeft"></td><td class="markdownTableBodyLeft"></td><td class="markdownTableBodyLeft"></td></tr>
 257 <tr class="markdownTableRowEven">
 258 <td class="markdownTableBodyLeft"><a class="el" href="structGICDistributor__Type.html#afbdd372578e2cd6f998320282cc8ed25">GICDistributor-&gt;SETSPI_NSR</a>   </td><td class="markdownTableBodyLeft"></td><td class="markdownTableBodyLeft"></td><td class="markdownTableBodyLeft"></td></tr>
 259 <tr class="markdownTableRowOdd">
 260 <td class="markdownTableBodyLeft"><a class="el" href="structGICDistributor__Type.html#a2f584d3fbeaa355faf234f2ee57d1168">GICDistributor-&gt;CLRSPI_NSR</a>   </td><td class="markdownTableBodyLeft"></td><td class="markdownTableBodyLeft"></td><td class="markdownTableBodyLeft"></td></tr>
 261 <tr class="markdownTableRowEven">
 262 <td class="markdownTableBodyLeft"><a class="el" href="structGICDistributor__Type.html#a6a9effdd633c6e75651d9f53caace306">GICDistributor-&gt;IGROUPR[]</a>   </td><td class="markdownTableBodyLeft">ICDISR   </td><td class="markdownTableBodyLeft">GICD_IGROUPRn   </td><td class="markdownTableBodyLeft">ICDISRn    </td></tr>
 263 <tr class="markdownTableRowOdd">
 264 <td class="markdownTableBodyLeft"><a class="el" href="structGICDistributor__Type.html#a1da3a2066b64644a0bb8a3066075ba87">GICDistributor-&gt;ISENABLER[]</a>   </td><td class="markdownTableBodyLeft">ICDISER   </td><td class="markdownTableBodyLeft">GICD_ISENABLERn   </td><td class="markdownTableBodyLeft">ICDISERn    </td></tr>
 265 <tr class="markdownTableRowEven">
 266 <td class="markdownTableBodyLeft"><a class="el" href="structGICDistributor__Type.html#a390fa9f2f460951b2c6094932d890807">GICDistributor-&gt;ICENABLER[]</a>   </td><td class="markdownTableBodyLeft">ICDICER   </td><td class="markdownTableBodyLeft">GICD_ICENABLERn   </td><td class="markdownTableBodyLeft">ICDICERn    </td></tr>
 267 <tr class="markdownTableRowOdd">
 268 <td class="markdownTableBodyLeft"><a class="el" href="structGICDistributor__Type.html#a1c15cd75ce30d8946792e2a1a19556a5">GICDistributor-&gt;ISPENDR[]</a>   </td><td class="markdownTableBodyLeft">ICDISPR   </td><td class="markdownTableBodyLeft">GICD_ISPENDRn   </td><td class="markdownTableBodyLeft">ICDISPRn    </td></tr>
 269 <tr class="markdownTableRowEven">
 270 <td class="markdownTableBodyLeft"><a class="el" href="structGICDistributor__Type.html#a0155cb4637845258e4ee76cd93cca2a6">GICDistributor-&gt;ICPENDR[]</a>   </td><td class="markdownTableBodyLeft">ICDICPR   </td><td class="markdownTableBodyLeft">GICD_ICPENDRn   </td><td class="markdownTableBodyLeft">ICDICPRn    </td></tr>
 271 <tr class="markdownTableRowOdd">
 272 <td class="markdownTableBodyLeft"><a class="el" href="structGICDistributor__Type.html#a5eb8e1ef5a88293e2759c41f6057ccc4">GICDistributor-&gt;ISACTIVER[]</a>   </td><td class="markdownTableBodyLeft">ICDABR   </td><td class="markdownTableBodyLeft">GICD_ISACTIVERn   </td><td class="markdownTableBodyLeft">ICDABRn    </td></tr>
 273 <tr class="markdownTableRowEven">
 274 <td class="markdownTableBodyLeft"><a class="el" href="structGICDistributor__Type.html#ac0fd4c1ad19b5a332e403bb9966ba967">GICDistributor-&gt;ICACTIVER[]</a>   </td><td class="markdownTableBodyLeft"></td><td class="markdownTableBodyLeft">GICD_ICACTIVERn   </td><td class="markdownTableBodyLeft"></td></tr>
 275 <tr class="markdownTableRowOdd">
 276 <td class="markdownTableBodyLeft"><a class="el" href="structGICDistributor__Type.html#a08fa902293567e85dc6398dab58afaa9">GICDistributor-&gt;IPRIORITYR[]</a>   </td><td class="markdownTableBodyLeft">ICDIPR   </td><td class="markdownTableBodyLeft">GICD_IPRIORITYRn   </td><td class="markdownTableBodyLeft">ICDIPRn    </td></tr>
 277 <tr class="markdownTableRowEven">
 278 <td class="markdownTableBodyLeft"><a class="el" href="structGICDistributor__Type.html#a6f1b07d48d3a9199f2effec8492f721c">GICDistributor-&gt;ITARGETSR[]</a>   </td><td class="markdownTableBodyLeft">ICDIPTR   </td><td class="markdownTableBodyLeft">GICD_ITARGETSRn   </td><td class="markdownTableBodyLeft">ICDIPTRn    </td></tr>
 279 <tr class="markdownTableRowOdd">
 280 <td class="markdownTableBodyLeft"><a class="el" href="structGICDistributor__Type.html#a9b306a630388c795d3cd32fc2e23a2b5">GICDistributor-&gt;ICFGR[]</a>   </td><td class="markdownTableBodyLeft">ICDICFR   </td><td class="markdownTableBodyLeft">GICD_ICFGRn   </td><td class="markdownTableBodyLeft">ICDICFRn    </td></tr>
 281 <tr class="markdownTableRowEven">
 282 <td class="markdownTableBodyLeft"><a class="el" href="structGICDistributor__Type.html#ae9eeb19ca95d0b95828f1f98700b5689">GICDistributor-&gt;IGRPMODR[0]</a>   </td><td class="markdownTableBodyLeft">ICDPPIS   </td><td class="markdownTableBodyLeft">GICD_PPISR   </td><td class="markdownTableBodyLeft">ppi_status    </td></tr>
 283 <tr class="markdownTableRowOdd">
 284 <td class="markdownTableBodyLeft"><a class="el" href="structGICDistributor__Type.html#ae9eeb19ca95d0b95828f1f98700b5689">GICDistributor-&gt;IGRPMODR[31:1]</a>   </td><td class="markdownTableBodyLeft">ICDSPIS   </td><td class="markdownTableBodyLeft">GICD_SPISRn   </td><td class="markdownTableBodyLeft">spi_status    </td></tr>
 285 <tr class="markdownTableRowEven">
 286 <td class="markdownTableBodyLeft"><a class="el" href="structGICDistributor__Type.html#a644abefb7064e434db20cc6dab5fe5f1">GICDistributor-&gt;NSACR[]</a>   </td><td class="markdownTableBodyLeft"></td><td class="markdownTableBodyLeft"></td><td class="markdownTableBodyLeft"></td></tr>
 287 <tr class="markdownTableRowOdd">
 288 <td class="markdownTableBodyLeft"><a class="el" href="structGICDistributor__Type.html#a6ac65c4a5394926cc9518753a00d4da1">GICDistributor-&gt;SGIR</a>   </td><td class="markdownTableBodyLeft">ICDSGIR   </td><td class="markdownTableBodyLeft">GICD_SGIR   </td><td class="markdownTableBodyLeft">ICDSGIR    </td></tr>
 289 <tr class="markdownTableRowEven">
 290 <td class="markdownTableBodyLeft"><a class="el" href="structGICDistributor__Type.html#a644a70cf4c12093c0277ce01f194b69b">GICDistributor-&gt;CPENDSGIR[]</a>   </td><td class="markdownTableBodyLeft"></td><td class="markdownTableBodyLeft">GICD_CPENDSGIRn   </td><td class="markdownTableBodyLeft"></td></tr>
 291 <tr class="markdownTableRowOdd">
 292 <td class="markdownTableBodyLeft"><a class="el" href="structGICDistributor__Type.html#ae40b4a50d9766c2bbf57441f68094f41">GICDistributor-&gt;SPENDSGIR[]</a>   </td><td class="markdownTableBodyLeft"></td><td class="markdownTableBodyLeft">GICD_SPENDSGIRn   </td><td class="markdownTableBodyLeft"></td></tr>
 293 <tr class="markdownTableRowEven">
 294 <td class="markdownTableBodyLeft"><a class="el" href="structGICDistributor__Type.html#a73e0c679e5f45710deea474ab0d39cdb">GICDistributor-&gt;IROUTER[]</a>   </td><td class="markdownTableBodyLeft"></td><td class="markdownTableBodyLeft"></td><td class="markdownTableBodyLeft"></td></tr>
 295 <tr class="markdownTableRowOdd">
 296 <td class="markdownTableBodyLeft"><b>GIC Interface</b>   </td><td class="markdownTableBodyLeft"></td><td class="markdownTableBodyLeft"></td><td class="markdownTableBodyLeft"></td></tr>
 297 <tr class="markdownTableRowEven">
 298 <td class="markdownTableBodyLeft"><a class="el" href="structGICInterface__Type.html#a5969edab40aa24e4d96e072af187a3a9">GICInterface-&gt;CTLR</a>   </td><td class="markdownTableBodyLeft">ICPICR   </td><td class="markdownTableBodyLeft">GICC_CTLR   </td><td class="markdownTableBodyLeft">ICCICR    </td></tr>
 299 <tr class="markdownTableRowOdd">
 300 <td class="markdownTableBodyLeft"><a class="el" href="structGICInterface__Type.html#a0edadabc6e3ce1f36d820f0b52bc143b">GICInterface-&gt;PMR</a>   </td><td class="markdownTableBodyLeft">ICCIPMR   </td><td class="markdownTableBodyLeft">GICC_PMRn   </td><td class="markdownTableBodyLeft">ICCPMR    </td></tr>
 301 <tr class="markdownTableRowEven">
 302 <td class="markdownTableBodyLeft"><a class="el" href="structGICInterface__Type.html#a949317484547dc1db89c9f7ab40d1829">GICInterface-&gt;BPR</a>   </td><td class="markdownTableBodyLeft">ICCBPR   </td><td class="markdownTableBodyLeft">GICC_BPR   </td><td class="markdownTableBodyLeft">ICCBPR    </td></tr>
 303 <tr class="markdownTableRowOdd">
 304 <td class="markdownTableBodyLeft"><a class="el" href="structGICInterface__Type.html#aa48569605fc0c163e1db35321b4c76ea">GICInterface-&gt;IAR</a>   </td><td class="markdownTableBodyLeft">ICCIAR   </td><td class="markdownTableBodyLeft">GICC_IAR   </td><td class="markdownTableBodyLeft">ICCIAR    </td></tr>
 305 <tr class="markdownTableRowEven">
 306 <td class="markdownTableBodyLeft"><a class="el" href="structGICInterface__Type.html#a4b9baa43aae026438bad64e63df17cdb">GICInterface-&gt;EOIR</a>   </td><td class="markdownTableBodyLeft">ICCEOIR   </td><td class="markdownTableBodyLeft">GICC_EOIR   </td><td class="markdownTableBodyLeft">ICCEOIR    </td></tr>
 307 <tr class="markdownTableRowOdd">
 308 <td class="markdownTableBodyLeft"><a class="el" href="structGICInterface__Type.html#a37762d42768ecb3d1302f34abc7f2821">GICInterface-&gt;RPR</a>   </td><td class="markdownTableBodyLeft">ICCRPR   </td><td class="markdownTableBodyLeft">GICC_RPR   </td><td class="markdownTableBodyLeft">ICCRPR    </td></tr>
 309 <tr class="markdownTableRowEven">
 310 <td class="markdownTableBodyLeft"><a class="el" href="structGICInterface__Type.html#af793cd280a74bf73cca8c4fedfc329d6">GICInterface-&gt;HPPIR</a>   </td><td class="markdownTableBodyLeft">ICCHPIR   </td><td class="markdownTableBodyLeft">GICC_HPPIR   </td><td class="markdownTableBodyLeft">ICCHPIR    </td></tr>
 311 <tr class="markdownTableRowOdd">
 312 <td class="markdownTableBodyLeft"><a class="el" href="structGICInterface__Type.html#a6d3ca9eaae5e0ac38f20846a1e67180d">GICInterface-&gt;ABPR</a>   </td><td class="markdownTableBodyLeft">ICCABPR   </td><td class="markdownTableBodyLeft">GICC_ABPR   </td><td class="markdownTableBodyLeft">ICCABPR    </td></tr>
 313 <tr class="markdownTableRowEven">
 314 <td class="markdownTableBodyLeft"><a class="el" href="structGICInterface__Type.html#a849e9ead6e9ced78dc6f0ba9256dd5a6">GICInterface-&gt;AIAR</a>   </td><td class="markdownTableBodyLeft"></td><td class="markdownTableBodyLeft">GICC_AIAR   </td><td class="markdownTableBodyLeft"></td></tr>
 315 <tr class="markdownTableRowOdd">
 316 <td class="markdownTableBodyLeft"><a class="el" href="structGICInterface__Type.html#a89d5a920c2b91b4b7bd0312ba4c38a89">GICInterface-&gt;AEOIR</a>   </td><td class="markdownTableBodyLeft"></td><td class="markdownTableBodyLeft">GICC_AEOIR   </td><td class="markdownTableBodyLeft"></td></tr>
 317 <tr class="markdownTableRowEven">
 318 <td class="markdownTableBodyLeft"><a class="el" href="structGICInterface__Type.html#a12f25dec95ab3dd13a477573fab4b9c8">GICInterface-&gt;AHPPIR</a>   </td><td class="markdownTableBodyLeft"></td><td class="markdownTableBodyLeft">GICC_AHPPIR   </td><td class="markdownTableBodyLeft"></td></tr>
 319 <tr class="markdownTableRowOdd">
 320 <td class="markdownTableBodyLeft"><a class="el" href="structGICInterface__Type.html#abd978b408fb69b7887be2c422f48ce7e">GICInterface-&gt;STATUSR</a>   </td><td class="markdownTableBodyLeft"></td><td class="markdownTableBodyLeft"></td><td class="markdownTableBodyLeft"></td></tr>
 321 <tr class="markdownTableRowEven">
 322 <td class="markdownTableBodyLeft"><a class="el" href="structGICInterface__Type.html#aebae4bdcd3930372d639b85c5c9301e8">GICInterface-&gt;APR[]</a>   </td><td class="markdownTableBodyLeft"></td><td class="markdownTableBodyLeft">GICC_APR0   </td><td class="markdownTableBodyLeft"></td></tr>
 323 <tr class="markdownTableRowOdd">
 324 <td class="markdownTableBodyLeft"><a class="el" href="structGICInterface__Type.html#ade3473ace2a8bf7c79a0251457be20f4">GICInterface-&gt;NSAPR[]</a>   </td><td class="markdownTableBodyLeft"></td><td class="markdownTableBodyLeft">GICC_NSAPR0   </td><td class="markdownTableBodyLeft"></td></tr>
 325 <tr class="markdownTableRowEven">
 326 <td class="markdownTableBodyLeft"><a class="el" href="structGICInterface__Type.html#aee78d0b6f64a7b47fbd730aabfcc86cf">GICInterface-&gt;IIDR</a>   </td><td class="markdownTableBodyLeft">ICCIIDR   </td><td class="markdownTableBodyLeft">GICC_IIDR   </td><td class="markdownTableBodyLeft">ICCIDR    </td></tr>
 327 <tr class="markdownTableRowOdd">
 328 <td class="markdownTableBodyLeft"><a class="el" href="structGICInterface__Type.html#a554bd1f88421df3189c664b9fd9c02aa">GICInterface-&gt;DIR</a>   </td><td class="markdownTableBodyLeft"></td><td class="markdownTableBodyLeft">GICC_DIR   </td><td class="markdownTableBodyLeft"></td></tr>
 329 </table>
 330 <h2 class="groupheader">Macro Definition Documentation</h2>
 331 <a id="ga82e193c0016a9377274756b2673464a6" name="ga82e193c0016a9377274756b2673464a6"></a>
 332 <h2 class="memtitle"><span class="permalink"><a href="#ga82e193c0016a9377274756b2673464a6">&#9670;&#160;</a></span>GICDistributor</h2>
 333
 334 <div class="memitem">
 335 <div class="memproto">
 336       <table class="memname">
 337         <tr>
 338           <td class="memname">#define GICDistributor&#160;&#160;&#160;((<a class="el" href="structGICDistributor__Type.html">GICDistributor_Type</a>      *)     GIC_DISTRIBUTOR_BASE )</td>
 339         </tr>
 340       </table>
 341 </div><div class="memdoc">
 342
 343 <p>GIC Distributor register set access pointer. </p>
 344 <p>Use GICDistributor to access the GIC Distributor registers.</p>
 345 <p><b>Example:</b> </p><div class="fragment"><div class="line"><a class="code hl_define" href="group__GIC__functions.html#ga82e193c0016a9377274756b2673464a6">GICDistributor</a>-&gt;CTRL |= 1; <span class="comment">// Enable group 0 interrupts</span></div>
 346 <div class="ttc" id="agroup__GIC__functions_html_ga82e193c0016a9377274756b2673464a6"><div class="ttname"><a href="group__GIC__functions.html#ga82e193c0016a9377274756b2673464a6">GICDistributor</a></div><div class="ttdeci">#define GICDistributor</div><div class="ttdoc">GIC Distributor register set access pointer.</div></div>
 347 </div><!-- fragment -->
 348 </div>
 349 </div>
 350 <a id="ga31a083dbdc5cb84178dbf184286180e3" name="ga31a083dbdc5cb84178dbf184286180e3"></a>
 351 <h2 class="memtitle"><span class="permalink"><a href="#ga31a083dbdc5cb84178dbf184286180e3">&#9670;&#160;</a></span>GICInterface</h2>
 352
 353 <div class="memitem">
 354 <div class="memproto">
 355       <table class="memname">
 356         <tr>
 357           <td class="memname">#define GICInterface&#160;&#160;&#160;((<a class="el" href="structGICInterface__Type.html">GICInterface_Type</a>        *)     GIC_INTERFACE_BASE )</td>
 358         </tr>
 359       </table>
 360 </div><div class="memdoc">
 361
 362 <p>GIC Interface register set access pointer. </p>
 363 <p>Use GICInterface to access the GIC Interface registers.</p>
 364 <p><b>Example:</b> </p><div class="fragment"><div class="line"><a class="code hl_define" href="group__GIC__functions.html#ga31a083dbdc5cb84178dbf184286180e3">GICInterface</a>-&gt;CTLR |= 1; <span class="comment">// Enable interrupt signaling</span></div>
 365 <div class="ttc" id="agroup__GIC__functions_html_ga31a083dbdc5cb84178dbf184286180e3"><div class="ttname"><a href="group__GIC__functions.html#ga31a083dbdc5cb84178dbf184286180e3">GICInterface</a></div><div class="ttdeci">#define GICInterface</div><div class="ttdoc">GIC Interface register set access pointer.</div></div>
 366 </div><!-- fragment -->
 367 </div>
 368 </div>
 369 <h2 class="groupheader">Function Documentation</h2>
 370 <a id="gafc08bbc58b25fef0d24003313fd16eb8" name="gafc08bbc58b25fef0d24003313fd16eb8"></a>
 371 <h2 class="memtitle"><span class="permalink"><a href="#gafc08bbc58b25fef0d24003313fd16eb8">&#9670;&#160;</a></span>GIC_AcknowledgePending()</h2>
 372
 373 <div class="memitem">
 374 <div class="memproto">
 375       <table class="memname">
 376         <tr>
 377           <td class="memname">__STATIC_INLINE <a class="el" href="group__irq__ctrl__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> GIC_AcknowledgePending </td>
 378           <td>(</td>
 379           <td class="paramtype">void&#160;</td>
 380           <td class="paramname"></td><td>)</td>
 381           <td></td>
 382         </tr>
 383       </table>
 384 </div><div class="memdoc">
 385
 386 <p>Read the CPU's IAR register. </p>
 387 <dl class="section return"><dt>Returns</dt><dd><a class="el" href="structGICInterface__Type.html#aa48569605fc0c163e1db35321b4c76ea" title="Offset: 0x00C (R/ ) Interrupt Acknowledge Register.">GICInterface_Type::IAR</a></dd></dl>
 388 <p>Provides the interrupt number of the highest priority interrupt pending. A read of this register acts as an acknowledge for the interrupt.</p>
 389 <p>The read returns a spurious interrupt number of 1023 if any of the following apply:</p><ul>
 390 <li>Forwarding of interrupts by the Distributor to the CPU interface is disabled.</li>
 391 <li>Signaling of interrupts by the CPU interface to the connected PE is disabled.</li>
 392 <li>There are no pending interrupts on the CPU interface with sufficient priority for the interface to signal it to the PE.</li>
 393 </ul>
 394 <dl class="section see"><dt>See also</dt><dd><a class="el" href="group__GIC__functions.html#gac23f090f572a058b4a737f6613ded9cd" title="Writes the given interrupt number to the CPU&#39;s EOIR register.">GIC_EndInterrupt</a> </dd></dl>
 395
 396 </div>
 397 </div>
 398 <a id="ga5ad17ad70f23d1ff36015ffac33d383d" name="ga5ad17ad70f23d1ff36015ffac33d383d"></a>
 399 <h2 class="memtitle"><span class="permalink"><a href="#ga5ad17ad70f23d1ff36015ffac33d383d">&#9670;&#160;</a></span>GIC_ClearPendingIRQ()</h2>
 400
 401 <div class="memitem">
 402 <div class="memproto">
 403       <table class="memname">
 404         <tr>
 405           <td class="memname">__STATIC_INLINE void GIC_ClearPendingIRQ </td>
 406           <td>(</td>
 407           <td class="paramtype"><a class="el" href="group__irq__ctrl__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a>&#160;</td>
 408           <td class="paramname"><em>IRQn</em></td><td>)</td>
 409           <td></td>
 410         </tr>
 411       </table>
 412 </div><div class="memdoc">
 413
 414 <p>Clears the given interrupt from being pending using GIC's ICPENDR register. </p>
 415 <dl class="params"><dt>Parameters</dt><dd>
 416   <table class="params">
 417     <tr><td class="paramdir">[in]</td><td class="paramname">IRQn</td><td>The interrupt to be enabled.</td></tr>
 418   </table>
 419   </dd>
 420 </dl>
 421 <p>Removes the pending state from the corresponding interrupt. </p>
 422
 423 </div>
 424 </div>
 425 <a id="ga1c93f8af9f428cda8ec066bf4bfbade9" name="ga1c93f8af9f428cda8ec066bf4bfbade9"></a>
 426 <h2 class="memtitle"><span class="permalink"><a href="#ga1c93f8af9f428cda8ec066bf4bfbade9">&#9670;&#160;</a></span>GIC_CPUInterfaceInit()</h2>
 427
 428 <div class="memitem">
 429 <div class="memproto">
 430       <table class="memname">
 431         <tr>
 432           <td class="memname">__STATIC_INLINE void GIC_CPUInterfaceInit </td>
 433           <td>(</td>
 434           <td class="paramtype">void&#160;</td>
 435           <td class="paramname"></td><td>)</td>
 436           <td></td>
 437         </tr>
 438       </table>
 439 </div><div class="memdoc">
 440
 441 <p>Initialize the CPU's interrupt interface. </p>
 442 <p>All software generated (SGIs) and private peripheral interrupts (PPIs) are initialized to be</p><ul>
 443 <li>disabled</li>
 444 <li>level-sensitive, 1-N model</li>
 445 <li>priority 0x7F and the interrupt interface is enabled.</li>
 446 </ul>
 447 <p>The binary point is set to zero.</p>
 448 <p>The interrupt priority mask is set to 0xFF.</p>
 449 <dl class="section see"><dt>See also</dt><dd><a class="el" href="group__GIC__functions.html#ga2102399d255690c0674209a6faeec13d" title="Disables the given interrupt using GIC&#39;s ICENABLER register.">GIC_DisableIRQ</a><br  />
 450 GIC_SetLevelModel<br  />
 451 <a class="el" href="group__GIC__functions.html#ga27b9862b58290276851ec669cabf0f71" title="Set the priority for the given interrupt in the GIC&#39;s IPRIORITYR register.">GIC_SetPriority</a><br  />
 452 <a class="el" href="group__GIC__functions.html#ga758e5600d7f891e4f2f551bb45d07fce" title="Enable the CPU&#39;s interrupt interface.">GIC_EnableInterface</a><br  />
 453 <a class="el" href="group__GIC__functions.html#ga5dfedeb5403656a77e0fef4e1cc2c0c6" title="Configures the group priority and subpriority split point using CPU&#39;s BPR register.">GIC_SetBinaryPoint</a><br  />
 454 <a class="el" href="group__GIC__functions.html#gaa5eb0e76dbc89596e1ce47ddb9edc4a0" title="Set the interrupt priority mask using CPU&#39;s PMR register.">GIC_SetInterfacePriorityMask</a><br  />
 455 </dd></dl>
 456
 457 </div>
 458 </div>
 459 <a id="ga363311538d4a4d750197b9936505d466" name="ga363311538d4a4d750197b9936505d466"></a>
 460 <h2 class="memtitle"><span class="permalink"><a href="#ga363311538d4a4d750197b9936505d466">&#9670;&#160;</a></span>GIC_DisableDistributor()</h2>
 461
 462 <div class="memitem">
 463 <div class="memproto">
 464       <table class="memname">
 465         <tr>
 466           <td class="memname">__STATIC_INLINE void GIC_DisableDistributor </td>
 467           <td>(</td>
 468           <td class="paramtype">void&#160;</td>
 469           <td class="paramname"></td><td>)</td>
 470           <td></td>
 471         </tr>
 472       </table>
 473 </div><div class="memdoc">
 474
 475 <p>Disable the interrupt distributor using the GIC's CTLR register. </p>
 476 <p>Globally disable the forwarding of interrupts to the CPU interfaces. </p><dl class="section see"><dt>See also</dt><dd><a class="el" href="group__GIC__functions.html#ga0f44df6823e90178183257e096e5cac6" title="Enable the interrupt distributor using the GIC&#39;s CTLR register.">GIC_EnableDistributor</a> </dd></dl>
 477
 478 </div>
 479 </div>
 480 <a id="ga0605877ad627c1f4320e518725fd103e" name="ga0605877ad627c1f4320e518725fd103e"></a>
 481 <h2 class="memtitle"><span class="permalink"><a href="#ga0605877ad627c1f4320e518725fd103e">&#9670;&#160;</a></span>GIC_DisableInterface()</h2>
 482
 483 <div class="memitem">
 484 <div class="memproto">
 485       <table class="memname">
 486         <tr>
 487           <td class="memname">__STATIC_INLINE void GIC_DisableInterface </td>
 488           <td>(</td>
 489           <td class="paramtype">void&#160;</td>
 490           <td class="paramname"></td><td>)</td>
 491           <td></td>
 492         </tr>
 493       </table>
 494 </div><div class="memdoc">
 495
 496 <p>Disable the CPU's interrupt interface. </p>
 497 <p>Resets the Enable bit in the local CPUs <a class="el" href="structGICInterface__Type.html#a5969edab40aa24e4d96e072af187a3a9">CTLR</a> register. Only the CPU executing the call is affected. </p>
 498
 499 </div>
 500 </div>
 501 <a id="ga2102399d255690c0674209a6faeec13d" name="ga2102399d255690c0674209a6faeec13d"></a>
 502 <h2 class="memtitle"><span class="permalink"><a href="#ga2102399d255690c0674209a6faeec13d">&#9670;&#160;</a></span>GIC_DisableIRQ()</h2>
 503
 504 <div class="memitem">
 505 <div class="memproto">
 506       <table class="memname">
 507         <tr>
 508           <td class="memname">__STATIC_INLINE void GIC_DisableIRQ </td>
 509           <td>(</td>
 510           <td class="paramtype"><a class="el" href="group__irq__ctrl__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a>&#160;</td>
 511           <td class="paramname"><em>IRQn</em></td><td>)</td>
 512           <td></td>
 513         </tr>
 514       </table>
 515 </div><div class="memdoc">
 516
 517 <p>Disables the given interrupt using GIC's ICENABLER register. </p>
 518 <dl class="params"><dt>Parameters</dt><dd>
 519   <table class="params">
 520     <tr><td class="paramdir">[in]</td><td class="paramname">IRQn</td><td>The interrupt to be disabled.</td></tr>
 521   </table>
 522   </dd>
 523 </dl>
 524 <p>Disables forwarding of the corresponding interrupt to the CPU interfaces. </p>
 525
 526 </div>
 527 </div>
 528 <a id="ga07acd03d02683bb6e33e7f57f5f371d1" name="ga07acd03d02683bb6e33e7f57f5f371d1"></a>
 529 <h2 class="memtitle"><span class="permalink"><a href="#ga07acd03d02683bb6e33e7f57f5f371d1">&#9670;&#160;</a></span>GIC_DistInit()</h2>
 530
 531 <div class="memitem">
 532 <div class="memproto">
 533       <table class="memname">
 534         <tr>
 535           <td class="memname">__STATIC_INLINE void GIC_DistInit </td>
 536           <td>(</td>
 537           <td class="paramtype">void&#160;</td>
 538           <td class="paramname"></td><td>)</td>
 539           <td></td>
 540         </tr>
 541       </table>
 542 </div><div class="memdoc">
 543
 544 <p>Initialize the interrupt distributor. </p>
 545 <p>All shared peripheral interrupts (SPIs) are initialized to be</p><ul>
 546 <li>disabled</li>
 547 <li>level-sensitive, 1-N model</li>
 548 <li>priority 0x7F</li>
 549 <li>targeting CPU0 and the distributor is enabled.</li>
 550 </ul>
 551 <dl class="section see"><dt>See also</dt><dd><a class="el" href="group__GIC__functions.html#ga2102399d255690c0674209a6faeec13d" title="Disables the given interrupt using GIC&#39;s ICENABLER register.">GIC_DisableIRQ</a><br  />
 552 GIC_SetLevelModel<br  />
 553 <a class="el" href="group__GIC__functions.html#ga27b9862b58290276851ec669cabf0f71" title="Set the priority for the given interrupt in the GIC&#39;s IPRIORITYR register.">GIC_SetPriority</a><br  />
 554 <a class="el" href="group__GIC__functions.html#gae86bba705d0d4ef812b84d29d7b3ca2b" title="Sets the GIC&#39;s ITARGETSR register for the given interrupt.">GIC_SetTarget</a><br  />
 555 <a class="el" href="group__GIC__functions.html#ga0f44df6823e90178183257e096e5cac6" title="Enable the interrupt distributor using the GIC&#39;s CTLR register.">GIC_EnableDistributor</a> </dd></dl>
 556
 557 </div>
 558 </div>
 559 <a id="ga1481d0cdf78f8c93fb2a710a519c4dc6" name="ga1481d0cdf78f8c93fb2a710a519c4dc6"></a>
 560 <h2 class="memtitle"><span class="permalink"><a href="#ga1481d0cdf78f8c93fb2a710a519c4dc6">&#9670;&#160;</a></span>GIC_DistributorImplementer()</h2>
 561
 562 <div class="memitem">
 563 <div class="memproto">
 564       <table class="memname">
 565         <tr>
 566           <td class="memname">__STATIC_INLINE uint32_t GIC_DistributorImplementer </td>
 567           <td>(</td>
 568           <td class="paramtype">void&#160;</td>
 569           <td class="paramname"></td><td>)</td>
 570           <td></td>
 571         </tr>
 572       </table>
 573 </div><div class="memdoc">
 574
 575 <p>Reads the GIC's IIDR register. </p>
 576 <dl class="section return"><dt>Returns</dt><dd><a class="el" href="structGICDistributor__Type.html#acebf65dae4cb82cd3c7deeefca9c9722" title="Offset: 0x008 (R/ ) Distributor Implementer Identification Register.">GICDistributor_Type::IIDR</a></dd></dl>
 577 <p>Provides information about the implementer and revision of the Distributor. </p>
 578
 579 </div>
 580 </div>
 581 <a id="ga7d93d39736ef5e379e6511430ee6e75f" name="ga7d93d39736ef5e379e6511430ee6e75f"></a>
 582 <h2 class="memtitle"><span class="permalink"><a href="#ga7d93d39736ef5e379e6511430ee6e75f">&#9670;&#160;</a></span>GIC_DistributorInfo()</h2>
 583
 584 <div class="memitem">
 585 <div class="memproto">
 586       <table class="memname">
 587         <tr>
 588           <td class="memname">__STATIC_INLINE uint32_t GIC_DistributorInfo </td>
 589           <td>(</td>
 590           <td class="paramtype">void&#160;</td>
 591           <td class="paramname"></td><td>)</td>
 592           <td></td>
 593         </tr>
 594       </table>
 595 </div><div class="memdoc">
 596
 597 <p>Read the GIC's TYPER register. </p>
 598 <dl class="section return"><dt>Returns</dt><dd><a class="el" href="structGICDistributor__Type.html#a405823d97dc90dd9d397a3980e2cd207" title="Offset: 0x004 (R/ ) Interrupt Controller Type Register.">GICDistributor_Type::TYPER</a></dd></dl>
 599 <p>Provides information about the configuration of the GIC. It indicates:</p><ul>
 600 <li>whether the GIC implements the Security Extensions</li>
 601 <li>the maximum number of interrupt IDs that the GIC supports</li>
 602 <li>the number of CPU interfaces implemented</li>
 603 <li>if the GIC implements the Security Extensions, the maximum number of implemented Lockable Shared Peripheral Interrupts (LSPIs). </li>
 604 </ul>
 605
 606 </div>
 607 </div>
 608 <a id="ga818881f69aae3eef6eb996bee6f6c63e" name="ga818881f69aae3eef6eb996bee6f6c63e"></a>
 609 <h2 class="memtitle"><span class="permalink"><a href="#ga818881f69aae3eef6eb996bee6f6c63e">&#9670;&#160;</a></span>GIC_Enable()</h2>
 610
 611 <div class="memitem">
 612 <div class="memproto">
 613       <table class="memname">
 614         <tr>
 615           <td class="memname">__STATIC_INLINE void GIC_Enable </td>
 616           <td>(</td>
 617           <td class="paramtype">void&#160;</td>
 618           <td class="paramname"></td><td>)</td>
 619           <td></td>
 620         </tr>
 621       </table>
 622 </div><div class="memdoc">
 623
 624 <p>Initialize and enable the GIC. </p>
 625 <p>Initializes the distributor and the cpu interface.</p>
 626 <dl class="section see"><dt>See also</dt><dd><a class="el" href="group__GIC__functions.html#ga07acd03d02683bb6e33e7f57f5f371d1" title="Initialize the interrupt distributor.">GIC_DistInit</a> <a class="el" href="group__GIC__functions.html#ga1c93f8af9f428cda8ec066bf4bfbade9" title="Initialize the CPU&#39;s interrupt interface.">GIC_CPUInterfaceInit</a> </dd></dl>
 627
 628 </div>
 629 </div>
 630 <a id="ga0f44df6823e90178183257e096e5cac6" name="ga0f44df6823e90178183257e096e5cac6"></a>
 631 <h2 class="memtitle"><span class="permalink"><a href="#ga0f44df6823e90178183257e096e5cac6">&#9670;&#160;</a></span>GIC_EnableDistributor()</h2>
 632
 633 <div class="memitem">
 634 <div class="memproto">
 635       <table class="memname">
 636         <tr>
 637           <td class="memname">__STATIC_INLINE void GIC_EnableDistributor </td>
 638           <td>(</td>
 639           <td class="paramtype">void&#160;</td>
 640           <td class="paramname"></td><td>)</td>
 641           <td></td>
 642         </tr>
 643       </table>
 644 </div><div class="memdoc">
 645
 646 <p>Enable the interrupt distributor using the GIC's CTLR register. </p>
 647 <p>Globally enable the forwarding of interrupts to the CPU interfaces. </p>
 648
 649 </div>
 650 </div>
 651 <a id="ga758e5600d7f891e4f2f551bb45d07fce" name="ga758e5600d7f891e4f2f551bb45d07fce"></a>
 652 <h2 class="memtitle"><span class="permalink"><a href="#ga758e5600d7f891e4f2f551bb45d07fce">&#9670;&#160;</a></span>GIC_EnableInterface()</h2>
 653
 654 <div class="memitem">
 655 <div class="memproto">
 656       <table class="memname">
 657         <tr>
 658           <td class="memname">__STATIC_INLINE void GIC_EnableInterface </td>
 659           <td>(</td>
 660           <td class="paramtype">void&#160;</td>
 661           <td class="paramname"></td><td>)</td>
 662           <td></td>
 663         </tr>
 664       </table>
 665 </div><div class="memdoc">
 666
 667 <p>Enable the CPU's interrupt interface. </p>
 668 <p>Sets the Enable bit in the local CPUs <a class="el" href="structGICInterface__Type.html#a5969edab40aa24e4d96e072af187a3a9">CTLR</a> register. Only the CPU executing the call is affected. </p>
 669
 670 </div>
 671 </div>
 672 <a id="gaeba215d9c4ec3599e0a168800288c3f3" name="gaeba215d9c4ec3599e0a168800288c3f3"></a>
 673 <h2 class="memtitle"><span class="permalink"><a href="#gaeba215d9c4ec3599e0a168800288c3f3">&#9670;&#160;</a></span>GIC_EnableIRQ()</h2>
 674
 675 <div class="memitem">
 676 <div class="memproto">
 677       <table class="memname">
 678         <tr>
 679           <td class="memname">__STATIC_INLINE void GIC_EnableIRQ </td>
 680           <td>(</td>
 681           <td class="paramtype"><a class="el" href="group__irq__ctrl__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a>&#160;</td>
 682           <td class="paramname"><em>IRQn</em></td><td>)</td>
 683           <td></td>
 684         </tr>
 685       </table>
 686 </div><div class="memdoc">
 687
 688 <p>Enables the given interrupt using GIC's ISENABLER register. </p>
 689 <dl class="params"><dt>Parameters</dt><dd>
 690   <table class="params">
 691     <tr><td class="paramdir">[in]</td><td class="paramname">IRQn</td><td>The interrupt to be enabled.</td></tr>
 692   </table>
 693   </dd>
 694 </dl>
 695 <p>Enables forwarding of the corresponding interrupt to the CPU interfaces. </p>
 696
 697 </div>
 698 </div>
 699 <a id="gac23f090f572a058b4a737f6613ded9cd" name="gac23f090f572a058b4a737f6613ded9cd"></a>
 700 <h2 class="memtitle"><span class="permalink"><a href="#gac23f090f572a058b4a737f6613ded9cd">&#9670;&#160;</a></span>GIC_EndInterrupt()</h2>
 701
 702 <div class="memitem">
 703 <div class="memproto">
 704       <table class="memname">
 705         <tr>
 706           <td class="memname">__STATIC_INLINE void GIC_EndInterrupt </td>
 707           <td>(</td>
 708           <td class="paramtype"><a class="el" href="group__irq__ctrl__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a>&#160;</td>
 709           <td class="paramname"><em>IRQn</em></td><td>)</td>
 710           <td></td>
 711         </tr>
 712       </table>
 713 </div><div class="memdoc">
 714
 715 <p>Writes the given interrupt number to the CPU's EOIR register. </p>
 716 <dl class="params"><dt>Parameters</dt><dd>
 717   <table class="params">
 718     <tr><td class="paramdir">[in]</td><td class="paramname">IRQn</td><td>The interrupt to be signaled as finished.</td></tr>
 719   </table>
 720   </dd>
 721 </dl>
 722 <p>A write to this register performs priority drop for the specified interrupt.</p>
 723 <p>For nested interrupts, the order of calls to this function must be the reverse of the order of interrupt acknowledgement, i.e. calls to <a class="el" href="group__GIC__functions.html#gafc08bbc58b25fef0d24003313fd16eb8">GIC_AcknowledgePending</a>. Behavior is UNPREDICTABLE if:</p><ul>
 724 <li>This ordering constraint is not maintained.</li>
 725 <li>The given interrupt number does not match an active interrupt, or the ID of a spurious interrupt.</li>
 726 <li>The given interrupt number does not match the last valid interrupt value returned by <a class="el" href="group__GIC__functions.html#gafc08bbc58b25fef0d24003313fd16eb8">GIC_AcknowledgePending</a>. </li>
 727 </ul>
 728
 729 </div>
 730 </div>
 731 <a id="gaa7046d8206ddd4696716726e68f85906" name="gaa7046d8206ddd4696716726e68f85906"></a>
 732 <h2 class="memtitle"><span class="permalink"><a href="#gaa7046d8206ddd4696716726e68f85906">&#9670;&#160;</a></span>GIC_GetBinaryPoint()</h2>
 733
 734 <div class="memitem">
 735 <div class="memproto">
 736       <table class="memname">
 737         <tr>
 738           <td class="memname">__STATIC_INLINE uint32_t GIC_GetBinaryPoint </td>
 739           <td>(</td>
 740           <td class="paramtype">void&#160;</td>
 741           <td class="paramname"></td><td>)</td>
 742           <td></td>
 743         </tr>
 744       </table>
 745 </div><div class="memdoc">
 746
 747 <p>Read the current group priority and subpriority split point from CPU's BPR register. </p>
 748 <dl class="section return"><dt>Returns</dt><dd><a class="el" href="structGICInterface__Type.html#a949317484547dc1db89c9f7ab40d1829" title="Offset: 0x008 (R/W) Binary Point Register.">GICInterface_Type::BPR</a></dd></dl>
 749 <dl class="section see"><dt>See also</dt><dd><a class="el" href="group__GIC__functions.html#ga5dfedeb5403656a77e0fef4e1cc2c0c6" title="Configures the group priority and subpriority split point using CPU&#39;s BPR register.">GIC_SetBinaryPoint</a> </dd></dl>
 750
 751 </div>
 752 </div>
 753 <a id="ga8bb27e1bab132a8df44190adb996c2a1" name="ga8bb27e1bab132a8df44190adb996c2a1"></a>
 754 <h2 class="memtitle"><span class="permalink"><a href="#ga8bb27e1bab132a8df44190adb996c2a1">&#9670;&#160;</a></span>GIC_GetHighPendingIRQ()</h2>
 755
 756 <div class="memitem">
 757 <div class="memproto">
 758       <table class="memname">
 759         <tr>
 760           <td class="memname">__STATIC_INLINE uint32_t GIC_GetHighPendingIRQ </td>
 761           <td>(</td>
 762           <td class="paramtype">void&#160;</td>
 763           <td class="paramname"></td><td>)</td>
 764           <td></td>
 765         </tr>
 766       </table>
 767 </div><div class="memdoc">
 768
 769 <p>Get the interrupt number of the highest interrupt pending from CPU's HPPIR register. </p>
 770 <dl class="section return"><dt>Returns</dt><dd><a class="el" href="structGICInterface__Type.html#af793cd280a74bf73cca8c4fedfc329d6" title="Offset: 0x018 (R/ ) Highest Priority Pending Interrupt Register.">GICInterface_Type::HPPIR</a> </dd></dl>
 771
 772 </div>
 773 </div>
 774 <a id="gaba1b2665cdda47fc0bc3d7b90690dc50" name="gaba1b2665cdda47fc0bc3d7b90690dc50"></a>
 775 <h2 class="memtitle"><span class="permalink"><a href="#gaba1b2665cdda47fc0bc3d7b90690dc50">&#9670;&#160;</a></span>GIC_GetInterfaceId()</h2>
 776
 777 <div class="memitem">
 778 <div class="memproto">
 779       <table class="memname">
 780         <tr>
 781           <td class="memname">__STATIC_INLINE uint32_t GIC_GetInterfaceId </td>
 782           <td>(</td>
 783           <td class="paramtype">void&#160;</td>
 784           <td class="paramname"></td><td>)</td>
 785           <td></td>
 786         </tr>
 787       </table>
 788 </div><div class="memdoc">
 789
 790 <p>Provides information about the implementer and revision of the CPU interface. </p>
 791 <dl class="section return"><dt>Returns</dt><dd><a class="el" href="structGICInterface__Type.html#aee78d0b6f64a7b47fbd730aabfcc86cf" title="Offset: 0x0FC (R/ ) CPU Interface Identification Register.">GICInterface_Type::IIDR</a> </dd></dl>
 792
 793 </div>
 794 </div>
 795 <a id="ga2c5f9e5637560fc9d5c29d772580a728" name="ga2c5f9e5637560fc9d5c29d772580a728"></a>
 796 <h2 class="memtitle"><span class="permalink"><a href="#ga2c5f9e5637560fc9d5c29d772580a728">&#9670;&#160;</a></span>GIC_GetInterfacePriorityMask()</h2>
 797
 798 <div class="memitem">
 799 <div class="memproto">
 800       <table class="memname">
 801         <tr>
 802           <td class="memname">__STATIC_INLINE uint32_t GIC_GetInterfacePriorityMask </td>
 803           <td>(</td>
 804           <td class="paramtype">void&#160;</td>
 805           <td class="paramname"></td><td>)</td>
 806           <td></td>
 807         </tr>
 808       </table>
 809 </div><div class="memdoc">
 810
 811 <p>Read the current interrupt priority mask from CPU's PMR register. </p>
 812 <dl class="section return"><dt>Returns</dt><dd><a class="el" href="structGICInterface__Type.html#a0edadabc6e3ce1f36d820f0b52bc143b" title="Offset: 0x004 (R/W) Interrupt Priority Mask Register.">GICInterface_Type::PMR</a></dd></dl>
 813 <dl class="section see"><dt>See also</dt><dd><a class="el" href="group__GIC__functions.html#gaa5eb0e76dbc89596e1ce47ddb9edc4a0" title="Set the interrupt priority mask using CPU&#39;s PMR register.">GIC_SetInterfacePriorityMask</a> </dd></dl>
 814
 815 </div>
 816 </div>
 817 <a id="gabc88483ecf94a2c222b644ecfa60eb9f" name="gabc88483ecf94a2c222b644ecfa60eb9f"></a>
 818 <h2 class="memtitle"><span class="permalink"><a href="#gabc88483ecf94a2c222b644ecfa60eb9f">&#9670;&#160;</a></span>GIC_GetIRQStatus()</h2>
 819
 820 <div class="memitem">
 821 <div class="memproto">
 822       <table class="memname">
 823         <tr>
 824           <td class="memname">__STATIC_INLINE uint32_t GIC_GetIRQStatus </td>
 825           <td>(</td>
 826           <td class="paramtype"><a class="el" href="group__irq__ctrl__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a>&#160;</td>
 827           <td class="paramname"><em>IRQn</em></td><td>)</td>
 828           <td></td>
 829         </tr>
 830       </table>
 831 </div><div class="memdoc">
 832
 833 <p>Get the status for a given interrupt. </p>
 834 <dl class="params"><dt>Parameters</dt><dd>
 835   <table class="params">
 836     <tr><td class="paramdir">[in]</td><td class="paramname">IRQn</td><td>The interrupt to get status for. </td></tr>
 837   </table>
 838   </dd>
 839 </dl>
 840 <dl class="section return"><dt>Returns</dt><dd>0 - not pending/active, 1 - pending, 2 - active, 3 - pending and active</dd></dl>
 841 <p>The return value is a combination of GIC's <a class="el" href="structGICDistributor__Type.html#a5eb8e1ef5a88293e2759c41f6057ccc4">ISACTIVER</a> and <a class="el" href="structGICDistributor__Type.html#a1c15cd75ce30d8946792e2a1a19556a5">ISPENDR</a> registers.</p>
 842 <p>Bit 0 denotes interrupts pending bit (interrupt should be handled) and bit 1 denotes interrupts active bit (interrupt is currently handled). </p>
 843
 844 </div>
 845 </div>
 846 <a id="ga397048004654f792649742f95bf8ae67" name="ga397048004654f792649742f95bf8ae67"></a>
 847 <h2 class="memtitle"><span class="permalink"><a href="#ga397048004654f792649742f95bf8ae67">&#9670;&#160;</a></span>GIC_GetPriority()</h2>
 848
 849 <div class="memitem">
 850 <div class="memproto">
 851       <table class="memname">
 852         <tr>
 853           <td class="memname">__STATIC_INLINE uint32_t GIC_GetPriority </td>
 854           <td>(</td>
 855           <td class="paramtype"><a class="el" href="group__irq__ctrl__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a>&#160;</td>
 856           <td class="paramname"><em>IRQn</em></td><td>)</td>
 857           <td></td>
 858         </tr>
 859       </table>
 860 </div><div class="memdoc">
 861
 862 <p>Read the current interrupt priority from GIC's IPRIORITYR register. </p>
 863 <dl class="params"><dt>Parameters</dt><dd>
 864   <table class="params">
 865     <tr><td class="paramdir">[in]</td><td class="paramname">IRQn</td><td>The interrupt to be queried.</td></tr>
 866   </table>
 867   </dd>
 868 </dl>
 869 <p>Can be used to retrieve the actual priority depending on the GIC implementation. </p><dl class="section see"><dt>See also</dt><dd><a class="el" href="group__GIC__functions.html#ga27b9862b58290276851ec669cabf0f71" title="Set the priority for the given interrupt in the GIC&#39;s IPRIORITYR register.">GIC_SetPriority</a> </dd></dl>
 870
 871 </div>
 872 </div>
 873 <a id="gafccf881f9517592f30489bcabcb738a8" name="gafccf881f9517592f30489bcabcb738a8"></a>
 874 <h2 class="memtitle"><span class="permalink"><a href="#gafccf881f9517592f30489bcabcb738a8">&#9670;&#160;</a></span>GIC_GetTarget()</h2>
 875
 876 <div class="memitem">
 877 <div class="memproto">
 878       <table class="memname">
 879         <tr>
 880           <td class="memname">__STATIC_INLINE uint32_t GIC_GetTarget </td>
 881           <td>(</td>
 882           <td class="paramtype"><a class="el" href="group__irq__ctrl__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a>&#160;</td>
 883           <td class="paramname"><em>IRQn</em></td><td>)</td>
 884           <td></td>
 885         </tr>
 886       </table>
 887 </div><div class="memdoc">
 888
 889 <p>Read the GIC's ITARGETSR register. </p>
 890 <dl class="params"><dt>Parameters</dt><dd>
 891   <table class="params">
 892     <tr><td class="paramdir">[in]</td><td class="paramname">IRQn</td><td>Interrupt to acquire the configuration for. </td></tr>
 893   </table>
 894   </dd>
 895 </dl>
 896 <dl class="section return"><dt>Returns</dt><dd><a class="el" href="structGICDistributor__Type.html#a6f1b07d48d3a9199f2effec8492f721c" title="Offset: 0x800 (R/W) Interrupt Targets Registers.">GICDistributor_Type::ITARGETSR</a></dd></dl>
 897 <p>Read the current interrupt to CPU assignment for the given interrupt. </p><dl class="section see"><dt>See also</dt><dd><a class="el" href="group__GIC__functions.html#gae86bba705d0d4ef812b84d29d7b3ca2b" title="Sets the GIC&#39;s ITARGETSR register for the given interrupt.">GIC_SetTarget</a> </dd></dl>
 898
 899 </div>
 900 </div>
 901 <a id="ga2de8850780af26e802ee4cc43e9da6e9" name="ga2de8850780af26e802ee4cc43e9da6e9"></a>
 902 <h2 class="memtitle"><span class="permalink"><a href="#ga2de8850780af26e802ee4cc43e9da6e9">&#9670;&#160;</a></span>GIC_SendSGI()</h2>
 903
 904 <div class="memitem">
 905 <div class="memproto">
 906       <table class="memname">
 907         <tr>
 908           <td class="memname">__STATIC_INLINE void GIC_SendSGI </td>
 909           <td>(</td>
 910           <td class="paramtype"><a class="el" href="group__irq__ctrl__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a>&#160;</td>
 911           <td class="paramname"><em>IRQn</em>, </td>
 912         </tr>
 913         <tr>
 914           <td class="paramkey"></td>
 915           <td></td>
 916           <td class="paramtype">uint32_t&#160;</td>
 917           <td class="paramname"><em>target_list</em>, </td>
 918         </tr>
 919         <tr>
 920           <td class="paramkey"></td>
 921           <td></td>
 922           <td class="paramtype">uint32_t&#160;</td>
 923           <td class="paramname"><em>filter_list</em>&#160;</td>
 924         </tr>
 925         <tr>
 926           <td></td>
 927           <td>)</td>
 928           <td></td><td></td>
 929         </tr>
 930       </table>
 931 </div><div class="memdoc">
 932
 933 <p>Generate a software interrupt using GIC's SGIR register. </p>
 934 <dl class="params"><dt>Parameters</dt><dd>
 935   <table class="params">
 936     <tr><td class="paramdir">[in]</td><td class="paramname">IRQn</td><td>Software interrupt to be generated. </td></tr>
 937     <tr><td class="paramdir">[in]</td><td class="paramname">target_list</td><td>List of CPUs the software interrupt should be forwarded to. </td></tr>
 938     <tr><td class="paramdir">[in]</td><td class="paramname">filter_list</td><td>Filter to be applied to determine interrupt receivers. </td></tr>
 939   </table>
 940   </dd>
 941 </dl>
 942
 943 </div>
 944 </div>
 945 <a id="ga5dfedeb5403656a77e0fef4e1cc2c0c6" name="ga5dfedeb5403656a77e0fef4e1cc2c0c6"></a>
 946 <h2 class="memtitle"><span class="permalink"><a href="#ga5dfedeb5403656a77e0fef4e1cc2c0c6">&#9670;&#160;</a></span>GIC_SetBinaryPoint()</h2>
 947
 948 <div class="memitem">
 949 <div class="memproto">
 950       <table class="memname">
 951         <tr>
 952           <td class="memname">__STATIC_INLINE void GIC_SetBinaryPoint </td>
 953           <td>(</td>
 954           <td class="paramtype">uint32_t&#160;</td>
 955           <td class="paramname"><em>binary_point</em></td><td>)</td>
 956           <td></td>
 957         </tr>
 958       </table>
 959 </div><div class="memdoc">
 960
 961 <p>Configures the group priority and subpriority split point using CPU's BPR register. </p>
 962 <dl class="params"><dt>Parameters</dt><dd>
 963   <table class="params">
 964     <tr><td class="paramdir">[in]</td><td class="paramname">binary_point</td><td>Amount of bits used as subpriority.</td></tr>
 965   </table>
 966   </dd>
 967 </dl>
 968 <p>The binary point defines the amount of priority bits used as a group priority and subpriorities.</p>
 969 <p>Interrupts sharing the same group priority do not preempt each other. But interrupts having a higher group priority (lower value) preempt interrups with a lower group priority.</p>
 970 <p>The subpriority defines the execution sequence of interrupts with the same group priority if multiple are pending at time. </p>
 971
 972 </div>
 973 </div>
 974 <a id="gaa5eb0e76dbc89596e1ce47ddb9edc4a0" name="gaa5eb0e76dbc89596e1ce47ddb9edc4a0"></a>
 975 <h2 class="memtitle"><span class="permalink"><a href="#gaa5eb0e76dbc89596e1ce47ddb9edc4a0">&#9670;&#160;</a></span>GIC_SetInterfacePriorityMask()</h2>
 976
 977 <div class="memitem">
 978 <div class="memproto">
 979       <table class="memname">
 980         <tr>
 981           <td class="memname">__STATIC_INLINE void GIC_SetInterfacePriorityMask </td>
 982           <td>(</td>
 983           <td class="paramtype">uint32_t&#160;</td>
 984           <td class="paramname"><em>priority</em></td><td>)</td>
 985           <td></td>
 986         </tr>
 987       </table>
 988 </div><div class="memdoc">
 989
 990 <p>Set the interrupt priority mask using CPU's PMR register. </p>
 991 <dl class="params"><dt>Parameters</dt><dd>
 992   <table class="params">
 993     <tr><td class="paramdir">[in]</td><td class="paramname">priority</td><td>Priority mask to be set.</td></tr>
 994   </table>
 995   </dd>
 996 </dl>
 997 <p>Only interrupts with a higher priority (lower values) than the value provided are signaled. </p>
 998
 999 </div>
1000 </div>
1001 <a id="ga18fbddf7f3594df141c97f61a71da47c" name="ga18fbddf7f3594df141c97f61a71da47c"></a>
1002 <h2 class="memtitle"><span class="permalink"><a href="#ga18fbddf7f3594df141c97f61a71da47c">&#9670;&#160;</a></span>GIC_SetPendingIRQ()</h2>
1003
1004 <div class="memitem">
1005 <div class="memproto">
1006       <table class="memname">
1007         <tr>
1008           <td class="memname">__STATIC_INLINE void GIC_SetPendingIRQ </td>
1009           <td>(</td>
1010           <td class="paramtype"><a class="el" href="group__irq__ctrl__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a>&#160;</td>
1011           <td class="paramname"><em>IRQn</em></td><td>)</td>
1012           <td></td>
1013         </tr>
1014       </table>
1015 </div><div class="memdoc">
1016
1017 <p>Sets the given interrupt as pending using GIC's ISPENDR register. </p>
1018 <dl class="params"><dt>Parameters</dt><dd>
1019   <table class="params">
1020     <tr><td class="paramdir">[in]</td><td class="paramname">IRQn</td><td>The interrupt to be enabled.</td></tr>
1021   </table>
1022   </dd>
1023 </dl>
1024 <p>Adds the pending state to the corresponding interrupt. </p>
1025
1026 </div>
1027 </div>
1028 <a id="ga27b9862b58290276851ec669cabf0f71" name="ga27b9862b58290276851ec669cabf0f71"></a>
1029 <h2 class="memtitle"><span class="permalink"><a href="#ga27b9862b58290276851ec669cabf0f71">&#9670;&#160;</a></span>GIC_SetPriority()</h2>
1030
1031 <div class="memitem">
1032 <div class="memproto">
1033       <table class="memname">
1034         <tr>
1035           <td class="memname">__STATIC_INLINE void GIC_SetPriority </td>
1036           <td>(</td>
1037           <td class="paramtype"><a class="el" href="group__irq__ctrl__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a>&#160;</td>
1038           <td class="paramname"><em>IRQn</em>, </td>
1039         </tr>
1040         <tr>
1041           <td class="paramkey"></td>
1042           <td></td>
1043           <td class="paramtype">uint32_t&#160;</td>
1044           <td class="paramname"><em>priority</em>&#160;</td>
1045         </tr>
1046         <tr>
1047           <td></td>
1048           <td>)</td>
1049           <td></td><td></td>
1050         </tr>
1051       </table>
1052 </div><div class="memdoc">
1053
1054 <p>Set the priority for the given interrupt in the GIC's IPRIORITYR register. </p>
1055 <dl class="params"><dt>Parameters</dt><dd>
1056   <table class="params">
1057     <tr><td class="paramdir">[in]</td><td class="paramname">IRQn</td><td>The interrupt to be configured. </td></tr>
1058     <tr><td class="paramdir">[in]</td><td class="paramname">priority</td><td>The priority for the interrupt, lower values denote higher priorities.</td></tr>
1059   </table>
1060   </dd>
1061 </dl>
1062 <p>Configures the priority of the given interrupt.</p>
1063 <p>The available interrupt priorities are IMPLEMENTATION DEFINED. In order to query the actual priorities one can</p>
1064 <div class="fragment"><div class="line"><a class="code hl_function" href="group__GIC__functions.html#ga27b9862b58290276851ec669cabf0f71">GIC_SetPriority</a>(IRQn_TIM1, UINT32_MAX);       <span class="comment">// try to configure lowest possible priority</span></div>
1065 <div class="line">uint32_t actual = <a class="code hl_function" href="group__GIC__functions.html#ga397048004654f792649742f95bf8ae67">GIC_GetPriority</a>(IRQn_TIM1); <span class="comment">// retrieve actual lowest priority usable</span></div>
1066 <div class="ttc" id="agroup__GIC__functions_html_ga27b9862b58290276851ec669cabf0f71"><div class="ttname"><a href="group__GIC__functions.html#ga27b9862b58290276851ec669cabf0f71">GIC_SetPriority</a></div><div class="ttdeci">__STATIC_INLINE void GIC_SetPriority(IRQn_Type IRQn, uint32_t priority)</div><div class="ttdoc">Set the priority for the given interrupt in the GIC's IPRIORITYR register.</div><div class="ttdef"><b>Definition:</b> core_ca.h:1655</div></div>
1067 <div class="ttc" id="agroup__GIC__functions_html_ga397048004654f792649742f95bf8ae67"><div class="ttname"><a href="group__GIC__functions.html#ga397048004654f792649742f95bf8ae67">GIC_GetPriority</a></div><div class="ttdeci">__STATIC_INLINE uint32_t GIC_GetPriority(IRQn_Type IRQn)</div><div class="ttdoc">Read the current interrupt priority from GIC's IPRIORITYR register.</div><div class="ttdef"><b>Definition:</b> core_ca.h:1664</div></div>
1068 </div><!-- fragment -->
1069 </div>
1070 </div>
1071 <a id="gae86bba705d0d4ef812b84d29d7b3ca2b" name="gae86bba705d0d4ef812b84d29d7b3ca2b"></a>
1072 <h2 class="memtitle"><span class="permalink"><a href="#gae86bba705d0d4ef812b84d29d7b3ca2b">&#9670;&#160;</a></span>GIC_SetTarget()</h2>
1073
1074 <div class="memitem">
1075 <div class="memproto">
1076       <table class="memname">
1077         <tr>
1078           <td class="memname">__STATIC_INLINE void GIC_SetTarget </td>
1079           <td>(</td>
1080           <td class="paramtype"><a class="el" href="group__irq__ctrl__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a>&#160;</td>
1081           <td class="paramname"><em>IRQn</em>, </td>
1082         </tr>
1083         <tr>
1084           <td class="paramkey"></td>
1085           <td></td>
1086           <td class="paramtype">uint32_t&#160;</td>
1087           <td class="paramname"><em>cpu_target</em>&#160;</td>
1088         </tr>
1089         <tr>
1090           <td></td>
1091           <td>)</td>
1092           <td></td><td></td>
1093         </tr>
1094       </table>
1095 </div><div class="memdoc">
1096
1097 <p>Sets the GIC's ITARGETSR register for the given interrupt. </p>
1098 <dl class="params"><dt>Parameters</dt><dd>
1099   <table class="params">
1100     <tr><td class="paramdir">[in]</td><td class="paramname">IRQn</td><td>Interrupt to be configured. </td></tr>
1101     <tr><td class="paramdir">[in]</td><td class="paramname">cpu_target</td><td>CPU interfaces to assign this interrupt to.</td></tr>
1102   </table>
1103   </dd>
1104 </dl>
1105 <p>The <a class="el" href="structGICDistributor__Type.html#a6f1b07d48d3a9199f2effec8492f721c">ITARGETSR</a> registers provide an 8-bit CPU targets field for each interrupt supported by the GIC. This field stores the list of target processors for the interrupt. That is, it holds the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and has sufficient priority. </p>
1106
1107 </div>
1108 </div>
1109 </div><!-- contents -->
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