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  46    <div id="projectname">CMSIS-Core (Cortex-M)
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  55    <div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div>
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 127   <div class="headertitle"><div class="title">Overview </div></div>
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 129 <div class="contents">
 130 <div class="textblock"><p>CMSIS-Core (Cortex-M) implements the basic run-time system for a Cortex-M device and gives the user access to the processor core and the device peripherals. In detail it defines:</p><ul>
 131 <li><b>Hardware Abstraction Layer (HAL)</b> for Cortex-M processor registers with standardized definitions for the SysTick, NVIC, System Control Block registers, MPU registers, FPU registers, and core access functions.</li>
 132 <li><b>System exception names</b> to interface to system exceptions without having compatibility issues.</li>
 133 <li><b>Methods to organize header files</b> that makes it easy to learn new Cortex-M microcontroller products and improve software portability. This includes naming conventions for device-specific interrupts.</li>
 134 <li><b>Methods for system initialization</b> to be used by each MCU vendor. For example, the standardized <a class="el" href="group__system__init__gr.html#ga93f514700ccf00d08dbdcff7f1224eb2" title="Function to Initialize the system.">SystemInit()</a> function is essential for configuring the clock system of the device.</li>
 135 <li><b>Intrinsic functions</b> used to generate CPU instructions that are not supported by standard C functions.</li>
 136 <li>A variable to determine the <b>system clock frequency</b> which simplifies the setup the SysTick timer.</li>
 137 </ul>
 138 <p>The following sections provide details about the CMSIS-Core (Cortex-M):</p><ul>
 139 <li><a class="el" href="using_pg.html">Using CMSIS in Embedded Applications</a> describes the project setup and shows a simple program example. </li>
 140 <li><a class="el" href="using_TrustZone_pg.html">Using TrustZone&reg; for Armv8-M</a> describes how to use the security extensions available in the Armv8-M architecture. </li>
 141 <li><a class="el" href="templates_pg.html">CMSIS-Core Device Templates</a> describes the files of the CMSIS-Core (Cortex-M) in detail and explains how to adapt template files provided by Arm to silicon vendor devices.</li>
 142 <li><a class="el" href="coreMISRA_Exceptions_pg.html">MISRA-C Deviations</a> describes the violations to the MISRA standard.</li>
 143 <li><a href="modules.html"><b>Reference</b> </a> describe the features and functions of the <a class="el" href="device_h_pg.html">Device Header File &lt;device.h&gt;</a> in detail.</li>
 144 <li><a href="annotated.html"><b>Data</b> <b>Structures</b> </a> describe the data structures of the <a class="el" href="device_h_pg.html">Device Header File &lt;device.h&gt;</a> in detail.</li>
 145 </ul>
 146 <h2><a class="anchor" id="autotoc_md0"></a>
 147 CMSIS-Core (Cortex-M) in ARM::CMSIS Pack</h2>
 148 <p>Files relevant to CMSIS-Core (Cortex-M) are present in the following <b>ARM::CMSIS</b> directories: </p><table class="markdownTable">
 149 <tr class="markdownTableHead">
 150 <th class="markdownTableHeadNone">File/Folder   </th><th class="markdownTableHeadNone">Content    </th></tr>
 151 <tr class="markdownTableRowOdd">
 152 <td class="markdownTableBodyNone"><b>CMSIS\Documentation\Core</b>   </td><td class="markdownTableBodyNone">This documentation    </td></tr>
 153 <tr class="markdownTableRowEven">
 154 <td class="markdownTableBodyNone"><b>CMSIS\Core\Include</b>   </td><td class="markdownTableBodyNone">CMSIS-Core (Cortex-M) header files (for example core_cm3.h, core_cmInstr.h, etc.)    </td></tr>
 155 <tr class="markdownTableRowOdd">
 156 <td class="markdownTableBodyNone"><b>Device</b>   </td><td class="markdownTableBodyNone"><a class="el" href="using_ARM_pg.html">Arm reference implementations</a> of Cortex-M devices    </td></tr>
 157 <tr class="markdownTableRowEven">
 158 <td class="markdownTableBodyNone"><b>Device\_Template_Vendor</b>   </td><td class="markdownTableBodyNone"><a class="el" href="templates_pg.html">CMSIS-Core Device Templates</a> for extension by silicon vendors   </td></tr>
 159 </table>
 160 <h1><a class="anchor" id="ref_v6-v8M"></a>
 161 Processor Support</h1>
 162 <p>CMSIS supports the complete range of <a href="https://developer.arm.com/products/processors/cortex-m" target="_blank"><b>Cortex-M processors</b></a> and the <a href="https://developer.arm.com/architectures/cpu-architecture/m-profile" target="_blank"><b>Armv8-M/v8.1-M architecture</b></a> including security extensions.</p>
 163 <h2><a class="anchor" id="ref_man_sec"></a>
 164 Cortex-M Generic User Guides</h2>
 165 <p>The Cortex-M Device Generic User Guides contain the programmers model and detailed information about the core peripherals and are available for:</p>
 166 <ul>
 167 <li><a href="https://developer.arm.com/documentation/dui0497/latest/" target="_blank"><b>Cortex-M0 Devices Generic User Guide</b></a> (Armv6-M architecture)</li>
 168 <li><a href="https://developer.arm.com/documentation/dui0662/latest/" target="_blank"><b>Cortex-M0+ Devices Generic User Guide</b></a> (Armv6-M architecture)</li>
 169 <li><a href="https://developer.arm.com/documentation/dui0552/latest/" target="_blank"><b>Cortex-M3 Devices Generic User Guide</b></a> (Armv7-M architecture)</li>
 170 <li><a href="https://developer.arm.com/documentation/dui0553/latest/" target="_blank"><b>Cortex-M4 Devices Generic User Guide</b></a> (Armv7-M architecture)</li>
 171 <li><a href="https://developer.arm.com/documentation/dui0646/latest/" target="_blank"><b>Cortex-M7 Devices Generic User Guide</b></a> (Armv7-M architecture)</li>
 172 <li><a href="https://developer.arm.com/documentation/dui1095/latest/" target="_blank"><b>Cortex-M23 Devices Generic User Guide</b></a> (Armv8-M architecture)</li>
 173 <li><a href="https://developer.arm.com/documentation/100235/latest/" target="_blank"><b>Cortex-M33 Devices Generic User Guide</b></a> (Armv8-M architecture)</li>
 174 <li><a href="https://developer.arm.com/documentation/101273/latest/" target="_blank"><b>Cortex-M55 Devices Generic User Guide</b></a> (Armv8.1-M architecture)</li>
 175 <li><a href="https://developer.arm.com/documentation/101928/latest" target="_blank"><b>Cortex-M85 Devices Generic User Guide</b></a> (Armv8.1-M architecture)</li>
 176 </ul>
 177 <p>CMSIS also supports the following Cortex-M processor variants:</p><ul>
 178 <li><a href="https://developer.arm.com/products/processors/cortex-m/cortex-m1" target="_blank"><b>Cortex-M1</b></a> is a processor designed specifically for implementation in FPGAs (Armv6-M architecture).</li>
 179 <li><a href="https://developer.arm.com/products/processors/cortex-m/sc000-processor" target="_blank"><b>SecurCore SC000</b></a> is designed specifically for smartcard and security applications (Armv6-M architecture).</li>
 180 <li><a href="https://developer.arm.com/products/processors/cortex-m/sc300-processor" target="_blank"><b>SecurCore SC300</b></a> is designed specifically for smartcard and security applications (Armv7-M architecture).</li>
 181 <li><a href="https://developer.arm.com/products/processors/cortex-m/cortex-m35p" target="_blank"><b>Cortex-M35P</b></a> is a tamper resistant Cortex-M processor with optional software isolation using TrustZone for Armv8-M.</li>
 182 <li><a href="https://www.armchina.com/mountain?infoId=160" target="_blank"><b>STAR-MC1</b></a> is a variant of Armv8-M with TrustZone designed by Arm China.</li>
 183 </ul>
 184 <h2><a class="anchor" id="ARMv8M"></a>
 185 Armv8-M and Armv8.1-M Architecture</h2>
 186 <p>Armv8-M introduces two profiles <b>baseline</b> (for power and area constrained applications) and <b>mainline</b> (full-featured with optional SIMD, floating-point, and co-processor extensions). Both Armv8-M profiles and Armv8.1-M are supported by CMSIS.</p>
 187 <p>The Armv8-M architecture is described in the <a href="https://developer.arm.com/documentation/ddi0553/latest/" target="_blank"><b>Armv8-M Architecture Reference Manual</b></a>.</p>
 188 <p>The Armv8.1-M architecture further extends Armv8-M with Helium (the so called M-Profile Vector Extension (MVE)), as well as further instruction set and debug extensions. More information about Armv8.1-M architecture is available under <a href="https://developer.arm.com/technologies/helium" target="_blank"><b>Arm Helium technology</b></a>.</p>
 189 <h1><a class="anchor" id="tested_tools_sec"></a>
 190 Tested and Verified Toolchains</h1>
 191 <p>The <a class="el" href="templates_pg.html">CMSIS-Core Device Templates</a> supplied by Arm have been tested and verified with the following toolchains:</p><ul>
 192 <li>Arm: Arm Compiler 5.06 update 7 (not for Cortex-M23/33/35P/55/85, Armv8-M, Armv8.1-M)</li>
 193 <li>Arm: Arm Compiler 6.16</li>
 194 <li>Arm: Arm Compiler 6.6.4 (not for Cortex-M0/23/33/35P/55/85, Armv8-M, Armv8.1-M)</li>
 195 <li>GNU: GNU Arm Embedded Toolchain 10-2020-q4-major (10.2.1 20201103)</li>
 196 <li>IAR: IAR ANSI C/C++ Compiler for Arm 8.20.1.14183 </li>
 197 </ul>
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