2 * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
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4 * SPDX-License-Identifier: Apache-2.0
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6 * Licensed under the Apache License, Version 2.0 (the License); you may
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7 * not use this file except in compliance with the License.
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8 * You may obtain a copy of the License at
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10 * http://www.apache.org/licenses/LICENSE-2.0
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12 * Unless required by applicable law or agreed to in writing, software
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13 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
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14 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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15 * See the License for the specific language governing permissions and
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16 * limitations under the License.
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18 * $Date: 30. May 2014
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21 * Project: NAND Flash Driver definitions
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26 * Updated ARM_NAND_ECC_INFO structure and ARM_NAND_ECC_xxx definitions
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28 * New simplified driver:
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29 * complexity moved to upper layer (command agnostic)
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30 * Added support for:
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31 * NV-DDR & NV-DDR2 Interface (ONFI specification)
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32 * VCC, VCCQ and VPP Power Supply Control
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33 * WP (Write Protect) Control
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35 * Changed prefix ARM_DRV -> ARM_DRIVER
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37 * Namespace prefix ARM_ added
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42 #ifndef __DRIVER_NAND_H
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43 #define __DRIVER_NAND_H
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45 #include "Driver_Common.h"
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47 #define ARM_NAND_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,01) /* API version */
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50 /****** NAND Device Power *****/
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51 #define ARM_NAND_POWER_VCC_Pos 0
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52 #define ARM_NAND_POWER_VCC_Msk (0x07UL << ARM_NAND_POWER_VCC_Pos)
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53 #define ARM_NAND_POWER_VCC_OFF (0x01UL << ARM_NAND_POWER_VCC_Pos) ///< VCC Power off
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54 #define ARM_NAND_POWER_VCC_3V3 (0x02UL << ARM_NAND_POWER_VCC_Pos) ///< VCC = 3.3V
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55 #define ARM_NAND_POWER_VCC_1V8 (0x03UL << ARM_NAND_POWER_VCC_Pos) ///< VCC = 1.8V
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56 #define ARM_NAND_POWER_VCCQ_Pos 3
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57 #define ARM_NAND_POWER_VCCQ_Msk (0x07UL << ARM_NAND_POWER_VCCQ_Pos)
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58 #define ARM_NAND_POWER_VCCQ_OFF (0x01UL << ARM_NAND_POWER_VCCQ_Pos) ///< VCCQ I/O Power off
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59 #define ARM_NAND_POWER_VCCQ_3V3 (0x02UL << ARM_NAND_POWER_VCCQ_Pos) ///< VCCQ = 3.3V
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60 #define ARM_NAND_POWER_VCCQ_1V8 (0x03UL << ARM_NAND_POWER_VCCQ_Pos) ///< VCCQ = 1.8V
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61 #define ARM_NAND_POWER_VPP_OFF (1UL << 6) ///< VPP off
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62 #define ARM_NAND_POWER_VPP_ON (1Ul << 7) ///< VPP on
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65 /****** NAND Control Codes *****/
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66 #define ARM_NAND_BUS_MODE (0x01) ///< Set Bus Mode as specified with arg
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67 #define ARM_NAND_BUS_DATA_WIDTH (0x02) ///< Set Bus Data Width as specified with arg
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68 #define ARM_NAND_DRIVER_STRENGTH (0x03) ///< Set Driver Strength as specified with arg
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69 #define ARM_NAND_DEVICE_READY_EVENT (0x04) ///< Generate \ref ARM_NAND_EVENT_DEVICE_READY; arg: 0=disabled (default), 1=enabled
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70 #define ARM_NAND_DRIVER_READY_EVENT (0x05) ///< Generate \ref ARM_NAND_EVENT_DRIVER_READY; arg: 0=disabled (default), 1=enabled
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72 /*----- NAND Bus Mode (ONFI - Open NAND Flash Interface) -----*/
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73 #define ARM_NAND_BUS_INTERFACE_Pos 4
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74 #define ARM_NAND_BUS_INTERFACE_Msk (0x03UL << ARM_NAND_BUS_INTERFACE_Pos)
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75 #define ARM_NAND_BUS_SDR (0x00UL << ARM_NAND_BUS_INTERFACE_Pos) ///< Data Interface: SDR (Single Data Rate) - Traditional interface (default)
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76 #define ARM_NAND_BUS_DDR (0x01UL << ARM_NAND_BUS_INTERFACE_Pos) ///< Data Interface: NV-DDR (Double Data Rate)
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77 #define ARM_NAND_BUS_DDR2 (0x02UL << ARM_NAND_BUS_INTERFACE_Pos) ///< Data Interface: NV-DDR2 (Double Data Rate)
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78 #define ARM_NAND_BUS_TIMING_MODE_Pos 0
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79 #define ARM_NAND_BUS_TIMING_MODE_Msk (0x0FUL << ARM_NAND_BUS_TIMING_MODE_Pos)
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80 #define ARM_NAND_BUS_TIMING_MODE_0 (0x00UL << ARM_NAND_BUS_TIMING_MODE_Pos) ///< Timing Mode 0 (default)
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81 #define ARM_NAND_BUS_TIMING_MODE_1 (0x01UL << ARM_NAND_BUS_TIMING_MODE_Pos) ///< Timing Mode 1
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82 #define ARM_NAND_BUS_TIMING_MODE_2 (0x02UL << ARM_NAND_BUS_TIMING_MODE_Pos) ///< Timing Mode 2
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83 #define ARM_NAND_BUS_TIMING_MODE_3 (0x03UL << ARM_NAND_BUS_TIMING_MODE_Pos) ///< Timing Mode 3
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84 #define ARM_NAND_BUS_TIMING_MODE_4 (0x04UL << ARM_NAND_BUS_TIMING_MODE_Pos) ///< Timing Mode 4 (SDR EDO capable)
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85 #define ARM_NAND_BUS_TIMING_MODE_5 (0x05UL << ARM_NAND_BUS_TIMING_MODE_Pos) ///< Timing Mode 5 (SDR EDO capable)
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86 #define ARM_NAND_BUS_TIMING_MODE_6 (0x06UL << ARM_NAND_BUS_TIMING_MODE_Pos) ///< Timing Mode 6 (NV-DDR2 only)
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87 #define ARM_NAND_BUS_TIMING_MODE_7 (0x07UL << ARM_NAND_BUS_TIMING_MODE_Pos) ///< Timing Mode 7 (NV-DDR2 only)
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88 #define ARM_NAND_BUS_DDR2_DO_WCYC_Pos 8
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89 #define ARM_NAND_BUS_DDR2_DO_WCYC_Msk (0x0FUL << ARM_NAND_BUS_DDR2_DO_WCYC_Pos)
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90 #define ARM_NAND_BUS_DDR2_DO_WCYC_0 (0x00UL << ARM_NAND_BUS_DDR2_DO_WCYC_Pos) ///< DDR2 Data Output Warm-up cycles: 0 (default)
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91 #define ARM_NAND_BUS_DDR2_DO_WCYC_1 (0x01UL << ARM_NAND_BUS_DDR2_DO_WCYC_Pos) ///< DDR2 Data Output Warm-up cycles: 1
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92 #define ARM_NAND_BUS_DDR2_DO_WCYC_2 (0x02UL << ARM_NAND_BUS_DDR2_DO_WCYC_Pos) ///< DDR2 Data Output Warm-up cycles: 2
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93 #define ARM_NAND_BUS_DDR2_DO_WCYC_4 (0x03UL << ARM_NAND_BUS_DDR2_DO_WCYC_Pos) ///< DDR2 Data Output Warm-up cycles: 4
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94 #define ARM_NAND_BUS_DDR2_DI_WCYC_Pos 12
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95 #define ARM_NAND_BUS_DDR2_DI_WCYC_Msk (0x0FUL << ARM_NAND_BUS_DDR2_DI_WCYC_Pos)
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96 #define ARM_NAND_BUS_DDR2_DI_WCYC_0 (0x00UL << ARM_NAND_BUS_DDR2_DI_WCYC_Pos) ///< DDR2 Data Input Warm-up cycles: 0 (default)
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97 #define ARM_NAND_BUS_DDR2_DI_WCYC_1 (0x01UL << ARM_NAND_BUS_DDR2_DI_WCYC_Pos) ///< DDR2 Data Input Warm-up cycles: 1
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98 #define ARM_NAND_BUS_DDR2_DI_WCYC_2 (0x02UL << ARM_NAND_BUS_DDR2_DI_WCYC_Pos) ///< DDR2 Data Input Warm-up cycles: 2
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99 #define ARM_NAND_BUS_DDR2_DI_WCYC_4 (0x03UL << ARM_NAND_BUS_DDR2_DI_WCYC_Pos) ///< DDR2 Data Input Warm-up cycles: 4
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100 #define ARM_NAND_BUS_DDR2_VEN (1UL << 16) ///< DDR2 Enable external VREFQ as reference
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101 #define ARM_NAND_BUS_DDR2_CMPD (1UL << 17) ///< DDR2 Enable complementary DQS (DQS_c) signal
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102 #define ARM_NAND_BUS_DDR2_CMPR (1UL << 18) ///< DDR2 Enable complementary RE_n (RE_c) signal
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104 /*----- NAND Data Bus Width -----*/
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105 #define ARM_NAND_BUS_DATA_WIDTH_8 (0x00) ///< Bus Data Width: 8 bit (default)
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106 #define ARM_NAND_BUS_DATA_WIDTH_16 (0x01) ///< Bus Data Width: 16 bit
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108 /*----- NAND Driver Strength (ONFI - Open NAND Flash Interface) -----*/
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109 #define ARM_NAND_DRIVER_STRENGTH_18 (0x00) ///< Driver Strength 2.0x = 18 Ohms
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110 #define ARM_NAND_DRIVER_STRENGTH_25 (0x01) ///< Driver Strength 1.4x = 25 Ohms
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111 #define ARM_NAND_DRIVER_STRENGTH_35 (0x02) ///< Driver Strength 1.0x = 35 Ohms (default)
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112 #define ARM_NAND_DRIVER_STRENGTH_50 (0x03) ///< Driver Strength 0.7x = 50 Ohms
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115 /****** NAND ECC for Read/Write Data Mode and Sequence Execution Code *****/
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116 #define ARM_NAND_ECC_INDEX_Pos 0
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117 #define ARM_NAND_ECC_INDEX_Msk (0xFFUL << ARM_NAND_ECC_INDEX_Pos)
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118 #define ARM_NAND_ECC(n) ((n) & ARM_NAND_ECC_INDEX_Msk) ///< Select ECC
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119 #define ARM_NAND_ECC0 (1UL << 8) ///< Use ECC0 of selected ECC
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120 #define ARM_NAND_ECC1 (1UL << 9) ///< Use ECC1 of selected ECC
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122 /****** NAND Flag for Read/Write Data Mode and Sequence Execution Code *****/
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123 #define ARM_NAND_DRIVER_DONE_EVENT (1UL << 16) ///< Generate \ref ARM_NAND_EVENT_DRIVER_DONE
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125 /****** NAND Sequence Execution Code *****/
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126 #define ARM_NAND_CODE_SEND_CMD1 (1UL << 17) ///< Send Command 1
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127 #define ARM_NAND_CODE_SEND_ADDR_COL1 (1UL << 18) ///< Send Column Address 1
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128 #define ARM_NAND_CODE_SEND_ADDR_COL2 (1UL << 19) ///< Send Column Address 2
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129 #define ARM_NAND_CODE_SEND_ADDR_ROW1 (1UL << 20) ///< Send Row Address 1
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130 #define ARM_NAND_CODE_SEND_ADDR_ROW2 (1UL << 21) ///< Send Row Address 2
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131 #define ARM_NAND_CODE_SEND_ADDR_ROW3 (1UL << 22) ///< Send Row Address 3
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132 #define ARM_NAND_CODE_INC_ADDR_ROW (1UL << 23) ///< Auto-increment Row Address
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133 #define ARM_NAND_CODE_WRITE_DATA (1UL << 24) ///< Write Data
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134 #define ARM_NAND_CODE_SEND_CMD2 (1UL << 25) ///< Send Command 2
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135 #define ARM_NAND_CODE_WAIT_BUSY (1UL << 26) ///< Wait while R/Bn busy
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136 #define ARM_NAND_CODE_READ_DATA (1UL << 27) ///< Read Data
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137 #define ARM_NAND_CODE_SEND_CMD3 (1UL << 28) ///< Send Command 3
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138 #define ARM_NAND_CODE_READ_STATUS (1UL << 29) ///< Read Status byte and check FAIL bit (bit 0)
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140 /*----- NAND Sequence Execution Code: Command -----*/
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141 #define ARM_NAND_CODE_CMD1_Pos 0
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142 #define ARM_NAND_CODE_CMD1_Msk (0xFFUL << ARM_NAND_CODE_CMD1_Pos)
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143 #define ARM_NAND_CODE_CMD2_Pos 8
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144 #define ARM_NAND_CODE_CMD2_Msk (0xFFUL << ARM_NAND_CODE_CMD2_Pos)
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145 #define ARM_NAND_CODE_CMD3_Pos 16
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146 #define ARM_NAND_CODE_CMD3_Msk (0xFFUL << ARM_NAND_CODE_CMD3_Pos)
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148 /*----- NAND Sequence Execution Code: Column Address -----*/
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149 #define ARM_NAND_CODE_ADDR_COL1_Pos 0
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150 #define ARM_NAND_CODE_ADDR_COL1_Msk (0xFFUL << ARM_NAND_CODE_ADDR_COL1_Pos)
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151 #define ARM_NAND_CODE_ADDR_COL2_Pos 8
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152 #define ARM_NAND_CODE_ADDR_COL2_Msk (0xFFUL << ARM_NAND_CODE_ADDR_COL2_Pos)
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154 /*----- NAND Sequence Execution Code: Row Address -----*/
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155 #define ARM_NAND_CODE_ADDR_ROW1_Pos 0
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156 #define ARM_NAND_CODE_ADDR_ROW1_Msk (0xFFUL << ARM_NAND_CODE_ADDR_ROW1_Pos)
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157 #define ARM_NAND_CODE_ADDR_ROW2_Pos 8
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158 #define ARM_NAND_CODE_ADDR_ROW2_Msk (0xFFUL << ARM_NAND_CODE_ADDR_ROW2_Pos)
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159 #define ARM_NAND_CODE_ADDR_ROW3_Pos 16
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160 #define ARM_NAND_CODE_ADDR_ROW3_Msk (0xFFUL << ARM_NAND_CODE_ADDR_ROW3_Pos)
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163 /****** NAND specific error codes *****/
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164 #define ARM_NAND_ERROR_ECC (ARM_DRIVER_ERROR_SPECIFIC - 1) ///< ECC generation/correction failed
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168 \brief NAND ECC (Error Correction Code) Information
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170 typedef struct _ARM_NAND_ECC_INFO {
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171 uint32_t type : 2; ///< Type: 1=ECC0 over Data, 2=ECC0 over Data+Spare, 3=ECC0 over Data and ECC1 over Spare
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172 uint32_t page_layout : 1; ///< Page layout: 0=|Data0|Spare0|...|DataN-1|SpareN-1|, 1=|Data0|...|DataN-1|Spare0|...|SpareN-1|
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173 uint32_t page_count : 3; ///< Number of virtual pages: N = 2 ^ page_count
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174 uint32_t page_size : 4; ///< Virtual Page size (Data+Spare): 0=512+16, 1=1k+32, 2=2k+64, 3=4k+128, 4=8k+256, 8=512+28, 9=1k+56, 10=2k+112, 11=4k+224, 12=8k+448
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175 uint32_t reserved : 14; ///< Reserved (must be zero)
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176 uint32_t correctable_bits : 8; ///< Number of correctable bits (based on 512 byte codeword size)
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177 uint16_t codeword_size [2]; ///< Number of bytes over which ECC is calculated
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178 uint16_t ecc_size [2]; ///< ECC size in bytes (rounded up)
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179 uint16_t ecc_offset [2]; ///< ECC offset in bytes (where ECC starts in Spare area)
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180 } ARM_NAND_ECC_INFO;
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186 typedef struct _ARM_NAND_STATUS {
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187 uint32_t busy : 1; ///< Driver busy flag
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188 uint32_t ecc_error : 1; ///< ECC error detected (cleared on next Read/WriteData or ExecuteSequence)
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192 /****** NAND Event *****/
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193 #define ARM_NAND_EVENT_DEVICE_READY (1UL << 0) ///< Device Ready: R/Bn rising edge
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194 #define ARM_NAND_EVENT_DRIVER_READY (1UL << 1) ///< Driver Ready
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195 #define ARM_NAND_EVENT_DRIVER_DONE (1UL << 2) ///< Driver operation done
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196 #define ARM_NAND_EVENT_ECC_ERROR (1UL << 3) ///< ECC could not correct data
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199 // Function documentation
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201 \fn ARM_DRIVER_VERSION ARM_NAND_GetVersion (void)
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202 \brief Get driver version.
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203 \return \ref ARM_DRIVER_VERSION
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206 \fn ARM_NAND_CAPABILITIES ARM_NAND_GetCapabilities (void)
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207 \brief Get driver capabilities.
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208 \return \ref ARM_NAND_CAPABILITIES
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211 \fn int32_t ARM_NAND_Initialize (ARM_NAND_SignalEvent_t cb_event)
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212 \brief Initialize the NAND Interface.
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213 \param[in] cb_event Pointer to \ref ARM_NAND_SignalEvent
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214 \return \ref execution_status
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217 \fn int32_t ARM_NAND_Uninitialize (void)
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218 \brief De-initialize the NAND Interface.
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219 \return \ref execution_status
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222 \fn int32_t ARM_NAND_PowerControl (ARM_POWER_STATE state)
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223 \brief Control the NAND interface power.
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224 \param[in] state Power state
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225 \return \ref execution_status
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228 \fn int32_t ARM_NAND_DevicePower (uint32_t voltage)
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229 \brief Set device power supply voltage.
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230 \param[in] voltage NAND Device supply voltage
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231 \return \ref execution_status
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234 \fn int32_t ARM_NAND_WriteProtect (uint32_t dev_num, bool enable)
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235 \brief Control WPn (Write Protect).
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236 \param[in] dev_num Device number
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238 - \b false Write Protect off
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239 - \b true Write Protect on
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240 \return \ref execution_status
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243 \fn int32_t ARM_NAND_ChipEnable (uint32_t dev_num, bool enable)
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244 \brief Control CEn (Chip Enable).
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245 \param[in] dev_num Device number
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247 - \b false Chip Enable off
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248 - \b true Chip Enable on
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249 \return \ref execution_status
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252 \fn int32_t ARM_NAND_GetDeviceBusy (uint32_t dev_num)
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253 \brief Get Device Busy pin state.
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254 \param[in] dev_num Device number
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255 \return 1=busy, 0=not busy, or error
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258 \fn int32_t ARM_NAND_SendCommand (uint32_t dev_num, uint8_t cmd)
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259 \brief Send command to NAND device.
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260 \param[in] dev_num Device number
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261 \param[in] cmd Command
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262 \return \ref execution_status
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265 \fn int32_t ARM_NAND_SendAddress (uint32_t dev_num, uint8_t addr)
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266 \brief Send address to NAND device.
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267 \param[in] dev_num Device number
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268 \param[in] addr Address
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269 \return \ref execution_status
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272 \fn int32_t ARM_NAND_ReadData (uint32_t dev_num, void *data, uint32_t cnt, uint32_t mode)
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273 \brief Read data from NAND device.
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274 \param[in] dev_num Device number
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275 \param[out] data Pointer to buffer for data to read from NAND device
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276 \param[in] cnt Number of data items to read
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277 \param[in] mode Operation mode
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278 \return number of data items read or \ref execution_status
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281 \fn int32_t ARM_NAND_WriteData (uint32_t dev_num, const void *data, uint32_t cnt, uint32_t mode)
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282 \brief Write data to NAND device.
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283 \param[in] dev_num Device number
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284 \param[out] data Pointer to buffer with data to write to NAND device
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285 \param[in] cnt Number of data items to write
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286 \param[in] mode Operation mode
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287 \return number of data items written or \ref execution_status
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290 \fn int32_t ARM_NAND_ExecuteSequence (uint32_t dev_num, uint32_t code, uint32_t cmd,
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291 uint32_t addr_col, uint32_t addr_row,
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292 void *data, uint32_t data_cnt,
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293 uint8_t *status, uint32_t *count)
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294 \brief Execute sequence of operations.
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295 \param[in] dev_num Device number
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296 \param[in] code Sequence code
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297 \param[in] cmd Command(s)
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298 \param[in] addr_col Column address
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299 \param[in] addr_row Row address
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300 \param[in,out] data Pointer to data to be written or read
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301 \param[in] data_cnt Number of data items in one iteration
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302 \param[out] status Pointer to status read
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303 \param[in,out] count Number of iterations
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304 \return \ref execution_status
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307 \fn int32_t ARM_NAND_AbortSequence (uint32_t dev_num)
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308 \brief Abort sequence execution.
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309 \param[in] dev_num Device number
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310 \return \ref execution_status
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313 \fn int32_t ARM_NAND_Control (uint32_t dev_num, uint32_t control, uint32_t arg)
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314 \brief Control NAND Interface.
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315 \param[in] dev_num Device number
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316 \param[in] control Operation
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317 \param[in] arg Argument of operation
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318 \return \ref execution_status
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321 \fn ARM_NAND_STATUS ARM_NAND_GetStatus (uint32_t dev_num)
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322 \brief Get NAND status.
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323 \param[in] dev_num Device number
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324 \return NAND status \ref ARM_NAND_STATUS
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327 \fn int32_t ARM_NAND_InquireECC (int32_t index, ARM_NAND_ECC_INFO *info)
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328 \brief Inquire about available ECC.
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329 \param[in] index Device number
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330 \param[out] info Pointer to ECC information \ref ARM_NAND_ECC_INFO retrieved
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331 \return \ref execution_status
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335 \fn void ARM_NAND_SignalEvent (uint32_t dev_num, uint32_t event)
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336 \brief Signal NAND event.
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337 \param[in] dev_num Device number
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338 \param[in] event Event notification mask
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342 typedef void (*ARM_NAND_SignalEvent_t) (uint32_t dev_num, uint32_t event); ///< Pointer to \ref ARM_NAND_SignalEvent : Signal NAND Event.
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346 \brief NAND Driver Capabilities.
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348 typedef struct _ARM_NAND_CAPABILITIES {
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349 uint32_t event_device_ready : 1; ///< Signal Device Ready event (R/Bn rising edge)
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350 uint32_t reentrant_operation : 1; ///< Supports re-entrant operation (SendCommand/Address, Read/WriteData)
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351 uint32_t sequence_operation : 1; ///< Supports Sequence operation (ExecuteSequence, AbortSequence)
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352 uint32_t vcc : 1; ///< Supports VCC Power Supply Control
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353 uint32_t vcc_1v8 : 1; ///< Supports 1.8 VCC Power Supply
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354 uint32_t vccq : 1; ///< Supports VCCQ I/O Power Supply Control
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355 uint32_t vccq_1v8 : 1; ///< Supports 1.8 VCCQ I/O Power Supply
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356 uint32_t vpp : 1; ///< Supports VPP High Voltage Power Supply Control
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357 uint32_t wp : 1; ///< Supports WPn (Write Protect) Control
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358 uint32_t ce_lines : 4; ///< Number of CEn (Chip Enable) lines: ce_lines + 1
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359 uint32_t ce_manual : 1; ///< Supports manual CEn (Chip Enable) Control
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360 uint32_t rb_monitor : 1; ///< Supports R/Bn (Ready/Busy) Monitoring
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361 uint32_t data_width_16 : 1; ///< Supports 16-bit data
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362 uint32_t ddr : 1; ///< Supports NV-DDR Data Interface (ONFI)
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363 uint32_t ddr2 : 1; ///< Supports NV-DDR2 Data Interface (ONFI)
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364 uint32_t sdr_timing_mode : 3; ///< Fastest (highest) SDR Timing Mode supported (ONFI)
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365 uint32_t ddr_timing_mode : 3; ///< Fastest (highest) NV_DDR Timing Mode supported (ONFI)
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366 uint32_t ddr2_timing_mode : 3; ///< Fastest (highest) NV_DDR2 Timing Mode supported (ONFI)
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367 uint32_t driver_strength_18 : 1; ///< Supports Driver Strength 2.0x = 18 Ohms
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368 uint32_t driver_strength_25 : 1; ///< Supports Driver Strength 1.4x = 25 Ohms
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369 uint32_t driver_strength_50 : 1; ///< Supports Driver Strength 0.7x = 50 Ohms
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370 } ARM_NAND_CAPABILITIES;
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374 \brief Access structure of the NAND Driver.
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376 typedef struct _ARM_DRIVER_NAND {
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377 ARM_DRIVER_VERSION (*GetVersion) (void); ///< Pointer to \ref ARM_NAND_GetVersion : Get driver version.
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378 ARM_NAND_CAPABILITIES (*GetCapabilities)(void); ///< Pointer to \ref ARM_NAND_GetCapabilities : Get driver capabilities.
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379 int32_t (*Initialize) (ARM_NAND_SignalEvent_t cb_event); ///< Pointer to \ref ARM_NAND_Initialize : Initialize NAND Interface.
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380 int32_t (*Uninitialize) (void); ///< Pointer to \ref ARM_NAND_Uninitialize : De-initialize NAND Interface.
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381 int32_t (*PowerControl) (ARM_POWER_STATE state); ///< Pointer to \ref ARM_NAND_PowerControl : Control NAND Interface Power.
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382 int32_t (*DevicePower) (uint32_t voltage); ///< Pointer to \ref ARM_NAND_DevicePower : Set device power supply voltage.
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383 int32_t (*WriteProtect) (uint32_t dev_num, bool enable); ///< Pointer to \ref ARM_NAND_WriteProtect : Control WPn (Write Protect).
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384 int32_t (*ChipEnable) (uint32_t dev_num, bool enable); ///< Pointer to \ref ARM_NAND_ChipEnable : Control CEn (Chip Enable).
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385 int32_t (*GetDeviceBusy) (uint32_t dev_num); ///< Pointer to \ref ARM_NAND_GetDeviceBusy : Get Device Busy pin state.
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386 int32_t (*SendCommand) (uint32_t dev_num, uint8_t cmd); ///< Pointer to \ref ARM_NAND_SendCommand : Send command to NAND device.
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387 int32_t (*SendAddress) (uint32_t dev_num, uint8_t addr); ///< Pointer to \ref ARM_NAND_SendAddress : Send address to NAND device.
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388 int32_t (*ReadData) (uint32_t dev_num, void *data, uint32_t cnt, uint32_t mode); ///< Pointer to \ref ARM_NAND_ReadData : Read data from NAND device.
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389 int32_t (*WriteData) (uint32_t dev_num, const void *data, uint32_t cnt, uint32_t mode); ///< Pointer to \ref ARM_NAND_WriteData : Write data to NAND device.
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390 int32_t (*ExecuteSequence)(uint32_t dev_num, uint32_t code, uint32_t cmd,
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391 uint32_t addr_col, uint32_t addr_row,
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392 void *data, uint32_t data_cnt,
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393 uint8_t *status, uint32_t *count); ///< Pointer to \ref ARM_NAND_ExecuteSequence : Execute sequence of operations.
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394 int32_t (*AbortSequence) (uint32_t dev_num); ///< Pointer to \ref ARM_NAND_AbortSequence : Abort sequence execution.
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395 int32_t (*Control) (uint32_t dev_num, uint32_t control, uint32_t arg); ///< Pointer to \ref ARM_NAND_Control : Control NAND Interface.
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396 ARM_NAND_STATUS (*GetStatus) (uint32_t dev_num); ///< Pointer to \ref ARM_NAND_GetStatus : Get NAND status.
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397 int32_t (*InquireECC) ( int32_t index, ARM_NAND_ECC_INFO *info); ///< Pointer to \ref ARM_NAND_InquireECC : Inquire about available ECC.
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398 } const ARM_DRIVER_NAND;
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400 #endif /* __DRIVER_NAND_H */
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