2 # instance.parameter=value #(type, mode) default = 'def value' : description : [min..max]
3 #----------------------------------------------------------------------------------------------
4 armcortexm4ct.vfp-present=0 # (bool , init-time) default = '1' : Set whether the model has VFP support
5 armcortexm4ct.semihosting-enable=1 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.
6 armcortexm4ct.semihosting-Thumb_SVC=0xAB # (int , init-time) default = '0xAB' : T32 SVC number for semihosting : [0x0..0xFF]
7 armcortexm4ct.semihosting-cmd_line="" # (string, init-time) default = '' : Command line available to semihosting SVC calls
8 armcortexm4ct.semihosting-heap_base=0x0 # (int , init-time) default = '0x0' : Virtual address of heap base : [0x0..0xFFFFFFFF]
9 armcortexm4ct.semihosting-heap_limit=0x0 # (int , init-time) default = '0x10700000' : Virtual address of top of heap : [0x0..0xFFFFFFFF]
10 armcortexm4ct.semihosting-stack_base=0x0 # (int , init-time) default = '0x10700000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF]
11 armcortexm4ct.semihosting-stack_limit=0x0 # (int , init-time) default = '0x10800000' : Virtual address of stack limit : [0x0..0xFFFFFFFF]
12 armcortexm4ct.semihosting-cwd="" # (string, init-time) default = '' : Base directory for semihosting file access.
13 armcortexm4ct.NUM_MPU_REGION=0x8 # (int , init-time) default = '0x8' : Number of MPU regions : [0x0..0x8]
14 armcortexm4ct.NUM_IRQ=0x10 # (int , init-time) default = '0x10' : Number of user interrupts : [0x1..0xF0]
15 armcortexm4ct.LVL_WIDTH=0x3 # (int , init-time) default = '0x3' : Number of bits of interrupt priority : [0x3..0x8]
16 armcortexm4ct.BIGENDINIT=0 # (bool , init-time) default = '0' : Initialize processor to big endian mode
17 armcortexm4ct.BB_PRESENT=1 # (bool , init-time) default = '1' : Enable bitbanding
18 armcortexm4ct.min_sync_level=0x0 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) : [0x0..0x3]
19 armcortexm4ct.cpi_mul=0x1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF]
20 armcortexm4ct.cpi_div=0x1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF]
21 armcortexm4ct.master_id=0x0 # (int , init-time) default = '0x0' : Master ID presented in bus transactions : [0x0..0xFFFFFFFF]
22 armcortexm4ct.DBGLVL=0x4 # (int , init-time) default = '0x4' : 0: No debug; 1: Minimal debug; 2: Full debug without DWT address matching; 3: Full debug support with, DWT can compare data as well as address; 4: Experiential value, support debug feature but no breakpoint and watchpoint compare : [0x0..0x4]
23 armcortexm4ct.WIC=1 # (bool , init-time) default = '1' : Include support for WIC-mode deep sleep
24 fvp_mps2.SCC_ID.Variant=0x0 # (int , init-time) default = '0x0' : SCC_ID[23:20], X in the FGPA version 'rXpY' : [0x0..0xF]
25 fvp_mps2.SCC_ID.Revision=0x1 # (int , init-time) default = '0x1' : SCC_ID[3:0], Y in the FGPA version 'rXpY' : [0x0..0xF]
26 fvp_mps2.iotss_systemcontrol.cpu0wait=0 # (bool , init-time) default = '0' : Whether to hold cpu0 in reset at boot
27 fvp_mps2.iotss_systemcontrol.cpu1wait=1 # (bool , init-time) default = '1' : Whether to hold cpu1 in reset at boot
28 fvp_mps2.platform_type=0x0 # (int , init-time) default = '0x0' : 0:Original MPS2 ; 1:IoT Kit (cut-down SSE-200) ; 2:Full SSE-200 : [0x0..0x2]
29 fvp_mps2.extra_psram=0 # (bool , init-time) default = '0' : Increases PSRAM to 32Mb
30 fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '1' : Disable Memory gating logic
31 fvp_mps2.NSC_CFG_0=0 # (bool , init-time) default = '0' : Whether 0x10000000..0x1FFFFFFF is non-secure-callable
32 fvp_mps2.NSC_CFG_1=0 # (bool , init-time) default = '0' : Whether 0x30000000..0x3FFFFFFF is non-secure-callable
33 fvp_mps2.APBPPCEXP_DIS0=0x0 # (int , init-time) default = '0x0' : Disables support for individual bits on the APBNSPPCEXP0 and APBPPPCEXP0 buses : [0x0..0xFFFF]
34 fvp_mps2.APBPPCEXP_DIS1=0x0 # (int , init-time) default = '0x0' : Disables support for individual bits on the APBNSPPCEXP1 and APBPPPCEXP1 buses : [0x0..0xFFFF]
35 fvp_mps2.APBPPCEXP_DIS2=0x0 # (int , init-time) default = '0x0' : Disables support for individual bits on the APBNSPPCEXP2 and APBPPPCEXP2 buses : [0x0..0xFFFF]
36 fvp_mps2.APBPPCEXP_DIS3=0x0 # (int , init-time) default = '0x0' : Disables support for individual bits on the APBNSPPCEXP3 and APBPPPCEXP3 buses : [0x0..0xFFFF]
37 fvp_mps2.AHBPPCEXP_DIS0=0x0 # (int , init-time) default = '0x0' : Disables support for individual bits on the AHBNSPPCEXP0 and AHBPPPCEXP0 buses : [0x0..0xFFFF]
38 fvp_mps2.AHBPPCEXP_DIS1=0x0 # (int , init-time) default = '0x0' : Disables support for individual bits on the AHBNSPPCEXP1 and AHBPPPCEXP1 buses : [0x0..0xFFFF]
39 fvp_mps2.AHBPPCEXP_DIS2=0x0 # (int , init-time) default = '0x0' : Disables support for individual bits on the AHBNSPPCEXP2 and AHBPPPCEXP2 buses : [0x0..0xFFFF]
40 fvp_mps2.AHBPPCEXP_DIS3=0x0 # (int , init-time) default = '0x0' : Disables support for individual bits on the AHBNSPPCEXP3 and AHBPPPCEXP3 buses : [0x0..0xFFFF]
41 fvp_mps2.UART2.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout)
42 fvp_mps2.UART2.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART
43 fvp_mps2.UART2.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output
44 fvp_mps2.UART2.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence
45 fvp_mps2.UART2.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available)
46 fvp_mps2.UART2.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted
47 fvp_mps2.UART1.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout)
48 fvp_mps2.UART1.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART
49 fvp_mps2.UART1.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output
50 fvp_mps2.UART1.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence
51 fvp_mps2.UART1.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available)
52 fvp_mps2.UART1.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted
53 fvp_mps2.mps2_visualisation.rate_limit-enable=1 # (bool , init-time) default = '1' : Rate limit simulation.
54 fvp_mps2.mps2_visualisation.disable-visualisation=0 # (bool , init-time) default = '0' : Enable/disable visualisation
55 fvp_mps2.mps2_visualisation.window_title="CLCD %cpu%" # (string, init-time) default = 'CLCD %cpu%' : Window title (%cpu% is replaced by cpu_name)
56 fvp_mps2.mps2_visualisation.idler.delay_ms=0x32 # (int , init-time) default = '0x32' : Determines the period, in milliseconds of real time, between gui_callback() calls.
57 fvp_mps2.telnetterminal0.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode
58 fvp_mps2.telnetterminal0.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected
59 fvp_mps2.telnetterminal0.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF]
60 fvp_mps2.telnetterminal0.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr
61 fvp_mps2.telnetterminal0.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows)
62 fvp_mps2.telnetterminal1.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode
63 fvp_mps2.telnetterminal1.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected
64 fvp_mps2.telnetterminal1.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF]
65 fvp_mps2.telnetterminal1.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr
66 fvp_mps2.telnetterminal1.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows)
67 fvp_mps2.telnetterminal2.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode
68 fvp_mps2.telnetterminal2.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected
69 fvp_mps2.telnetterminal2.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF]
70 fvp_mps2.telnetterminal2.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr
71 fvp_mps2.telnetterminal2.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows)
72 fvp_mps2.PSRAM_M7.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
73 fvp_mps2.PSRAM_M7.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
74 fvp_mps2.PSRAM_M7.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
75 fvp_mps2.UART0.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout)
76 fvp_mps2.UART0.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART
77 fvp_mps2.UART0.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output
78 fvp_mps2.UART0.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence
79 fvp_mps2.UART0.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available)
80 fvp_mps2.UART0.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted
81 fvp_mps2.cmsdk_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset.
82 fvp_mps2.PSRAM.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
83 fvp_mps2.PSRAM.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
84 fvp_mps2.PSRAM.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
85 fvp_mps2.ssram2.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
86 fvp_mps2.ssram2.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
87 fvp_mps2.ssram2.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
88 fvp_mps2.ssram1.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
89 fvp_mps2.ssram1.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
90 fvp_mps2.ssram1.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
91 fvp_mps2.stub0.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
92 fvp_mps2.stub1.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
93 fvp_mps2.stub_i2c1.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
94 fvp_mps2.stub_i2s.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
95 fvp_mps2.stub_spi0.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
96 fvp_mps2.stub_spi2.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
97 fvp_mps2.expansion_warning_memory.abort_on_reads=0 # (bool , init-time) default = '0' : Abort on reads (read 0 if false)
98 fvp_mps2.expansion_warning_memory.abort_on_writes=0 # (bool , init-time) default = '0' : Abort on writes (ignore if false)
99 fvp_mps2.expansion_warning_memory.read_data=0x0 # (int , init-time) default = '0x0' : Data to return on reads, if not aborting
100 fvp_mps2.smsc_91c111.enabled=0 # (bool , init-time) default = '0' : Host interface connection enabled
101 fvp_mps2.smsc_91c111.mac_address="00:02:f7:ef:4e:b4" # (string, init-time) default = '00:02:f7:ef:4e:b4' : Host/model MAC address
102 fvp_mps2.smsc_91c111.promiscuous=1 # (bool , init-time) default = '1' : Put host into promiscuous mode
103 fvp_mps2.hostbridge.interfaceName="ARM0" # (string, init-time) default = 'ARM0' : Host Interface
104 fvp_mps2.hostbridge.userNetworking=0 # (bool , init-time) default = '0' : Enable user-mode networking
105 fvp_mps2.hostbridge.userNetSubnet="172.20.51.0/24" # (string, init-time) default = '172.20.51.0/24' : Virtual subnet for user-mode networking
106 fvp_mps2.hostbridge.userNetPorts="" # (string, init-time) default = '' : Listening ports to expose in user-mode networking
107 fvp_mps2.sse200.secure_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset.
108 fvp_mps2.sse200.nonsecure_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset.
109 fvp_mps2.sse200.secure_control_register_block.FLASH_BLOCK_CFG=0x3 # (int , init-time) default = '0x3' : Flash Block size configuration : [0x0..0x31]
110 fvp_mps2.sse200.secure_control_register_block.SRAM_BLOCK_CFG=0x3 # (int , init-time) default = '0x3' : SRAM Block size configuration : [0x0..0x31]
111 fvp_mps2.sse200.secure_control_register_block.FLASH_WATERMARK_SUPPORTED=1 # (bool , init-time) default = '1' : Flash Watermark supported
112 fvp_mps2.sse200.secure_control_register_block.SRAM_WATERMARK_SUPPORTED=1 # (bool , init-time) default = '1' : SRAM Watermark supported
113 fvp_mps2.sse200.apb_ppc_iotss_subsystem0.NONSEC_MASK=0x0 # (int , init-time) default = '0x0' : 16-bit wide mask for security checking of ports: 0 = check, 1 = mask : [0x0..0x1]
114 fvp_mps2.sse200.apb_ppc_iotss_subsystem0.PORTx_ENABLE=0xFFFF # (int , init-time) default = '0xFFFF' : Enable (1) or disable (0) port x (where x is between 0-15): enable = 1, disable = 0 : [0x0..0xFFFF]
115 fvp_mps2.sse200.apb_ppc_iotss_subsystem1.NONSEC_MASK=0x0 # (int , init-time) default = '0x0' : 16-bit wide mask for security checking of ports: 0 = check, 1 = mask : [0x0..0x1]
116 fvp_mps2.sse200.apb_ppc_iotss_subsystem1.PORTx_ENABLE=0xFFFF # (int , init-time) default = '0xFFFF' : Enable (1) or disable (0) port x (where x is between 0-15): enable = 1, disable = 0 : [0x0..0xFFFF]
117 fvp_mps2.sse200.s32k_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset.
118 fvp_mps2.sse200.sys_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
119 fvp_mps2.sse200.sys_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
120 fvp_mps2.sse200.cpu0core_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
121 fvp_mps2.sse200.cpu0dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
122 fvp_mps2.sse200.cpu1core_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
123 fvp_mps2.sse200.cpu1core_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
124 fvp_mps2.sse200.cpu1dbg_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
125 fvp_mps2.sse200.cpu1dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
126 fvp_mps2.sse200.crypto_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
127 fvp_mps2.sse200.crypto_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
128 fvp_mps2.sse200.cordio_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
129 fvp_mps2.sse200.cordio_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
130 fvp_mps2.sse200.dbg_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
131 fvp_mps2.sse200.dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
132 fvp_mps2.sse200.ram0_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
133 fvp_mps2.sse200.ram0_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
134 fvp_mps2.sse200.ram1_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
135 fvp_mps2.sse200.ram1_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
136 fvp_mps2.sse200.ram2_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
137 fvp_mps2.sse200.ram2_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
138 fvp_mps2.sse200.ram3_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal
139 fvp_mps2.sse200.ram3_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision
140 fvp_mps2.sse200.iotss_cpuidentity.debugger_master_id=0xFFFFFFFF # (int , init-time) default = '0xFFFFFFFF' : : [0x0..0xFFFFFFFF]
141 fvp_mps2.sse200.iotss_internal_sram0.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
142 fvp_mps2.sse200.iotss_internal_sram0.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
143 fvp_mps2.sse200.iotss_internal_sram0.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
144 fvp_mps2.sse200.iotss_internal_sram1.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
145 fvp_mps2.sse200.iotss_internal_sram1.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
146 fvp_mps2.sse200.iotss_internal_sram1.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
147 fvp_mps2.sse200.iotss_internal_sram2.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
148 fvp_mps2.sse200.iotss_internal_sram2.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
149 fvp_mps2.sse200.iotss_internal_sram2.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
150 fvp_mps2.sse200.iotss_internal_sram3.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size
151 fvp_mps2.sse200.iotss_internal_sram3.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern
152 fvp_mps2.sse200.iotss_internal_sram3.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern
153 fvp_mps2.sse200.bus_error_warning_memory.read_data=0x0 # (int , init-time) default = '0x0' : Data to return on reads, if not aborting
154 fvp_mps2.sse200.exclusive_monitor_iotss_internal_sram.enable_component=1 # (bool , init-time) default = '1' : Enable component
155 fvp_mps2.sse200.exclusive_monitor_iotss_internal_sram.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF]
156 fvp_mps2.sse200.exclusive_monitor_iotss_internal_sram.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB]
157 fvp_mps2.sse200.exclusive_monitor_iotss_internal_sram.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master
158 fvp_mps2.sse200.exclusive_monitor_iotss_internal_sram.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit
159 fvp_mps2.sse200.exclusive_monitor_iotss_internal_sram.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3]
160 fvp_mps2.sse200.exclusive_monitor_iotss_internal_sram.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores
161 fvp_mps2.mps2_secure_control_register_block.FLASH_BLOCK_CFG=0x3 # (int , init-time) default = '0x3' : Flash Block size configuration : [0x0..0x31]
162 fvp_mps2.mps2_secure_control_register_block.SRAM_BLOCK_CFG=0x3 # (int , init-time) default = '0x3' : SRAM Block size configuration : [0x0..0x31]
163 fvp_mps2.mps2_secure_control_register_block.FLASH_WATERMARK_SUPPORTED=1 # (bool , init-time) default = '1' : Flash Watermark supported
164 fvp_mps2.mps2_secure_control_register_block.SRAM_WATERMARK_SUPPORTED=1 # (bool , init-time) default = '1' : SRAM Watermark supported
165 fvp_mps2.mps2_secure_control_register_block.APBPPCEXP_DIS0=0x0 # (int , init-time) default = '0x0' : Disables support for individual bits on the APBNSPPCEXP0 and APBPPPCEXP0 buses : [0x0..0xFFFF]
166 fvp_mps2.mps2_secure_control_register_block.APBPPCEXP_DIS1=0x0 # (int , init-time) default = '0x0' : Disables support for individual bits on the APBNSPPCEXP1 and APBPPPCEXP1 buses : [0x0..0xFFFF]
167 fvp_mps2.mps2_secure_control_register_block.APBPPCEXP_DIS2=0x0 # (int , init-time) default = '0x0' : Disables support for individual bits on the APBNSPPCEXP2 and APBPPPCEXP2 buses : [0x0..0xFFFF]
168 fvp_mps2.mps2_secure_control_register_block.APBPPCEXP_DIS3=0x0 # (int , init-time) default = '0x0' : Disables support for individual bits on the APBNSPPCEXP3 and APBPPPCEXP3 buses : [0x0..0xFFFF]
169 fvp_mps2.mps2_secure_control_register_block.AHBPPCEXP_DIS0=0x0 # (int , init-time) default = '0x0' : Disables support for individual bits on the AHBNSPPCEXP0 and AHBPPPCEXP0 buses : [0x0..0xFFFF]
170 fvp_mps2.mps2_secure_control_register_block.AHBPPCEXP_DIS1=0x0 # (int , init-time) default = '0x0' : Disables support for individual bits on the AHBNSPPCEXP1 and AHBPPPCEXP1 buses : [0x0..0xFFFF]
171 fvp_mps2.mps2_secure_control_register_block.AHBPPCEXP_DIS2=0x0 # (int , init-time) default = '0x0' : Disables support for individual bits on the AHBNSPPCEXP2 and AHBPPPCEXP2 buses : [0x0..0xFFFF]
172 fvp_mps2.mps2_secure_control_register_block.AHBPPCEXP_DIS3=0x0 # (int , init-time) default = '0x0' : Disables support for individual bits on the AHBNSPPCEXP3 and AHBPPPCEXP3 buses : [0x0..0xFFFF]
173 fvp_mps2.ahb_ppc_iotss_expansion0.NONSEC_MASK=0x0 # (int , init-time) default = '0x0' : 16-bit wide mask for security checking of ports: 0 = check, 1 = mask : [0x0..0x1]
174 fvp_mps2.ahb_ppc_iotss_expansion1.NONSEC_MASK=0x0 # (int , init-time) default = '0x0' : 16-bit wide mask for security checking of ports: 0 = check, 1 = mask : [0x0..0x1]
175 fvp_mps2.apb_ppc_iotss_expansion0.NONSEC_MASK=0x0 # (int , init-time) default = '0x0' : 16-bit wide mask for security checking of ports: 0 = check, 1 = mask : [0x0..0x1]
176 fvp_mps2.apb_ppc_iotss_expansion1.NONSEC_MASK=0x0 # (int , init-time) default = '0x0' : 16-bit wide mask for security checking of ports: 0 = check, 1 = mask : [0x0..0x1]
177 fvp_mps2.apb_ppc_iotss_expansion2.NONSEC_MASK=0x0 # (int , init-time) default = '0x0' : 16-bit wide mask for security checking of ports: 0 = check, 1 = mask : [0x0..0x1]
178 fvp_mps2.exclusive_monitor_psram.enable_component=1 # (bool , init-time) default = '1' : Enable component
179 fvp_mps2.exclusive_monitor_psram.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF]
180 fvp_mps2.exclusive_monitor_psram.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB]
181 fvp_mps2.exclusive_monitor_psram.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master
182 fvp_mps2.exclusive_monitor_psram.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit
183 fvp_mps2.exclusive_monitor_psram.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3]
184 fvp_mps2.exclusive_monitor_psram.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores
185 fvp_mps2.exclusive_monitor_psram_iotss.enable_component=1 # (bool , init-time) default = '1' : Enable component
186 fvp_mps2.exclusive_monitor_psram_iotss.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF]
187 fvp_mps2.exclusive_monitor_psram_iotss.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB]
188 fvp_mps2.exclusive_monitor_psram_iotss.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master
189 fvp_mps2.exclusive_monitor_psram_iotss.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit
190 fvp_mps2.exclusive_monitor_psram_iotss.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3]
191 fvp_mps2.exclusive_monitor_psram_iotss.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores
192 fvp_mps2.exclusive_monitor_zbtsram1.enable_component=1 # (bool , init-time) default = '1' : Enable component
193 fvp_mps2.exclusive_monitor_zbtsram1.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF]
194 fvp_mps2.exclusive_monitor_zbtsram1.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB]
195 fvp_mps2.exclusive_monitor_zbtsram1.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master
196 fvp_mps2.exclusive_monitor_zbtsram1.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit
197 fvp_mps2.exclusive_monitor_zbtsram1.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3]
198 fvp_mps2.exclusive_monitor_zbtsram1.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores
199 fvp_mps2.exclusive_monitor_zbtsram2.enable_component=1 # (bool , init-time) default = '1' : Enable component
200 fvp_mps2.exclusive_monitor_zbtsram2.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF]
201 fvp_mps2.exclusive_monitor_zbtsram2.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB]
202 fvp_mps2.exclusive_monitor_zbtsram2.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master
203 fvp_mps2.exclusive_monitor_zbtsram2.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit
204 fvp_mps2.exclusive_monitor_zbtsram2.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3]
205 fvp_mps2.exclusive_monitor_zbtsram2.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores
206 fvp_mps2.mps2_exclusive_monitor_zbtsram1.enable_component=1 # (bool , init-time) default = '1' : Enable component
207 fvp_mps2.mps2_exclusive_monitor_zbtsram1.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF]
208 fvp_mps2.mps2_exclusive_monitor_zbtsram1.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB]
209 fvp_mps2.mps2_exclusive_monitor_zbtsram1.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master
210 fvp_mps2.mps2_exclusive_monitor_zbtsram1.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit
211 fvp_mps2.mps2_exclusive_monitor_zbtsram1.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3]
212 fvp_mps2.mps2_exclusive_monitor_zbtsram1.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores
213 fvp_mps2.mps2_exclusive_monitor_zbtsram2.enable_component=1 # (bool , init-time) default = '1' : Enable component
214 fvp_mps2.mps2_exclusive_monitor_zbtsram2.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF]
215 fvp_mps2.mps2_exclusive_monitor_zbtsram2.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB]
216 fvp_mps2.mps2_exclusive_monitor_zbtsram2.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master
217 fvp_mps2.mps2_exclusive_monitor_zbtsram2.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit
218 fvp_mps2.mps2_exclusive_monitor_zbtsram2.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3]
219 fvp_mps2.mps2_exclusive_monitor_zbtsram2.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores
220 fvp_mps2.dma0_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S
221 fvp_mps2.dma1_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S
222 fvp_mps2.dma2_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S
223 fvp_mps2.dma3_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S
224 fvp_mps2.dma0.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes
225 fvp_mps2.dma0.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer
226 fvp_mps2.dma0.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response
227 fvp_mps2.dma0.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay
228 fvp_mps2.dma1.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes
229 fvp_mps2.dma1.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer
230 fvp_mps2.dma1.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response
231 fvp_mps2.dma1.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay
232 fvp_mps2.dma2.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes
233 fvp_mps2.dma2.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer
234 fvp_mps2.dma2.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response
235 fvp_mps2.dma2.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay
236 fvp_mps2.dma3.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes
237 fvp_mps2.dma3.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer
238 fvp_mps2.dma3.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response
239 fvp_mps2.dma3.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay
240 #----------------------------------------------------------------------------------------------
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